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SYSCTRL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

INTENCLR

XOSC

XOSC32K

OSC32K

OSCULP32K

OSC8M

DFLLCTRL

DFLLVAL

DFLLMUL

DFLLSYNC

BOD33

INTENSET

VREF

DPLLCTRLA

DPLLRATIO

DPLLCTRLB

DPLLSTATUS

INTFLAG

PCLKSR


INTENCLR

Interrupt Enable Clear
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOSCRDY XOSC32KRDY OSC32KRDY OSC8MRDY DFLLRDY DFLLOOB DFLLLCKF DFLLLCKC DFLLRCS BOD33RDY BOD33DET B33SRDY DPLLLCKR DPLLLCKF DPLLLTO

XOSCRDY : XOSC Ready Interrupt Enable
bits : 0 - 0 (1 bit)

XOSC32KRDY : XOSC32K Ready Interrupt Enable
bits : 1 - 1 (1 bit)

OSC32KRDY : OSC32K Ready Interrupt Enable
bits : 2 - 2 (1 bit)

OSC8MRDY : OSC8M Ready Interrupt Enable
bits : 3 - 3 (1 bit)

DFLLRDY : DFLL Ready Interrupt Enable
bits : 4 - 4 (1 bit)

DFLLOOB : DFLL Out Of Bounds Interrupt Enable
bits : 5 - 5 (1 bit)

DFLLLCKF : DFLL Lock Fine Interrupt Enable
bits : 6 - 6 (1 bit)

DFLLLCKC : DFLL Lock Coarse Interrupt Enable
bits : 7 - 7 (1 bit)

DFLLRCS : DFLL Reference Clock Stopped Interrupt Enable
bits : 8 - 8 (1 bit)

BOD33RDY : BOD33 Ready Interrupt Enable
bits : 9 - 9 (1 bit)

BOD33DET : BOD33 Detection Interrupt Enable
bits : 10 - 10 (1 bit)

B33SRDY : BOD33 Synchronization Ready Interrupt Enable
bits : 11 - 11 (1 bit)

DPLLLCKR : DPLL Lock Rise Interrupt Enable
bits : 15 - 15 (1 bit)

DPLLLCKF : DPLL Lock Fall Interrupt Enable
bits : 16 - 16 (1 bit)

DPLLLTO : DPLL Lock Timeout Interrupt Enable
bits : 17 - 17 (1 bit)


XOSC

External Multipurpose Crystal Oscillator (XOSC) Control
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XOSC XOSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE XTALEN RUNSTDBY ONDEMAND GAIN AMPGC STARTUP

ENABLE : Oscillator Enable
bits : 1 - 1 (1 bit)

XTALEN : Crystal Oscillator Enable
bits : 2 - 2 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)

GAIN : Oscillator Gain
bits : 8 - 10 (3 bit)

Enumeration: GAINSelect

0x0 : 0x0

2MHz

0x1 : 0x1

4MHz

0x2 : 0x2

8MHz

0x3 : 0x3

16MHz

0x4 : 0x4

30MHz

End of enumeration elements list.

AMPGC : Automatic Amplitude Gain Control
bits : 11 - 11 (1 bit)

STARTUP : Start-Up Time
bits : 12 - 15 (4 bit)


XOSC32K

32kHz External Crystal Oscillator (XOSC32K) Control
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XOSC32K XOSC32K read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE XTALEN EN32K EN1K AAMPEN RUNSTDBY ONDEMAND STARTUP WRTLOCK

ENABLE : Oscillator Enable
bits : 1 - 1 (1 bit)

XTALEN : Crystal Oscillator Enable
bits : 2 - 2 (1 bit)

EN32K : 32kHz Output Enable
bits : 3 - 3 (1 bit)

EN1K : 1kHz Output Enable
bits : 4 - 4 (1 bit)

AAMPEN : Automatic Amplitude Control Enable
bits : 5 - 5 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)

STARTUP : Oscillator Start-Up Time
bits : 8 - 10 (3 bit)

WRTLOCK : Write Lock
bits : 12 - 12 (1 bit)


OSC32K

32kHz Internal Oscillator (OSC32K) Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC32K OSC32K read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE EN32K EN1K RUNSTDBY ONDEMAND STARTUP WRTLOCK CALIB

ENABLE : Oscillator Enable
bits : 1 - 1 (1 bit)

EN32K : 32kHz Output Enable
bits : 2 - 2 (1 bit)

EN1K : 1kHz Output Enable
bits : 3 - 3 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)

STARTUP : Oscillator Start-Up Time
bits : 8 - 10 (3 bit)

WRTLOCK : Write Lock
bits : 12 - 12 (1 bit)

CALIB : Oscillator Calibration
bits : 16 - 22 (7 bit)


OSCULP32K

32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSCULP32K OSCULP32K read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CALIB WRTLOCK

CALIB : Oscillator Calibration
bits : 0 - 4 (5 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


OSC8M

8MHz Internal Oscillator (OSC8M) Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSC8M OSC8M read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RUNSTDBY ONDEMAND PRESC CALIB FRANGE

ENABLE : Oscillator Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)

PRESC : Oscillator Prescaler
bits : 8 - 9 (2 bit)

Enumeration: PRESCSelect

0x0 : 0x0

1

0x1 : 0x1

2

0x2 : 0x2

4

0x3 : 0x3

8

End of enumeration elements list.

CALIB : Oscillator Calibration
bits : 16 - 27 (12 bit)

FRANGE : Oscillator Frequency Range
bits : 30 - 31 (2 bit)

Enumeration: FRANGESelect

0x0 : 0x0

4 to 6MHz

0x1 : 0x1

6 to 8MHz

0x2 : 0x2

8 to 11MHz

0x3 : 0x3

11 to 15MHz

End of enumeration elements list.


DFLLCTRL

DFLL48M Control
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFLLCTRL DFLLCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE MODE STABLE LLAW USBCRM RUNSTDBY ONDEMAND CCDIS QLDIS BPLCKC WAITLOCK

ENABLE : DFLL Enable
bits : 1 - 1 (1 bit)

MODE : Operating Mode Selection
bits : 2 - 2 (1 bit)

STABLE : Stable DFLL Frequency
bits : 3 - 3 (1 bit)

LLAW : Lose Lock After Wake
bits : 4 - 4 (1 bit)

USBCRM : USB Clock Recovery Mode
bits : 5 - 5 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)

CCDIS : Chill Cycle Disable
bits : 8 - 8 (1 bit)

QLDIS : Quick Lock Disable
bits : 9 - 9 (1 bit)

BPLCKC : Bypass Coarse Lock
bits : 10 - 10 (1 bit)

WAITLOCK : Wait Lock
bits : 11 - 11 (1 bit)


DFLLVAL

DFLL48M Value
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFLLVAL DFLLVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FINE COARSE DIFF

FINE : Fine Value
bits : 0 - 9 (10 bit)

COARSE : Coarse Value
bits : 10 - 15 (6 bit)

DIFF : Multiplication Ratio Difference
bits : 16 - 31 (16 bit)
access : read-only


DFLLMUL

DFLL48M Multiplier
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFLLMUL DFLLMUL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUL FSTEP CSTEP

MUL : DFLL Multiply Factor
bits : 0 - 15 (16 bit)

FSTEP : Fine Maximum Step
bits : 16 - 25 (10 bit)

CSTEP : Coarse Maximum Step
bits : 26 - 31 (6 bit)


DFLLSYNC

DFLL48M Synchronization
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFLLSYNC DFLLSYNC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 READREQ

READREQ : Read Request
bits : 7 - 7 (1 bit)
access : write-only


BOD33

3.3V Brown-Out Detector (BOD33) Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOD33 BOD33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE HYST ACTION RUNSTDBY MODE CEN PSEL LEVEL

ENABLE : Enable
bits : 1 - 1 (1 bit)

HYST : Hysteresis
bits : 2 - 2 (1 bit)

ACTION : BOD33 Action
bits : 3 - 4 (2 bit)

Enumeration: ACTIONSelect

0x0 : NONE

No action

0x1 : RESET

The BOD33 generates a reset

0x2 : INTERRUPT

The BOD33 generates an interrupt

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

MODE : Operation Mode
bits : 8 - 8 (1 bit)

CEN : Clock Enable
bits : 9 - 9 (1 bit)

PSEL : Prescaler Select
bits : 12 - 15 (4 bit)

Enumeration: PSELSelect

0x0 : DIV2

Divide clock by 2

0x1 : DIV4

Divide clock by 4

0x2 : DIV8

Divide clock by 8

0x3 : DIV16

Divide clock by 16

0x4 : DIV32

Divide clock by 32

0x5 : DIV64

Divide clock by 64

0x6 : DIV128

Divide clock by 128

0x7 : DIV256

Divide clock by 256

0x8 : DIV512

Divide clock by 512

0x9 : DIV1K

Divide clock by 1024

0xa : DIV2K

Divide clock by 2048

0xb : DIV4K

Divide clock by 4096

0xc : DIV8K

Divide clock by 8192

0xd : DIV16K

Divide clock by 16384

0xe : DIV32K

Divide clock by 32768

0xf : DIV64K

Divide clock by 65536

End of enumeration elements list.

LEVEL : BOD33 Threshold Level
bits : 16 - 21 (6 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOSCRDY XOSC32KRDY OSC32KRDY OSC8MRDY DFLLRDY DFLLOOB DFLLLCKF DFLLLCKC DFLLRCS BOD33RDY BOD33DET B33SRDY DPLLLCKR DPLLLCKF DPLLLTO

XOSCRDY : XOSC Ready Interrupt Enable
bits : 0 - 0 (1 bit)

XOSC32KRDY : XOSC32K Ready Interrupt Enable
bits : 1 - 1 (1 bit)

OSC32KRDY : OSC32K Ready Interrupt Enable
bits : 2 - 2 (1 bit)

OSC8MRDY : OSC8M Ready Interrupt Enable
bits : 3 - 3 (1 bit)

DFLLRDY : DFLL Ready Interrupt Enable
bits : 4 - 4 (1 bit)

DFLLOOB : DFLL Out Of Bounds Interrupt Enable
bits : 5 - 5 (1 bit)

DFLLLCKF : DFLL Lock Fine Interrupt Enable
bits : 6 - 6 (1 bit)

DFLLLCKC : DFLL Lock Coarse Interrupt Enable
bits : 7 - 7 (1 bit)

DFLLRCS : DFLL Reference Clock Stopped Interrupt Enable
bits : 8 - 8 (1 bit)

BOD33RDY : BOD33 Ready Interrupt Enable
bits : 9 - 9 (1 bit)

BOD33DET : BOD33 Detection Interrupt Enable
bits : 10 - 10 (1 bit)

B33SRDY : BOD33 Synchronization Ready Interrupt Enable
bits : 11 - 11 (1 bit)

DPLLLCKR : DPLL Lock Rise Interrupt Enable
bits : 15 - 15 (1 bit)

DPLLLCKF : DPLL Lock Fall Interrupt Enable
bits : 16 - 16 (1 bit)

DPLLLTO : DPLL Lock Timeout Interrupt Enable
bits : 17 - 17 (1 bit)


VREF

Voltage References System (VREF) Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREF VREF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSEN BGOUTEN CALIB

TSEN : Temperature Sensor Enable
bits : 1 - 1 (1 bit)

BGOUTEN : Bandgap Output Enable
bits : 2 - 2 (1 bit)

CALIB : Bandgap Voltage Generator Calibration
bits : 16 - 26 (11 bit)


DPLLCTRLA

DPLL Control A
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPLLCTRLA DPLLCTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ENABLE RUNSTDBY ONDEMAND

ENABLE : DPLL Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

ONDEMAND : On Demand Clock Activation
bits : 7 - 7 (1 bit)


DPLLRATIO

DPLL Ratio Control
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPLLRATIO DPLLRATIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LDR LDRFRAC

LDR : Loop Divider Ratio
bits : 0 - 11 (12 bit)

LDRFRAC : Loop Divider Ratio Fractional Part
bits : 16 - 19 (4 bit)


DPLLCTRLB

DPLL Control B
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPLLCTRLB DPLLCTRLB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILTER LPEN WUF REFCLK LTIME LBYPASS DIV

FILTER : Proportional Integral Filter Selection
bits : 0 - 1 (2 bit)

Enumeration: FILTERSelect

0x0 : DEFAULT

Default filter mode

0x1 : LBFILT

Low bandwidth filter

0x2 : HBFILT

High bandwidth filter

0x3 : HDFILT

High damping filter

End of enumeration elements list.

LPEN : Low-Power Enable
bits : 2 - 2 (1 bit)

WUF : Wake Up Fast
bits : 3 - 3 (1 bit)

REFCLK : Reference Clock Selection
bits : 4 - 5 (2 bit)

Enumeration: REFCLKSelect

0x0 : REF0

CLK_DPLL_REF0 clock reference

0x1 : REF1

CLK_DPLL_REF1 clock reference

0x2 : GCLK

GCLK_DPLL clock reference

End of enumeration elements list.

LTIME : Lock Time
bits : 8 - 10 (3 bit)

Enumeration: LTIMESelect

0x0 : 0x0

Default No time-out

0x4 : 0x4

8MS Time-out if no lock within 8 ms

0x5 : 0x5

9MS Time-out if no lock within 9 ms

0x6 : 0x6

10MS Time-out if no lock within 10 ms

0x7 : 0x7

11MS Time-out if no lock within 11 ms

End of enumeration elements list.

LBYPASS : Lock Bypass
bits : 12 - 12 (1 bit)

DIV : Clock Divider
bits : 16 - 26 (11 bit)


DPLLSTATUS

DPLL Status
address_offset : 0x50 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DPLLSTATUS DPLLSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LOCK CLKRDY ENABLE DIV

LOCK : DPLL Lock Status
bits : 0 - 0 (1 bit)
access : read-only

CLKRDY : Output Clock Ready
bits : 1 - 1 (1 bit)
access : read-only

ENABLE : DPLL Enable
bits : 2 - 2 (1 bit)
access : read-only

DIV : Divider Enable
bits : 3 - 3 (1 bit)
access : read-only


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOSCRDY XOSC32KRDY OSC32KRDY OSC8MRDY DFLLRDY DFLLOOB DFLLLCKF DFLLLCKC DFLLRCS BOD33RDY BOD33DET B33SRDY DPLLLCKR DPLLLCKF DPLLLTO

XOSCRDY : XOSC Ready
bits : 0 - 0 (1 bit)

XOSC32KRDY : XOSC32K Ready
bits : 1 - 1 (1 bit)

OSC32KRDY : OSC32K Ready
bits : 2 - 2 (1 bit)

OSC8MRDY : OSC8M Ready
bits : 3 - 3 (1 bit)

DFLLRDY : DFLL Ready
bits : 4 - 4 (1 bit)

DFLLOOB : DFLL Out Of Bounds
bits : 5 - 5 (1 bit)

DFLLLCKF : DFLL Lock Fine
bits : 6 - 6 (1 bit)

DFLLLCKC : DFLL Lock Coarse
bits : 7 - 7 (1 bit)

DFLLRCS : DFLL Reference Clock Stopped
bits : 8 - 8 (1 bit)

BOD33RDY : BOD33 Ready
bits : 9 - 9 (1 bit)

BOD33DET : BOD33 Detection
bits : 10 - 10 (1 bit)

B33SRDY : BOD33 Synchronization Ready
bits : 11 - 11 (1 bit)

DPLLLCKR : DPLL Lock Rise
bits : 15 - 15 (1 bit)

DPLLLCKF : DPLL Lock Fall
bits : 16 - 16 (1 bit)

DPLLLTO : DPLL Lock Timeout
bits : 17 - 17 (1 bit)


PCLKSR

Power and Clocks Status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCLKSR PCLKSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOSCRDY XOSC32KRDY OSC32KRDY OSC8MRDY DFLLRDY DFLLOOB DFLLLCKF DFLLLCKC DFLLRCS BOD33RDY BOD33DET B33SRDY DPLLLCKR DPLLLCKF DPLLLTO

XOSCRDY : XOSC Ready
bits : 0 - 0 (1 bit)
access : read-only

XOSC32KRDY : XOSC32K Ready
bits : 1 - 1 (1 bit)
access : read-only

OSC32KRDY : OSC32K Ready
bits : 2 - 2 (1 bit)
access : read-only

OSC8MRDY : OSC8M Ready
bits : 3 - 3 (1 bit)
access : read-only

DFLLRDY : DFLL Ready
bits : 4 - 4 (1 bit)
access : read-only

DFLLOOB : DFLL Out Of Bounds
bits : 5 - 5 (1 bit)
access : read-only

DFLLLCKF : DFLL Lock Fine
bits : 6 - 6 (1 bit)
access : read-only

DFLLLCKC : DFLL Lock Coarse
bits : 7 - 7 (1 bit)
access : read-only

DFLLRCS : DFLL Reference Clock Stopped
bits : 8 - 8 (1 bit)
access : read-only

BOD33RDY : BOD33 Ready
bits : 9 - 9 (1 bit)
access : read-only

BOD33DET : BOD33 Detection
bits : 10 - 10 (1 bit)
access : read-only

B33SRDY : BOD33 Synchronization Ready
bits : 11 - 11 (1 bit)
access : read-only

DPLLLCKR : DPLL Lock Rise
bits : 15 - 15 (1 bit)
access : read-only

DPLLLCKF : DPLL Lock Fall
bits : 16 - 16 (1 bit)
access : read-only

DPLLLTO : DPLL Lock Timeout
bits : 17 - 17 (1 bit)
access : read-only



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