\n

USART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SR

CR2

CR3

DR

BRR

CR1


SR

UART4_SR
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE FE NE ORE IDLE RXNE TC TXE LBD

PE : PE
bits : 0 - 0 (1 bit)
access : read-only

FE : FE
bits : 1 - 1 (1 bit)
access : read-only

NE : NE
bits : 2 - 2 (1 bit)
access : read-only

ORE : ORE
bits : 3 - 3 (1 bit)
access : read-only

IDLE : IDLE
bits : 4 - 4 (1 bit)
access : read-only

RXNE : RXNE
bits : 5 - 5 (1 bit)
access : read-write

TC : TC
bits : 6 - 6 (1 bit)
access : read-write

TXE : TXE
bits : 7 - 7 (1 bit)
access : read-only

LBD : LBD
bits : 8 - 8 (1 bit)
access : read-write


CR2

UART4_CR2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD LBDL LBDIE STOP LINEN

ADD : ADD
bits : 0 - 3 (4 bit)

LBDL : LBDL
bits : 5 - 5 (1 bit)

LBDIE : LBDIE
bits : 6 - 6 (1 bit)

STOP : STOP
bits : 12 - 13 (2 bit)

LINEN : LINEN
bits : 14 - 14 (1 bit)


CR3

UART4_CR3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR3 CR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EIE IREN IRLP HDSEL DMAT

EIE : Error interrupt enable
bits : 0 - 0 (1 bit)

IREN : IrDA mode enable
bits : 1 - 1 (1 bit)

IRLP : IrDA low-power
bits : 2 - 2 (1 bit)

HDSEL : Half-duplex selection
bits : 3 - 3 (1 bit)

DMAT : DMA enable transmitter
bits : 7 - 7 (1 bit)


DR

UART4_DR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR

DR : DR
bits : 0 - 8 (9 bit)


BRR

UART4_BRR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRR BRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_Fraction DIV_Mantissa

DIV_Fraction : DIV_Fraction
bits : 0 - 3 (4 bit)

DIV_Mantissa : DIV_Mantissa
bits : 4 - 15 (12 bit)


CR1

UART4_CR1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBK RWU RE TE IDLEIE RXNEIE TCIE TXEIE PEIE PS PCE WAKE M UE

SBK : SBK
bits : 0 - 0 (1 bit)

RWU : RWU
bits : 1 - 1 (1 bit)

RE : RE
bits : 2 - 2 (1 bit)

TE : TE
bits : 3 - 3 (1 bit)

IDLEIE : IDLEIE
bits : 4 - 4 (1 bit)

RXNEIE : RXNEIE
bits : 5 - 5 (1 bit)

TCIE : TCIE
bits : 6 - 6 (1 bit)

TXEIE : TXEIE
bits : 7 - 7 (1 bit)

PEIE : PEIE
bits : 8 - 8 (1 bit)

PS : PS
bits : 9 - 9 (1 bit)

PCE : PCE
bits : 10 - 10 (1 bit)

WAKE : WAKE
bits : 11 - 11 (1 bit)

M : M
bits : 12 - 12 (1 bit)

UE : UE
bits : 13 - 13 (1 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.