\n
address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected
Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only
CRC : 32-bit Cyclic Redundancy Code
bits : 2 - 2 (1 bit)
access : write-only
MBIST : Memory built-in self-test
bits : 3 - 3 (1 bit)
access : write-only
CE : Chip-Erase
bits : 4 - 4 (1 bit)
access : write-only
ARR : Auxiliary Row Read
bits : 6 - 6 (1 bit)
access : write-only
SMSA : Start Memory Stream Access
bits : 7 - 7 (1 bit)
access : write-only
Status A
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DONE : Done
bits : 0 - 0 (1 bit)
CRSTEXT : CPU Reset Phase Extension
bits : 1 - 1 (1 bit)
BERR : Bus Error
bits : 2 - 2 (1 bit)
FAIL : Failure
bits : 3 - 3 (1 bit)
PERR : Protection Error
bits : 4 - 4 (1 bit)
Coresight ROM Table End
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
END : End Marker
bits : 0 - 31 (32 bit)
Device Identification
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEVSEL : Device Select
bits : 0 - 7 (8 bit)
access : read-only
REVISION : Revision Number
bits : 8 - 11 (4 bit)
access : read-only
DIE : Die Number
bits : 12 - 15 (4 bit)
access : read-only
SERIES : Series
bits : 16 - 21 (6 bit)
access : read-only
Enumeration: SERIESSelect
0x0 : 0
Cortex-M0+ processor, basic feature set
0x1 : 1
Cortex-M0+ processor, USB
End of enumeration elements list.
FAMILY : Family
bits : 23 - 27 (5 bit)
access : read-only
Enumeration: FAMILYSelect
0x0 : 0
General purpose microcontroller
0x1 : 1
PicoPower
End of enumeration elements list.
PROCESSOR : Processor
bits : 28 - 31 (4 bit)
access : read-only
Enumeration: PROCESSORSelect
0x0 : 0
Cortex-M0
0x1 : 1
Cortex-M0+
0x2 : 2
Cortex-M3
0x3 : 3
Cortex-M4
End of enumeration elements list.
Device Configuration
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCFG : Device Configuration
bits : 0 - 31 (32 bit)
Coresight ROM Table Memory Type
address_offset : 0x1FCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SMEMP : System Memory Present
bits : 0 - 0 (1 bit)
Peripheral Identification 4
address_offset : 0x1FD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEPCC : JEP-106 Continuation Code
bits : 0 - 3 (4 bit)
FKBC : 4KB count
bits : 4 - 7 (4 bit)
access : read-only
Peripheral Identification 5
address_offset : 0x1FD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification 6
address_offset : 0x1FD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification 7
address_offset : 0x1FDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral Identification 0
address_offset : 0x1FE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PARTNBL : Part Number Low
bits : 0 - 7 (8 bit)
Peripheral Identification 1
address_offset : 0x1FE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PARTNBH : Part Number High
bits : 0 - 3 (4 bit)
JEPIDCL : Low part of the JEP-106 Identity Code
bits : 4 - 7 (4 bit)
access : read-only
Peripheral Identification 2
address_offset : 0x1FE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JEPIDCH : JEP-106 Identity Code High
bits : 0 - 2 (3 bit)
JEPU : JEP-106 Identity Code is used
bits : 3 - 3 (1 bit)
access : read-only
REVISION : Revision Number
bits : 4 - 7 (4 bit)
access : read-only
Peripheral Identification 3
address_offset : 0x1FEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CUSMOD : ARM CUSMOD
bits : 0 - 3 (4 bit)
REVAND : Revision Number
bits : 4 - 7 (4 bit)
access : read-only
Component Identification 0
address_offset : 0x1FF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLEB0 : Preamble Byte 0
bits : 0 - 7 (8 bit)
access : read-only
Component Identification 1
address_offset : 0x1FF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLE : Preamble
bits : 0 - 3 (4 bit)
access : read-only
CCLASS : Component Class
bits : 4 - 7 (4 bit)
access : read-only
Component Identification 2
address_offset : 0x1FF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLEB2 : Preamble Byte 2
bits : 0 - 7 (8 bit)
access : read-only
Component Identification 3
address_offset : 0x1FFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PREAMBLEB3 : Preamble Byte 3
bits : 0 - 7 (8 bit)
Status B
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PROT : Protected
bits : 0 - 0 (1 bit)
DBGPRES : Debugger Present
bits : 1 - 1 (1 bit)
DCCD0 : Debug Communication Channel 0 Dirty
bits : 2 - 2 (1 bit)
DCCD1 : Debug Communication Channel 1 Dirty
bits : 3 - 3 (1 bit)
HPE : Hot-Plugging Enable
bits : 4 - 4 (1 bit)
Debug Communication Channel n
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
Coresight ROM Table Entry n
address_offset : 0x2000 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPRES : Entry Present
bits : 0 - 0 (1 bit)
FMT : Format
bits : 1 - 1 (1 bit)
access : read-only
ADDOFF : Address Offset
bits : 12 - 31 (20 bit)
access : read-only
Device Configuration
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCFG : Device Configuration
bits : 0 - 31 (32 bit)
Coresight ROM Table Entry n
address_offset : 0x3004 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPRES : Entry Present
bits : 0 - 0 (1 bit)
FMT : Format
bits : 1 - 1 (1 bit)
access : read-only
ADDOFF : Address Offset
bits : 12 - 31 (20 bit)
access : read-only
Debug Communication Channel n
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
Address
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AMOD : Access Mode
bits : 0 - 1 (2 bit)
ADDR : Address
bits : 2 - 31 (30 bit)
Length
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LENGTH : Length
bits : 2 - 31 (30 bit)
Data
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
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