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TWIHS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

CWGR

RPR

RCR

TPR

TCR

RNPR

RNCR

TNPR

TNCR

PTCR

PTSR

SR

IER

IDR

IMR

RHR

THR

SMBTR

MMR

ACR

FILTR

SMR

IADR

WPMR

WPSR


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP MSEN MSDIS SVEN SVDIS QUICK SWRST HSEN HSDIS SMBEN SMBDIS PECEN PECDIS PECRQ CLEAR

START : Send a START Condition
bits : 0 - 0 (1 bit)
access : write-only

STOP : Send a STOP Condition
bits : 1 - 1 (1 bit)
access : write-only

MSEN : TWI Master Mode Enabled
bits : 2 - 2 (1 bit)
access : write-only

MSDIS : TWI Master Mode Disabled
bits : 3 - 3 (1 bit)
access : write-only

SVEN : TWI Slave Mode Enabled
bits : 4 - 4 (1 bit)
access : write-only

SVDIS : TWI Slave Mode Disabled
bits : 5 - 5 (1 bit)
access : write-only

QUICK : SMBUS Quick Command
bits : 6 - 6 (1 bit)
access : write-only

SWRST : Software Reset
bits : 7 - 7 (1 bit)
access : write-only

HSEN : TWI High-Speed Mode Enabled
bits : 8 - 8 (1 bit)
access : write-only

HSDIS : TWI High-Speed Mode Disabled
bits : 9 - 9 (1 bit)
access : write-only

SMBEN : SMBus Mode Enabled
bits : 10 - 10 (1 bit)
access : write-only

SMBDIS : SMBus Mode Disabled
bits : 11 - 11 (1 bit)
access : write-only

PECEN : Packet Error Checking Enable
bits : 12 - 12 (1 bit)
access : write-only

PECDIS : Packet Error Checking Disable
bits : 13 - 13 (1 bit)
access : write-only

PECRQ : PEC Request
bits : 14 - 14 (1 bit)
access : write-only

CLEAR : Bus CLEAR Command
bits : 15 - 15 (1 bit)
access : write-only


CWGR

Clock Waveform Generator Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CWGR CWGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLDIV CHDIV CKDIV HOLD

CLDIV : Clock Low Divider
bits : 0 - 7 (8 bit)
access : read-write

CHDIV : Clock High Divider
bits : 8 - 15 (8 bit)
access : read-write

CKDIV : Clock Divider
bits : 16 - 18 (3 bit)
access : read-write

HOLD : TWD Hold Time Versus TWCK Falling
bits : 24 - 28 (5 bit)
access : read-write


RPR

Receive Pointer Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPR RPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPTR

RXPTR : Receive Pointer Register
bits : 0 - 31 (32 bit)
access : read-write


RCR

Receive Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCTR

RXCTR : Receive Counter Register
bits : 0 - 15 (16 bit)
access : read-write


TPR

Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPR TPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPTR

TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write


TCR

Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCTR

TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write


RNPR

Receive Next Pointer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNPR RNPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNPTR

RXNPTR : Receive Next Pointer
bits : 0 - 31 (32 bit)
access : read-write


RNCR

Receive Next Counter Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNCR RNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNCTR

RXNCTR : Receive Next Counter
bits : 0 - 15 (16 bit)
access : read-write


TNPR

Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNPR TNPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXNPTR

TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write


TNCR

Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNCR TNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXNCTR

TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write


PTCR

Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PTCR PTCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN RXTDIS TXTEN TXTDIS

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only

RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only

TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only


PTSR

Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PTSR PTSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN TXTEN

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only


SR

Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVREAD SVACC GACC OVRE UNRE NACK ARBLST SCLWS EOSACC ENDRX ENDTX RXBUFF TXBUFE MCACK TOUT PECERR SMBDAM SMBHHM SCL SDA

TXCOMP : Transmission Completed (automatically set / reset)
bits : 0 - 0 (1 bit)
access : read-only

RXRDY : Receive Holding Register Ready (automatically set / reset)
bits : 1 - 1 (1 bit)
access : read-only

TXRDY : Transmit Holding Register Ready (automatically set / reset)
bits : 2 - 2 (1 bit)
access : read-only

SVREAD : Slave Read (automatically set / reset)
bits : 3 - 3 (1 bit)
access : read-only

SVACC : Slave Access (automatically set / reset)
bits : 4 - 4 (1 bit)
access : read-only

GACC : General Call Access (clear on read)
bits : 5 - 5 (1 bit)
access : read-only

OVRE : Overrun Error (clear on read)
bits : 6 - 6 (1 bit)
access : read-only

UNRE : Underrun Error (clear on read)
bits : 7 - 7 (1 bit)
access : read-only

NACK : Not Acknowledged (clear on read)
bits : 8 - 8 (1 bit)
access : read-only

ARBLST : Arbitration Lost (clear on read)
bits : 9 - 9 (1 bit)
access : read-only

SCLWS : Clock Wait State (automatically set / reset)
bits : 10 - 10 (1 bit)
access : read-only

EOSACC : End Of Slave Access (clear on read)
bits : 11 - 11 (1 bit)
access : read-only

ENDRX : End of RX Buffer
bits : 12 - 12 (1 bit)
access : read-only

ENDTX : End of TX Buffer
bits : 13 - 13 (1 bit)
access : read-only

RXBUFF : RX Buffer Full
bits : 14 - 14 (1 bit)
access : read-only

TXBUFE : TX Buffer Empty
bits : 15 - 15 (1 bit)
access : read-only

MCACK : Master Code Acknowledge
bits : 16 - 16 (1 bit)
access : read-only

TOUT : Timeout Error
bits : 18 - 18 (1 bit)
access : read-only

PECERR : PEC Error
bits : 19 - 19 (1 bit)
access : read-only

SMBDAM : SMBus Default Address Match
bits : 20 - 20 (1 bit)
access : read-only

SMBHHM : SMBus Host Header Address Match
bits : 21 - 21 (1 bit)
access : read-only

SCL : SCL line value
bits : 24 - 24 (1 bit)
access : read-only

SDA : SDA line value
bits : 25 - 25 (1 bit)
access : read-only


IER

Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE UNRE NACK ARBLST SCL_WS EOSACC ENDRX ENDTX RXBUFF TXBUFE MCACK TOUT PECERR SMBDAM SMBHHM

TXCOMP : Transmission Completed Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXRDY : Receive Holding Register Ready Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXRDY : Transmit Holding Register Ready Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

SVACC : Slave Access Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

GACC : General Call Access Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

UNRE : Underrun Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NACK : Not Acknowledge Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

ARBLST : Arbitration Lost Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

SCL_WS : Clock Wait State Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

EOSACC : End Of Slave Access Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

ENDRX : End of Receive Buffer Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

ENDTX : End of Transmit Buffer Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

RXBUFF : Receive Buffer Full Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

TXBUFE : Transmit Buffer Empty Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only

MCACK : Master Code Acknowledge Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only

TOUT : Timeout Error Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

PECERR : PEC Error Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only

SMBDAM : SMBus Default Address Match Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only

SMBHHM : SMBus Host Header Address Match Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE UNRE NACK ARBLST SCL_WS EOSACC ENDRX ENDTX RXBUFF TXBUFE MCACK TOUT PECERR SMBDAM SMBHHM

TXCOMP : Transmission Completed Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

RXRDY : Receive Holding Register Ready Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXRDY : Transmit Holding Register Ready Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

SVACC : Slave Access Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

GACC : General Call Access Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

UNRE : Underrun Error Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NACK : Not Acknowledge Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

ARBLST : Arbitration Lost Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

SCL_WS : Clock Wait State Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

EOSACC : End Of Slave Access Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

ENDRX : End of Receive Buffer Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

ENDTX : End of Transmit Buffer Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

RXBUFF : Receive Buffer Full Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

TXBUFE : Transmit Buffer Empty Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only

MCACK : Master Code Acknowledge Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only

TOUT : Timeout Error Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

PECERR : PEC Error Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only

SMBDAM : SMBus Default Address Match Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only

SMBHHM : SMBus Host Header Address Match Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE UNRE NACK ARBLST SCL_WS EOSACC ENDRX ENDTX RXBUFF TXBUFE MCACK TOUT PECERR SMBDAM SMBHHM

TXCOMP : Transmission Completed Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

RXRDY : Receive Holding Register Ready Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

TXRDY : Transmit Holding Register Ready Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

SVACC : Slave Access Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only

GACC : General Call Access Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

OVRE : Overrun Error Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only

UNRE : Underrun Error Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only

NACK : Not Acknowledge Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only

ARBLST : Arbitration Lost Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only

SCL_WS : Clock Wait State Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only

EOSACC : End Of Slave Access Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only

ENDRX : End of Receive Buffer Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only

ENDTX : End of Transmit Buffer Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only

RXBUFF : Receive Buffer Full Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only

TXBUFE : Transmit Buffer Empty Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only

MCACK : Master Code Acknowledge Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only

TOUT : Timeout Error Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only

PECERR : PEC Error Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only

SMBDAM : SMBus Default Address Match Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only

SMBHHM : SMBus Host Header Address Match Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only


RHR

Receive Holding Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RHR RHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : Master or Slave Receive Holding Data
bits : 0 - 7 (8 bit)
access : read-only


THR

Transmit Holding Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

THR THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : Master or Slave Transmit Holding Data
bits : 0 - 7 (8 bit)
access : write-only


SMBTR

SMBus Timing Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMBTR SMBTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC TLOWS TLOWM THMAX

PRESC : SMBus Clock Prescaler
bits : 0 - 3 (4 bit)
access : read-write

TLOWS : Slave Clock Stretch Maximum Cycles
bits : 8 - 15 (8 bit)
access : read-write

TLOWM : Master Clock Stretch Maximum Cycles
bits : 16 - 23 (8 bit)
access : read-write

THMAX : Clock High Maximum Cycles
bits : 24 - 31 (8 bit)
access : read-write


MMR

Master Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMR MMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IADRSZ MREAD DADR

IADRSZ : Internal Device Address Size
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No internal device address

0x1 : 1_BYTE

One-byte internal device address

0x2 : 2_BYTE

Two-byte internal device address

0x3 : 3_BYTE

Three-byte internal device address

End of enumeration elements list.

MREAD : Master Read Direction
bits : 12 - 12 (1 bit)
access : read-write

DADR : Device Address
bits : 16 - 22 (7 bit)
access : read-write


ACR

Alternative Command Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FILTR

Filter Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FILTR FILTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILT PADFEN PADFCFG THRES

FILT : RX Digital Filter
bits : 0 - 0 (1 bit)
access : read-write

PADFEN : PAD Filter Enable
bits : 1 - 1 (1 bit)
access : read-write

PADFCFG : PAD Filter Config
bits : 2 - 2 (1 bit)
access : read-write

THRES : Digital Filter Threshold
bits : 8 - 10 (3 bit)
access : read-write


SMR

Slave Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMR SMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NACKEN SMDA SMHH SCLWSDIS MASK SADR

NACKEN : Slave Receiver Data Phase NACK enable
bits : 0 - 0 (1 bit)
access : read-write

SMDA : SMBus Default Address
bits : 2 - 2 (1 bit)
access : read-write

SMHH : SMBus Host Header
bits : 3 - 3 (1 bit)
access : read-write

SCLWSDIS : Clock Wait State Disable
bits : 6 - 6 (1 bit)
access : read-write

MASK : Slave Address Mask
bits : 8 - 14 (7 bit)
access : read-write

SADR : Slave Address
bits : 16 - 22 (7 bit)
access : read-write


IADR

Internal Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IADR IADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IADR

IADR : Internal Address
bits : 0 - 23 (24 bit)
access : read-write


WPMR

Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x545749 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0

End of enumeration elements list.


WPSR

Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protect Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protection Violation Source
bits : 8 - 31 (24 bit)
access : read-only



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