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USART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

CR_SPI_MODE

IMR

IMR_SPI_MODE

RPR

RCR

TPR

TCR

RNPR

RNCR

TNPR

TNCR

PTCR

PTSR

CSR

CSR_SPI_MODE

RHR

THR

BRGR

RTOR

TTGR

MR

MR_SPI_MODE

NER

IER

IER_SPI_MODE

IDR

IDR_SPI_MODE

WPMR

WPSR


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTRX RSTTX RXEN RXDIS TXEN TXDIS RSTSTA STTBRK STPBRK STTTO SENDA RETTO RTSEN RTSDIS

RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
access : write-only

RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
access : write-only

RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
access : write-only

RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
access : write-only

TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
access : write-only

TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
access : write-only

RSTSTA : Reset Status Bits
bits : 8 - 8 (1 bit)
access : write-only

STTBRK : Start Break
bits : 9 - 9 (1 bit)
access : write-only

STPBRK : Stop Break
bits : 10 - 10 (1 bit)
access : write-only

STTTO : Clear TIMEOUT Flag and Start Time-out After Next Character Received
bits : 11 - 11 (1 bit)
access : write-only

SENDA : Send Address
bits : 12 - 12 (1 bit)
access : write-only

RETTO : Start Time-out Immediately
bits : 15 - 15 (1 bit)
access : write-only

RTSEN : Request to Send Pin Control
bits : 18 - 18 (1 bit)
access : write-only

RTSDIS : Request to Send Pin Control
bits : 19 - 19 (1 bit)
access : write-only


CR_SPI_MODE

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0

CR_SPI_MODE CR_SPI_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTRX RSTTX RXEN RXDIS TXEN TXDIS RSTSTA FCS RCS

RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
access : write-only

RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
access : write-only

RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
access : write-only

RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
access : write-only

TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
access : write-only

TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
access : write-only

RSTSTA : Reset Status Bits
bits : 8 - 8 (1 bit)
access : write-only

FCS : Force SPI Chip Select
bits : 18 - 18 (1 bit)
access : write-only

RCS : Release SPI Chip Select
bits : 19 - 19 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY RXBRK ENDRX ENDTX OVRE FRAME PARE TIMEOUT TXEMPTY TXBUFE RXBUFF CTSIC

RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

RXBRK : Receiver Break Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

ENDRX : End of Receive Buffer Interrupt Mask (available in all USART modes of operation)
bits : 3 - 3 (1 bit)
access : read-only

ENDTX : End of Transmit Buffer Interrupt Mask (available in all USART modes of operation)
bits : 4 - 4 (1 bit)
access : read-only

OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

FRAME : Framing Error Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only

PARE : Parity Error Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only

TIMEOUT : Time-out Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only

TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only

TXBUFE : Transmit Buffer Empty Interrupt Mask (available in all USART modes of operation)
bits : 11 - 11 (1 bit)
access : read-only

RXBUFF : Receive Buffer Full Interrupt Mask (available in all USART modes of operation)
bits : 12 - 12 (1 bit)
access : read-only

CTSIC : Clear to Send Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only


IMR_SPI_MODE

Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0

IMR_SPI_MODE IMR_SPI_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE TXEMPTY UNRE TXBUFE RXBUFF

RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

ENDRX :
bits : 3 - 3 (1 bit)
access : read-only

ENDTX :
bits : 4 - 4 (1 bit)
access : read-only

OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only

UNRE : SPI Underrun Error Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only

TXBUFE :
bits : 11 - 11 (1 bit)
access : read-only

RXBUFF :
bits : 12 - 12 (1 bit)
access : read-only


RPR

Receive Pointer Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPR RPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPTR

RXPTR : Receive Pointer Register
bits : 0 - 31 (32 bit)
access : read-write


RCR

Receive Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCTR

RXCTR : Receive Counter Register
bits : 0 - 15 (16 bit)
access : read-write


TPR

Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPR TPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPTR

TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write


TCR

Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCTR

TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write


RNPR

Receive Next Pointer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNPR RNPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNPTR

RXNPTR : Receive Next Pointer
bits : 0 - 31 (32 bit)
access : read-write


RNCR

Receive Next Counter Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNCR RNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNCTR

RXNCTR : Receive Next Counter
bits : 0 - 15 (16 bit)
access : read-write


TNPR

Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNPR TNPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXNPTR

TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write


TNCR

Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNCR TNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXNCTR

TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write


PTCR

Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PTCR PTCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN RXTDIS TXTEN TXTDIS RXCBEN RXCBDIS TXCBEN TXCBDIS ERRCLR

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only

RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only

TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only

RXCBEN : Receiver Circular Buffer Enable
bits : 16 - 16 (1 bit)
access : write-only

RXCBDIS : Receiver Circular Buffer Disable
bits : 17 - 17 (1 bit)
access : write-only

TXCBEN : Transmitter Circular Buffer Enable
bits : 18 - 18 (1 bit)
access : write-only

TXCBDIS : Transmitter Circular Buffer Disable
bits : 19 - 19 (1 bit)
access : write-only

ERRCLR : Transfer Bus Error Clear
bits : 24 - 24 (1 bit)
access : write-only


PTSR

Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PTSR PTSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN TXTEN RXCBEN TXCBEN ERR

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only

RXCBEN : Receiver Circular Buffer Enable
bits : 16 - 16 (1 bit)
access : read-only

TXCBEN : Transmitter Circular Buffer Enable
bits : 18 - 18 (1 bit)
access : read-only

ERR : Transfer Bus Error
bits : 24 - 24 (1 bit)
access : read-only


CSR

Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY RXBRK ENDRX ENDTX OVRE FRAME PARE TIMEOUT TXEMPTY TXBUFE RXBUFF CTSIC CTS

RXRDY : Receiver Ready (cleared by reading US_RHR)
bits : 0 - 0 (1 bit)
access : read-only

TXRDY : Transmitter Ready (cleared by writing US_THR)
bits : 1 - 1 (1 bit)
access : read-only

RXBRK : Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA)
bits : 2 - 2 (1 bit)
access : read-only

ENDRX : End of RX Buffer (cleared by writing US_RCR or US_RNCR)
bits : 3 - 3 (1 bit)
access : read-only

ENDTX : End of TX Buffer (cleared by writing US_TCR or US_TNCR)
bits : 4 - 4 (1 bit)
access : read-only

OVRE : Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 5 - 5 (1 bit)
access : read-only

FRAME : Framing Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 6 - 6 (1 bit)
access : read-only

PARE : Parity Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 7 - 7 (1 bit)
access : read-only

TIMEOUT : Receiver Time-out (cleared by writing a one to bit US_CR.STTTO)
bits : 8 - 8 (1 bit)
access : read-only

TXEMPTY : Transmitter Empty (cleared by writing US_THR)
bits : 9 - 9 (1 bit)
access : read-only

TXBUFE : TX Buffer Empty (cleared by writing US_TCR or US_TNCR)
bits : 11 - 11 (1 bit)
access : read-only

RXBUFF : RX Buffer Full (cleared by writing US_RCR or US_RNCR)
bits : 12 - 12 (1 bit)
access : read-only

CTSIC : Clear to Send Input Change Flag (cleared on read)
bits : 19 - 19 (1 bit)
access : read-only

CTS : Image of CTS Input
bits : 23 - 23 (1 bit)
access : read-only


CSR_SPI_MODE

Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0

CSR_SPI_MODE CSR_SPI_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE TXEMPTY UNRE TXBUFE RXBUFF

RXRDY : Receiver Ready (cleared by reading US_RHR)
bits : 0 - 0 (1 bit)
access : read-only

TXRDY : Transmitter Ready (cleared by writing US_THR)
bits : 1 - 1 (1 bit)
access : read-only

ENDRX :
bits : 3 - 3 (1 bit)
access : read-only

ENDTX :
bits : 4 - 4 (1 bit)
access : read-only

OVRE : Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 5 - 5 (1 bit)
access : read-only

TXEMPTY : Transmitter Empty (cleared by writing US_THR)
bits : 9 - 9 (1 bit)
access : read-only

UNRE : Underrun Error (cleared by writing a one to bit US_CR.RSTSTA)
bits : 10 - 10 (1 bit)
access : read-only

TXBUFE :
bits : 11 - 11 (1 bit)
access : read-only

RXBUFF :
bits : 12 - 12 (1 bit)
access : read-only


RHR

Receive Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RHR RHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCHR RXSYNH

RXCHR : Received Character
bits : 0 - 8 (9 bit)
access : read-only

RXSYNH : Received Sync
bits : 15 - 15 (1 bit)
access : read-only


THR

Transmit Holding Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

THR THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCHR TXSYNH

TXCHR : Character to be Transmitted
bits : 0 - 8 (9 bit)
access : write-only

TXSYNH : Sync Field to be Transmitted
bits : 15 - 15 (1 bit)
access : write-only


BRGR

Baud Rate Generator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRGR BRGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CD FP

CD : Clock Divider
bits : 0 - 15 (16 bit)
access : read-write

FP : Fractional Part
bits : 16 - 18 (3 bit)
access : read-write


RTOR

Receiver Time-out Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTOR RTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO

TO : Time-out Value
bits : 0 - 15 (16 bit)
access : read-write


TTGR

Transmitter Timeguard Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TTGR TTGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TG

TG : Timeguard Value
bits : 0 - 7 (8 bit)
access : read-write


MR

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART_MODE USCLKS CHRL SYNC PAR NBSTOP CHMODE MODE9 CLKO OVER FILTER

USART_MODE : USART Mode of Operation
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : NORMAL

Normal mode

0x1 : RS485

RS485

0x2 : HW_HANDSHAKING

Hardware Handshaking

0xE : SPI_MASTER

SPI master

0xF : SPI_SLAVE

SPI Slave

End of enumeration elements list.

USCLKS : Clock Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : MCK

Peripheral clock is selected

0x1 : DIV

Peripheral clock divided (DIV=8) is selected

0x3 : SCK

Serial clock (SCK) is selected

End of enumeration elements list.

CHRL : Character Length
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x0 : 5_BIT

Character length is 5 bits

0x1 : 6_BIT

Character length is 6 bits

0x2 : 7_BIT

Character length is 7 bits

0x3 : 8_BIT

Character length is 8 bits

End of enumeration elements list.

SYNC : Synchronous Mode Select
bits : 8 - 8 (1 bit)
access : read-write

PAR : Parity Type
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

0x0 : EVEN

Even parity

0x1 : ODD

Odd parity

0x2 : SPACE

Parity forced to 0 (Space)

0x3 : MARK

Parity forced to 1 (Mark)

0x4 : NO

No parity

0x6 : MULTIDROP

Multidrop mode

End of enumeration elements list.

NBSTOP : Number of Stop Bits
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BIT

1 stop bit

0x1 : 1_5_BIT

1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)

0x2 : 2_BIT

2 stop bits

End of enumeration elements list.

CHMODE : Channel Mode
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0x0 : NORMAL

Normal mode

0x1 : AUTOMATIC

Automatic Echo. Receiver input is connected to the TXD pin.

0x2 : LOCAL_LOOPBACK

Local Loopback. Transmitter output is connected to the Receiver Input.

0x3 : REMOTE_LOOPBACK

Remote Loopback. RXD pin is internally connected to the TXD pin.

End of enumeration elements list.

MODE9 : 9-bit Character Length
bits : 17 - 17 (1 bit)
access : read-write

CLKO : Clock Output Select
bits : 18 - 18 (1 bit)
access : read-write

OVER : Oversampling Mode
bits : 19 - 19 (1 bit)
access : read-write

FILTER : Receive Line Filter
bits : 28 - 28 (1 bit)
access : read-write


MR_SPI_MODE

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0

MR_SPI_MODE MR_SPI_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART_MODE USCLKS CHRL CPHA CPOL CLKO WRDBT

USART_MODE : USART Mode of Operation
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0xE : SPI_MASTER

SPI master

0xF : SPI_SLAVE

SPI Slave

End of enumeration elements list.

USCLKS : Clock Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : MCK

Peripheral clock is selected

0x1 : DIV

Peripheral clock divided (DIV=8) is selected

0x3 : SCK

Serial Clock SLK is selected

End of enumeration elements list.

CHRL : Character Length
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x3 : 8_BIT

Character length is 8 bits

End of enumeration elements list.

CPHA : SPI Clock Phase
bits : 8 - 8 (1 bit)
access : read-write

CPOL : SPI Clock Polarity
bits : 16 - 16 (1 bit)
access : read-write

CLKO : Clock Output Select
bits : 18 - 18 (1 bit)
access : read-write

WRDBT : Wait Read Data Before Transfer
bits : 20 - 20 (1 bit)
access : read-write


NER

Number of Errors Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NER NER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IER

Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY RXBRK ENDRX ENDTX OVRE FRAME PARE TIMEOUT TXEMPTY TXBUFE RXBUFF CTSIC

RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

RXBRK : Receiver Break Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

ENDRX : End of Receive Buffer Interrupt Enable (available in all USART modes of operation)
bits : 3 - 3 (1 bit)
access : write-only

ENDTX : End of Transmit Buffer Interrupt Enable (available in all USART modes of operation)
bits : 4 - 4 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

FRAME : Framing Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

PARE : Parity Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

TIMEOUT : Time-out Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TXBUFE : Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation)
bits : 11 - 11 (1 bit)
access : write-only

RXBUFF : Receive Buffer Full Interrupt Enable (available in all USART modes of operation)
bits : 12 - 12 (1 bit)
access : write-only

CTSIC : Clear to Send Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only


IER_SPI_MODE

Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0

IER_SPI_MODE IER_SPI_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE TXEMPTY UNRE TXBUFE RXBUFF

RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

ENDRX :
bits : 3 - 3 (1 bit)
access : write-only

ENDTX :
bits : 4 - 4 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

UNRE : SPI Underrun Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXBUFE :
bits : 11 - 11 (1 bit)
access : write-only

RXBUFF :
bits : 12 - 12 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY RXBRK ENDRX ENDTX OVRE FRAME PARE TIMEOUT TXEMPTY TXBUFE RXBUFF CTSIC

RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

RXBRK : Receiver Break Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

ENDRX : End of Receive Buffer Transfer Interrupt Disable (available in all USART modes of operation)
bits : 3 - 3 (1 bit)
access : write-only

ENDTX : End of Transmit Buffer Interrupt Disable (available in all USART modes of operation)
bits : 4 - 4 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

FRAME : Framing Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

PARE : Parity Error Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

TIMEOUT : Time-out Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TXBUFE : Transmit Buffer Empty Interrupt Disable (available in all USART modes of operation)
bits : 11 - 11 (1 bit)
access : write-only

RXBUFF : Receive Buffer Full Interrupt Disable (available in all USART modes of operation)
bits : 12 - 12 (1 bit)
access : write-only

CTSIC : Clear to Send Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only


IDR_SPI_MODE

Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0

IDR_SPI_MODE IDR_SPI_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE TXEMPTY UNRE TXBUFE RXBUFF

RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

ENDRX :
bits : 3 - 3 (1 bit)
access : write-only

ENDTX :
bits : 4 - 4 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

UNRE : SPI Underrun Error Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXBUFE :
bits : 11 - 11 (1 bit)
access : write-only

RXBUFF :
bits : 12 - 12 (1 bit)
access : write-only


WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x555341 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

End of enumeration elements list.


WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only



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