\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Memory to Memory Transfer Holding Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THDATA : Transfer Holding Data
bits : 0 - 31 (32 bit)
access : read-write
Memory to Memory Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXEND : End of Transfer Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
RXBUFF : Buffer Full Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
Receive Pointer Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPTR : Receive Pointer Register
bits : 0 - 31 (32 bit)
access : read-write
Receive Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXCTR : Receive Counter Register
bits : 0 - 15 (16 bit)
access : read-write
Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write
Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write
Receive Next Pointer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNPTR : Receive Next Pointer
bits : 0 - 31 (32 bit)
access : read-write
Receive Next Counter Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNCTR : Receive Next Counter
bits : 0 - 15 (16 bit)
access : read-write
Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write
Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write
Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only
RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only
TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only
RXCBEN : Receiver Circular Buffer Enable
bits : 16 - 16 (1 bit)
access : write-only
RXCBDIS : Receiver Circular Buffer Disable
bits : 17 - 17 (1 bit)
access : write-only
TXCBEN : Transmitter Circular Buffer Enable
bits : 18 - 18 (1 bit)
access : write-only
TXCBDIS : Transmitter Circular Buffer Disable
bits : 19 - 19 (1 bit)
access : write-only
ERRCLR : Transfer Bus Error Clear
bits : 24 - 24 (1 bit)
access : write-only
Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only
RXCBEN : Receiver Circular Buffer Enable
bits : 16 - 16 (1 bit)
access : read-only
TXCBEN : Transmitter Circular Buffer Enable
bits : 18 - 18 (1 bit)
access : read-only
ERR : Transfer Bus Error
bits : 24 - 24 (1 bit)
access : read-only
Memory to Memory Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXEND : End of Transfer
bits : 0 - 0 (1 bit)
access : read-only
RXBUFF : Buffer Full
bits : 1 - 1 (1 bit)
access : read-only
Memory to Memory Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSIZE : Transfer Size
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : T_8BIT
The buffer size is defined in byte.
0x1 : T_16BIT
The buffer size is defined in half-word (16-bit).
0x2 : T_32BIT
The buffer size is defined in word (32-bit). Default value.
End of enumeration elements list.
Memory to Memory Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXEND : End of Transfer Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXBUFF : Buffer Full Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
Memory to Memory Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXEND : End of Transfer Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
RXBUFF : Buffer Full Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.