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USART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

CR_SPI_MODE

IMR

IMR_SPI_MODE

IMR_LIN_MODE

RPR

RCR

TPR

TCR

RNPR

RNCR

TNPR

TNCR

PTCR

PTSR

CSR

CSR_SPI_MODE

CSR_LIN_MODE

RHR

THR

BRGR

RTOR

TTGR

MR

MR_SPI_MODE

FIDI

NER

LINMR

LINIR

LINBRR

IER

IER_SPI_MODE

IER_LIN_MODE

CMPR

IDR

IDR_SPI_MODE

IDR_LIN_MODE

WPMR

WPSR


CR

USART Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTRX RSTTX RXEN RXDIS TXEN TXDIS RSTSTA STTBRK STPBRK STTTO SENDA RSTIT RSTNACK RETTO RTSEN RTSDIS LINABT LINWKUP REQCLR

RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
access : write-only

RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
access : write-only

RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
access : write-only

RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
access : write-only

TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
access : write-only

TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
access : write-only

RSTSTA : Reset Status Bits
bits : 8 - 8 (1 bit)
access : write-only

STTBRK : Start Break
bits : 9 - 9 (1 bit)
access : write-only

STPBRK : Stop Break
bits : 10 - 10 (1 bit)
access : write-only

STTTO : Start Time-out
bits : 11 - 11 (1 bit)
access : write-only

SENDA : Send Address
bits : 12 - 12 (1 bit)
access : write-only

RSTIT : Reset Iterations
bits : 13 - 13 (1 bit)
access : write-only

RSTNACK : Reset Non Acknowledge
bits : 14 - 14 (1 bit)
access : write-only

RETTO : Rearm Time-out
bits : 15 - 15 (1 bit)
access : write-only

RTSEN : Request to Send Enable
bits : 18 - 18 (1 bit)
access : write-only

RTSDIS : Request to Send Disable
bits : 19 - 19 (1 bit)
access : write-only

LINABT : Abort LIN Transmission
bits : 20 - 20 (1 bit)
access : write-only

LINWKUP : Send LIN Wakeup Signal
bits : 21 - 21 (1 bit)
access : write-only

REQCLR : Request to Clear the Comparison Trigger
bits : 28 - 28 (1 bit)
access : write-only


CR_SPI_MODE

USART Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0

CR_SPI_MODE CR_SPI_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTRX RSTTX RXEN RXDIS TXEN TXDIS RSTSTA FCS RCS

RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
access : write-only

RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
access : write-only

RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
access : write-only

RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
access : write-only

TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
access : write-only

TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
access : write-only

RSTSTA : Reset Status Bits
bits : 8 - 8 (1 bit)
access : write-only

FCS : Force SPI Chip Select
bits : 18 - 18 (1 bit)
access : write-only

RCS : Release SPI Chip Select
bits : 19 - 19 (1 bit)
access : write-only


IMR

USART Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY RXBRK ENDRX ENDTX OVRE FRAME PARE TIMEOUT TXEMPTY ITER TXBUFE RXBUFF NACK CTSIC CMP

RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

RXBRK : Receiver Break Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

ENDRX : End of Receive Buffer Interrupt Mask (available in all USART modes of operation)
bits : 3 - 3 (1 bit)
access : read-only

ENDTX : End of Transmit Buffer Interrupt Mask (available in all USART modes of operation)
bits : 4 - 4 (1 bit)
access : read-only

OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

FRAME : Framing Error Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only

PARE : Parity Error Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only

TIMEOUT : Time-out Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only

TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only

ITER : Max Number of Repetitions Reached Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only

TXBUFE : Transmit Buffer Empty Interrupt Mask (available in all USART modes of operation)
bits : 11 - 11 (1 bit)
access : read-only

RXBUFF : Receive Buffer Full Interrupt Mask (available in all USART modes of operation)
bits : 12 - 12 (1 bit)
access : read-only

NACK : Non Acknowledge Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only

CTSIC : Clear to Send Input Change Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only

CMP : Comparison Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only


IMR_SPI_MODE

USART Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0

IMR_SPI_MODE IMR_SPI_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE TXEMPTY UNRE TXBUFE RXBUFF CMP

RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

ENDRX :
bits : 3 - 3 (1 bit)
access : read-only

ENDTX :
bits : 4 - 4 (1 bit)
access : read-only

OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only

UNRE : SPI Underrun Error Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only

TXBUFE :
bits : 11 - 11 (1 bit)
access : read-only

RXBUFF :
bits : 12 - 12 (1 bit)
access : read-only

CMP : Comparison Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only


IMR_LIN_MODE

USART Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : LIN_MODE
reset_Mask : 0x0

IMR_LIN_MODE IMR_LIN_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE FRAME PARE TIMEOUT TXEMPTY TXBUFE RXBUFF LINBK LINID LINTC LINBE LINISFE LINIPE LINCE LINSNRE LINSTE LINHTE

RXRDY : RXRDY Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

TXRDY : TXRDY Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

ENDRX :
bits : 3 - 3 (1 bit)
access : read-only

ENDTX :
bits : 4 - 4 (1 bit)
access : read-only

OVRE : Overrun Error Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

FRAME : Framing Error Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only

PARE : Parity Error Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only

TIMEOUT : Time-out Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only

TXEMPTY : TXEMPTY Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only

TXBUFE :
bits : 11 - 11 (1 bit)
access : read-only

RXBUFF :
bits : 12 - 12 (1 bit)
access : read-only

LINBK : LIN Break Sent or LIN Break Received Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only

LINID : LIN Identifier Sent or LIN Identifier Received Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only

LINTC : LIN Transfer Completed Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only

LINBE : LIN Bus Error Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only

LINISFE : LIN Inconsistent Synch Field Error Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only

LINIPE : LIN Identifier Parity Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only

LINCE : LIN Checksum Error Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only

LINSNRE : LIN Slave Not Responding Error Interrupt Mask
bits : 29 - 29 (1 bit)
access : read-only

LINSTE : LIN Synch Tolerance Error Interrupt Mask
bits : 30 - 30 (1 bit)
access : read-only

LINHTE : LIN Header Timeout Error Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-only


RPR

Receive Pointer Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPR RPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPTR

RXPTR : Receive Pointer Register
bits : 0 - 31 (32 bit)
access : read-write


RCR

Receive Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCTR

RXCTR : Receive Counter Register
bits : 0 - 15 (16 bit)
access : read-write


TPR

Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPR TPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPTR

TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write


TCR

Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCTR

TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write


RNPR

Receive Next Pointer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNPR RNPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNPTR

RXNPTR : Receive Next Pointer
bits : 0 - 31 (32 bit)
access : read-write


RNCR

Receive Next Counter Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNCR RNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNCTR

RXNCTR : Receive Next Counter
bits : 0 - 15 (16 bit)
access : read-write


TNPR

Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNPR TNPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXNPTR

TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write


TNCR

Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNCR TNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXNCTR

TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write


PTCR

Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PTCR PTCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN RXTDIS TXTEN TXTDIS RXCBEN RXCBDIS TXCBEN TXCBDIS ERRCLR

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only

RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only

TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only

RXCBEN : Receiver Circular Buffer Enable
bits : 16 - 16 (1 bit)
access : write-only

RXCBDIS : Receiver Circular Buffer Disable
bits : 17 - 17 (1 bit)
access : write-only

TXCBEN : Transmitter Circular Buffer Enable
bits : 18 - 18 (1 bit)
access : write-only

TXCBDIS : Transmitter Circular Buffer Disable
bits : 19 - 19 (1 bit)
access : write-only

ERRCLR : Transfer Bus Error Clear
bits : 24 - 24 (1 bit)
access : write-only


PTSR

Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PTSR PTSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN TXTEN RXCBEN TXCBEN ERR

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only

RXCBEN : Receiver Transfer Enable
bits : 16 - 16 (1 bit)
access : read-only

TXCBEN : Transmitter Transfer Enable
bits : 18 - 18 (1 bit)
access : read-only

ERR : Transfer Bus Error (clear on read)
bits : 24 - 24 (1 bit)
access : read-only


CSR

USART Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY RXBRK ENDRX ENDTX OVRE FRAME PARE TIMEOUT TXEMPTY ITER TXBUFE RXBUFF NACK CTSIC CMP CTS

RXRDY : Receiver Ready (automatically set / cleared)
bits : 0 - 0 (1 bit)
access : read-only

TXRDY : Transmitter Ready (automatically set / cleared)
bits : 1 - 1 (1 bit)
access : read-only

RXBRK : Break Received/End of Break (cleared by US_CR.RSTSTA command)
bits : 2 - 2 (1 bit)
access : read-only

ENDRX : End of RX Buffer (automatically set / cleared)
bits : 3 - 3 (1 bit)
access : read-only

ENDTX : End of TX Buffer (automatically set / cleared)
bits : 4 - 4 (1 bit)
access : read-only

OVRE : Overrun Error (cleared by US_CR.RSTSTA command)
bits : 5 - 5 (1 bit)
access : read-only

FRAME : Framing Error (cleared by US_CR.RSTSTA command)
bits : 6 - 6 (1 bit)
access : read-only

PARE : Parity Error (cleared by US_CR.RSTSTA command)
bits : 7 - 7 (1 bit)
access : read-only

TIMEOUT : Receiver Time-out (cleared by US_CR.STTTO command)
bits : 8 - 8 (1 bit)
access : read-only

TXEMPTY : Transmitter Empty (automatically set / cleared)
bits : 9 - 9 (1 bit)
access : read-only

ITER : Max Number of Repetitions Reached (cleared by US_CR.RSTIT command)
bits : 10 - 10 (1 bit)
access : read-only

TXBUFE : TX Buffer Empty (automatically set / cleared)
bits : 11 - 11 (1 bit)
access : read-only

RXBUFF : RX Buffer Full (automatically set / cleared)
bits : 12 - 12 (1 bit)
access : read-only

NACK : Non Acknowledge Interrupt (cleared by US_CR.RSTNACK command)
bits : 13 - 13 (1 bit)
access : read-only

CTSIC : Clear to Send Input Change Flag (clear on read)
bits : 19 - 19 (1 bit)
access : read-only

CMP : Comparison Status (cleared by US_CR.RSTSTA command)
bits : 22 - 22 (1 bit)
access : read-only

CTS : Image of CTS Input (automatically set / cleared)
bits : 23 - 23 (1 bit)
access : read-only


CSR_SPI_MODE

USART Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0

CSR_SPI_MODE CSR_SPI_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE TXEMPTY UNRE TXBUFE RXBUFF CMP

RXRDY : Receiver Ready (automatically set / cleared)
bits : 0 - 0 (1 bit)
access : read-only

TXRDY : Transmitter Ready (automatically set / cleared)
bits : 1 - 1 (1 bit)
access : read-only

ENDRX :
bits : 3 - 3 (1 bit)
access : read-only

ENDTX :
bits : 4 - 4 (1 bit)
access : read-only

OVRE : Overrun Error (cleared by US_CR.RSTSTA)
bits : 5 - 5 (1 bit)
access : read-only

TXEMPTY : Transmitter Empty (automatically set / cleared)
bits : 9 - 9 (1 bit)
access : read-only

UNRE : Underrun Error (cleared by US_CR.RSTSTA)
bits : 10 - 10 (1 bit)
access : read-only

TXBUFE :
bits : 11 - 11 (1 bit)
access : read-only

RXBUFF :
bits : 12 - 12 (1 bit)
access : read-only

CMP : Comparison Match (cleared by US_CR.RSTSTA)
bits : 22 - 22 (1 bit)
access : read-only


CSR_LIN_MODE

USART Channel Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : LIN_MODE
reset_Mask : 0x0

CSR_LIN_MODE CSR_LIN_MODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE FRAME PARE TIMEOUT TXEMPTY TXBUFE RXBUFF LINBK LINID LINTC LINBLS LINBE LINISFE LINIPE LINCE LINSNRE LINSTE LINHTE

RXRDY : Receiver Ready (automatically set / cleared)
bits : 0 - 0 (1 bit)
access : read-only

TXRDY : Transmitter Ready (automatically set / cleared)
bits : 1 - 1 (1 bit)
access : read-only

ENDRX :
bits : 3 - 3 (1 bit)
access : read-only

ENDTX :
bits : 4 - 4 (1 bit)
access : read-only

OVRE : Overrun Error (cleared by US_CR.RSTSTA command)
bits : 5 - 5 (1 bit)
access : read-only

FRAME : Framing Error (cleared by US_CR.RSTSTA command)
bits : 6 - 6 (1 bit)
access : read-only

PARE : Parity Error (cleared by US_CR.RSTSTA command)
bits : 7 - 7 (1 bit)
access : read-only

TIMEOUT : Receiver Time-out (cleared by US_CR.STTTO command)
bits : 8 - 8 (1 bit)
access : read-only

TXEMPTY : Transmitter Empty (automatically set / cleared)
bits : 9 - 9 (1 bit)
access : read-only

TXBUFE :
bits : 11 - 11 (1 bit)
access : read-only

RXBUFF :
bits : 12 - 12 (1 bit)
access : read-only

LINBK : LIN Break Sent or LIN Break Received (cleared by US_CR.RSTSTA command)
bits : 13 - 13 (1 bit)
access : read-only

LINID : LIN Identifier Sent or LIN Identifier Received (cleared by US_CR.RSTSTA command)
bits : 14 - 14 (1 bit)
access : read-only

LINTC : LIN Transfer Completed (cleared by US_CR.RSTSTA command)
bits : 15 - 15 (1 bit)
access : read-only

LINBLS : LIN Bus Line Status
bits : 23 - 23 (1 bit)
access : read-only

LINBE : LIN Bit Error (cleared by US_CR.RSTSTA command)
bits : 25 - 25 (1 bit)
access : read-only

LINISFE : LIN Inconsistent Synch Field Error (cleared by US_CR.RSTSTA command)
bits : 26 - 26 (1 bit)
access : read-only

LINIPE : LIN Identifier Parity Error (cleared by US_CR.RSTSTA command)
bits : 27 - 27 (1 bit)
access : read-only

LINCE : LIN Checksum Error (cleared by US_CR.RSTSTA command)
bits : 28 - 28 (1 bit)
access : read-only

LINSNRE : LIN Slave Not Responding Error (cleared by US_CR.RSTSTA command)
bits : 29 - 29 (1 bit)
access : read-only

LINSTE : LIN Synch Tolerance Error (cleared by US_CR.RSTSTA command)
bits : 30 - 30 (1 bit)
access : read-only

LINHTE : LIN Header Timeout Error (cleared by US_CR.RSTSTA command)
bits : 31 - 31 (1 bit)
access : read-only


RHR

USART Receive Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RHR RHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCHR RXSYNH

RXCHR : Received Character
bits : 0 - 8 (9 bit)
access : read-only

RXSYNH : Received Sync
bits : 15 - 15 (1 bit)
access : read-only


THR

USART Transmit Holding Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

THR THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCHR TXSYNH

TXCHR : Character to be Transmitted
bits : 0 - 8 (9 bit)
access : write-only

TXSYNH : Sync Field to be Transmitted
bits : 15 - 15 (1 bit)
access : write-only


BRGR

USART Baud Rate Generator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRGR BRGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CD FP

CD : Clock Divider
bits : 0 - 15 (16 bit)
access : read-write

FP : Fractional Part
bits : 16 - 18 (3 bit)
access : read-write


RTOR

USART Receiver Time-out Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTOR RTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO

TO : Time-out Value
bits : 0 - 16 (17 bit)
access : read-write


TTGR

USART Transmitter Timeguard Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TTGR TTGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TG

TG : Timeguard Value
bits : 0 - 7 (8 bit)
access : read-write


MR

USART Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART_MODE USCLKS CHRL SYNC PAR NBSTOP CHMODE MSBF MODE9 CLKO OVER INACK DSNACK INVDATA MAX_ITERATION FILTER

USART_MODE : USART Mode of Operation
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : NORMAL

Normal mode

0x1 : RS485

RS485 mode

0x2 : HW_HANDSHAKING

Hardware Handshaking

0x4 : IS07816_T_0

IS07816 Protocol: T = 0

0x6 : IS07816_T_1

IS07816 Protocol: T = 1

0xA : LIN_MASTER

LIN master mode

0xB : LIN_SLAVE

LIN Slave mode

0xE : SPI_MASTER

SPI master mode

0xF : SPI_SLAVE

SPI Slave mode

End of enumeration elements list.

USCLKS : Clock Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : MCK

Peripheral clock is selected

0x1 : DIV

Peripheral clock Divided (DIV=8) is selected

0x2 : PMC_PCK

PMC programmable clock (PCK) is selected.If the SCK pin is driven (CLKO=1), the CD field must be greater than 1.

0x3 : SCK

External pin (SCK) is selected

End of enumeration elements list.

CHRL : Character Length
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x0 : 5_BIT

Character length is 5 bits

0x1 : 6_BIT

Character length is 6 bits

0x2 : 7_BIT

Character length is 7 bits

0x3 : 8_BIT

Character length is 8 bits

End of enumeration elements list.

SYNC : Synchronous Mode Select
bits : 8 - 8 (1 bit)
access : read-write

PAR : Parity Type
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

0x0 : EVEN

Even parity

0x1 : ODD

Odd parity

0x2 : SPACE

Parity forced to 0 (Space)

0x3 : MARK

Parity forced to 1 (Mark)

0x4 : NO

No parity

0x6 : MULTIDROP

Multidrop mode

End of enumeration elements list.

NBSTOP : Number of Stop Bits
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BIT

1 stop bit

0x1 : 1_5_BIT

1.5 stop bits (SYNC = 0) or reserved (SYNC = 1)

0x2 : 2_BIT

2 stop bits

End of enumeration elements list.

CHMODE : Channel Mode
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0x0 : NORMAL

Normal mode

0x1 : AUTOMATIC

Automatic Echo. Receiver input is connected to the TXD pin.

0x2 : LOCAL_LOOPBACK

Local Loopback. Transmitter output is connected to the Receiver Input.

0x3 : REMOTE_LOOPBACK

Remote Loopback. RXD pin is internally connected to the TXD pin.

End of enumeration elements list.

MSBF : Bit Order
bits : 16 - 16 (1 bit)
access : read-write

MODE9 : 9-bit Character Length
bits : 17 - 17 (1 bit)
access : read-write

CLKO : Clock Output Select
bits : 18 - 18 (1 bit)
access : read-write

OVER : Oversampling Mode
bits : 19 - 19 (1 bit)
access : read-write

INACK : Inhibit Non Acknowledge
bits : 20 - 20 (1 bit)
access : read-write

DSNACK : Disable Successive NACK
bits : 21 - 21 (1 bit)
access : read-write

INVDATA : Inverted Data
bits : 23 - 23 (1 bit)
access : read-write

MAX_ITERATION : Maximum Number of Automatic Iteration
bits : 24 - 26 (3 bit)
access : read-write

FILTER : Receive Line Filter
bits : 28 - 28 (1 bit)
access : read-write


MR_SPI_MODE

USART Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0

MR_SPI_MODE MR_SPI_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART_MODE USCLKS CHRL CPHA CPOL WRDBT

USART_MODE : USART Mode of Operation
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0xE : SPI_MASTER

SPI master mode

0xF : SPI_SLAVE

SPI Slave mode

End of enumeration elements list.

USCLKS : Clock Selection
bits : 4 - 5 (2 bit)
access : read-write

CHRL : Character Length
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0x3 : 8_BIT

Character length is 8 bits

End of enumeration elements list.

CPHA : SPI Clock Phase
bits : 8 - 8 (1 bit)
access : read-write

CPOL : SPI Clock Polarity
bits : 16 - 16 (1 bit)
access : read-write

WRDBT : Wait Read Data Before Transfer
bits : 20 - 20 (1 bit)
access : read-write


FIDI

USART FI DI Ratio Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIDI FIDI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FI_DI_RATIO

FI_DI_RATIO : FI Over DI Ratio Value
bits : 0 - 15 (16 bit)
access : read-write


NER

USART Number of Errors Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NER NER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NB_ERRORS

NB_ERRORS : Number of Errors
bits : 0 - 7 (8 bit)
access : read-only


LINMR

USART LIN Mode Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LINMR LINMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NACT PARDIS CHKDIS CHKTYP DLM FSDIS WKUPTYP DLC PDCM SYNCDIS

NACT : LIN Node Action
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x0 : PUBLISH

The USART transmits the response.

0x1 : SUBSCRIBE

The USART receives the response.

0x2 : IGNORE

The USART does not transmit and does not receive the response.

End of enumeration elements list.

PARDIS : Parity Disable
bits : 2 - 2 (1 bit)
access : read-write

CHKDIS : Checksum Disable
bits : 3 - 3 (1 bit)
access : read-write

CHKTYP : Checksum Type
bits : 4 - 4 (1 bit)
access : read-write

DLM : Data Length Mode
bits : 5 - 5 (1 bit)
access : read-write

FSDIS : Frame Slot Mode Disable
bits : 6 - 6 (1 bit)
access : read-write

WKUPTYP : Wakeup Signal Type
bits : 7 - 7 (1 bit)
access : read-write

DLC : Data Length Control
bits : 8 - 15 (8 bit)
access : read-write

PDCM : PDC Mode
bits : 16 - 16 (1 bit)
access : read-write

SYNCDIS : Synchronization Disable
bits : 17 - 17 (1 bit)
access : read-write


LINIR

USART LIN Identifier Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LINIR LINIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDCHR

IDCHR : Identifier Character
bits : 0 - 7 (8 bit)
access : read-write


LINBRR

USART LIN Baud Rate Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LINBRR LINBRR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINCD LINFP

LINCD : Clock Divider after Synchronization
bits : 0 - 15 (16 bit)
access : read-only

LINFP : Fractional Part after Synchronization
bits : 16 - 18 (3 bit)
access : read-only


IER

USART Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY RXBRK ENDRX ENDTX OVRE FRAME PARE TIMEOUT TXEMPTY ITER TXBUFE RXBUFF NACK CTSIC CMP

RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

RXBRK : Receiver Break Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

ENDRX : End of Receive Buffer Interrupt Enable (available in all USART modes of operation)
bits : 3 - 3 (1 bit)
access : write-only

ENDTX : End of Transmit Buffer Interrupt Enable (available in all USART modes of operation)
bits : 4 - 4 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

FRAME : Framing Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

PARE : Parity Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

TIMEOUT : Time-out Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

ITER : Max number of Repetitions Reached Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXBUFE : Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation)
bits : 11 - 11 (1 bit)
access : write-only

RXBUFF : Receive Buffer Full Interrupt Enable (available in all USART modes of operation)
bits : 12 - 12 (1 bit)
access : write-only

NACK : Non Acknowledge Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

CTSIC : Clear to Send Input Change Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only

CMP : Comparison Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only


IER_SPI_MODE

USART Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0

IER_SPI_MODE IER_SPI_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE TXEMPTY UNRE TXBUFE RXBUFF CMP

RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

ENDRX :
bits : 3 - 3 (1 bit)
access : write-only

ENDTX :
bits : 4 - 4 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

UNRE : SPI Underrun Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

TXBUFE :
bits : 11 - 11 (1 bit)
access : write-only

RXBUFF :
bits : 12 - 12 (1 bit)
access : write-only

CMP : Comparison Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only


IER_LIN_MODE

USART Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : LIN_MODE
reset_Mask : 0x0

IER_LIN_MODE IER_LIN_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE FRAME PARE TIMEOUT TXEMPTY TXBUFE RXBUFF LINBK LINID LINTC LINBE LINISFE LINIPE LINCE LINSNRE LINSTE LINHTE

RXRDY : RXRDY Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXRDY : TXRDY Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

ENDRX :
bits : 3 - 3 (1 bit)
access : write-only

ENDTX :
bits : 4 - 4 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

FRAME : Framing Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

PARE : Parity Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

TIMEOUT : Time-out Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

TXEMPTY : TXEMPTY Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

TXBUFE :
bits : 11 - 11 (1 bit)
access : write-only

RXBUFF :
bits : 12 - 12 (1 bit)
access : write-only

LINBK : LIN Break Sent or LIN Break Received Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

LINID : LIN Identifier Sent or LIN Identifier Received Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

LINTC : LIN Transfer Completed Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only

LINBE : LIN Bus Error Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only

LINISFE : LIN Inconsistent Synch Field Error Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only

LINIPE : LIN Identifier Parity Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only

LINCE : LIN Checksum Error Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only

LINSNRE : LIN Slave Not Responding Error Interrupt Enable
bits : 29 - 29 (1 bit)
access : write-only

LINSTE : LIN Synch Tolerance Error Interrupt Enable
bits : 30 - 30 (1 bit)
access : write-only

LINHTE : LIN Header Timeout Error Interrupt Enable
bits : 31 - 31 (1 bit)
access : write-only


CMPR

USART Comparison Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPR CMPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL1 CMPMODE CMPPAR VAL2

VAL1 : First Comparison Value for Received Character
bits : 0 - 8 (9 bit)
access : read-write

CMPMODE : Comparison Mode
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : FLAG_ONLY

Any character is received and comparison function drives CMP flag.

1 : START_CONDITION

Comparison condition must be met to start reception of all incoming charactersuntil REQCLR is set.

End of enumeration elements list.

CMPPAR : Compare Parity
bits : 14 - 14 (1 bit)
access : read-write

VAL2 : Second Comparison Value for Received Character
bits : 16 - 24 (9 bit)
access : read-write


IDR

USART Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY RXBRK ENDRX ENDTX OVRE FRAME PARE TIMEOUT TXEMPTY ITER TXBUFE RXBUFF NACK CTSIC CMP

RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

RXBRK : Receiver Break Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

ENDRX : End of Receive Buffer Interrupt Enable (available in all USART modes of operation)
bits : 3 - 3 (1 bit)
access : write-only

ENDTX : End of Transmit Buffer Interrupt Disable (available in all USART modes of operation)
bits : 4 - 4 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

FRAME : Framing Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

PARE : Parity Error Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

TIMEOUT : Time-out Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

ITER : Max Number of Repetitions Reached Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXBUFE : Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation)
bits : 11 - 11 (1 bit)
access : write-only

RXBUFF : Receive Buffer Full Interrupt Enable (available in all USART modes of operation)
bits : 12 - 12 (1 bit)
access : write-only

NACK : Non Acknowledge Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

CTSIC : Clear to Send Input Change Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only

CMP : Comparison Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only


IDR_SPI_MODE

USART Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : SPI_MODE
reset_Mask : 0x0

IDR_SPI_MODE IDR_SPI_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE TXEMPTY UNRE TXBUFE RXBUFF CMP

RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

ENDRX :
bits : 3 - 3 (1 bit)
access : write-only

ENDTX :
bits : 4 - 4 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

UNRE : SPI Underrun Error Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

TXBUFE :
bits : 11 - 11 (1 bit)
access : write-only

RXBUFF :
bits : 12 - 12 (1 bit)
access : write-only

CMP : Comparison Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only


IDR_LIN_MODE

USART Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : LIN_MODE
reset_Mask : 0x0

IDR_LIN_MODE IDR_LIN_MODE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXRDY TXRDY ENDRX ENDTX OVRE FRAME PARE TIMEOUT TXEMPTY TXBUFE RXBUFF LINBK LINID LINTC LINBE LINISFE LINIPE LINCE LINSNRE LINSTE LINHTE

RXRDY : RXRDY Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXRDY : TXRDY Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

ENDRX :
bits : 3 - 3 (1 bit)
access : write-only

ENDTX :
bits : 4 - 4 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

FRAME : Framing Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

PARE : Parity Error Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

TIMEOUT : Time-out Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

TXEMPTY : TXEMPTY Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

TXBUFE :
bits : 11 - 11 (1 bit)
access : write-only

RXBUFF :
bits : 12 - 12 (1 bit)
access : write-only

LINBK : LIN Break Sent or LIN Break Received Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

LINID : LIN Identifier Sent or LIN Identifier Received Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

LINTC : LIN Transfer Completed Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only

LINBE : LIN Bus Error Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only

LINISFE : LIN Inconsistent Synch Field Error Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only

LINIPE : LIN Identifier Parity Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only

LINCE : LIN Checksum Error Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only

LINSNRE : LIN Slave Not Responding Error Interrupt Disable
bits : 29 - 29 (1 bit)
access : write-only

LINSTE : LIN Synch Tolerance Error Interrupt Disable
bits : 30 - 30 (1 bit)
access : write-only

LINHTE : LIN Header Timeout Error Interrupt Disable
bits : 31 - 31 (1 bit)
access : write-only


WPMR

USART Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x555341 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

End of enumeration elements list.


WPSR

USART Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only



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