\n

SYSC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

SR

MR


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROCRST PERRST EXTRST KEY

PROCRST : Processor Reset
bits : 0 - 0 (1 bit)
access : write-only

PERRST : Peripheral Reset
bits : 2 - 2 (1 bit)
access : write-only

EXTRST : External Reset
bits : 3 - 3 (1 bit)
access : write-only

KEY : System Reset Key
bits : 24 - 31 (8 bit)
access : write-only

Enumeration:

0xA5 : PASSWD

Writing any other value in this field aborts the write operation.

End of enumeration elements list.


SR

Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 URSTS RSTTYP NRSTL SRCMP

URSTS : User Reset Status
bits : 0 - 0 (1 bit)
access : read-only

RSTTYP : Reset Type
bits : 8 - 10 (3 bit)
access : read-only

Enumeration:

0x0 : GENERAL_RST

First power-up reset

0x1 : BACKUP_RST

Return from Backup Mode

0x2 : WDT_RST

Watchdog fault occurred

0x3 : SOFT_RST

Processor reset required by the software

0x4 : USER_RST

NRST pin detected low

0x7 : SLCK_XTAL_RST

Slow Crystal Failure Detection fault occured

End of enumeration elements list.

NRSTL : NRST Pin Level
bits : 16 - 16 (1 bit)
access : read-only

SRCMP : Software Reset Command in Progress
bits : 17 - 17 (1 bit)
access : read-only


MR

Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 URSTEN SCKSW URSTIEN ERSTL KEY

URSTEN : User Reset Enable
bits : 0 - 0 (1 bit)
access : read-write

SCKSW : Slow Clock Switching
bits : 1 - 1 (1 bit)
access : read-write

URSTIEN : User Reset Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

ERSTL : External Reset Length
bits : 8 - 11 (4 bit)
access : read-write

KEY : Write Access Password
bits : 24 - 31 (8 bit)
access : read-write

Enumeration:

0xA5 : PASSWD

Writing any other value in this field aborts the write operation.Always reads as 0.

End of enumeration elements list.



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