\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : read-write
ENPDM : Enable PDM
bits : 4 - 4 (1 bit)
access : read-write
Receive Pointer Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPTR : Receive Pointer Register
bits : 0 - 31 (32 bit)
access : read-write
Receive Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXCTR : Receive Counter Register
bits : 0 - 15 (16 bit)
access : read-write
Receive Next Pointer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNPTR : Receive Next Pointer
bits : 0 - 31 (32 bit)
access : read-write
Receive Next Counter Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNCTR : Receive Next Counter
bits : 0 - 15 (16 bit)
access : read-write
Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only
RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only
TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only
RXCBEN : Receiver Circular Buffer Enable
bits : 16 - 16 (1 bit)
access : write-only
RXCBDIS : Receiver Circular Buffer Disable
bits : 17 - 17 (1 bit)
access : write-only
TXCBEN : Transmitter Circular Buffer Enable
bits : 18 - 18 (1 bit)
access : write-only
TXCBDIS : Transmitter Circular Buffer Disable
bits : 19 - 19 (1 bit)
access : write-only
ERRCLR : Transfer Bus Error Clear
bits : 24 - 24 (1 bit)
access : write-only
Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only
RXCBEN : Receiver Transfer Enable
bits : 16 - 16 (1 bit)
access : read-only
TXCBEN : Transmitter Transfer Enable
bits : 18 - 18 (1 bit)
access : read-only
ERR : Transfer Bus Error (clear on read)
bits : 24 - 24 (1 bit)
access : read-only
Converted Data Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Data Converted
bits : 0 - 31 (32 bit)
access : read-only
Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DRDY : Data Ready Interrupt Enable
bits : 24 - 24 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
ENDRX : End of Receive Buffer Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only
RXBUFF : Receive Buffer Full Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DRDY : Data Ready Interrupt Disable
bits : 24 - 24 (1 bit)
access : write-only
OVRE : General Overrun Error Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
ENDRX : End of Receive Buffer Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only
RXBUFF : Receive Buffer Full Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only
Interrupt Mask Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DRDY : Data Ready Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-only
OVRE : General Overrun Error Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
ENDRX : End of Receive Buffer Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only
RXBUFF : Receive Buffer Full Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only
Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIFOCNT : FIFO Count
bits : 16 - 23 (8 bit)
access : read-only
DRDY : Data Ready
bits : 24 - 24 (1 bit)
access : read-only
OVRE : Overrun Error
bits : 25 - 25 (1 bit)
access : read-only
ENDRX : End of RX Buffer
bits : 27 - 27 (1 bit)
access : read-only
RXBUFF : RX Buffer Full
bits : 28 - 28 (1 bit)
access : read-only
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESCAL : Prescaler Rate Selection
bits : 8 - 14 (7 bit)
access : read-write
DSP Configuration Register 0
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPFBYP : High-Pass Filter Bypass
bits : 1 - 1 (1 bit)
access : read-write
SINBYP : SINCC Filter Bypass
bits : 2 - 2 (1 bit)
access : read-write
SIZE : Data Size
bits : 3 - 3 (1 bit)
access : read-write
OSR : Oversampling Ratio
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : 128
Oversampling ratio is 128
1 : 64
Oversampling ratio is 64
End of enumeration elements list.
SCALE : Data Scale
bits : 8 - 11 (4 bit)
access : read-write
SHIFT : Data Shift
bits : 12 - 15 (4 bit)
access : read-write
DSP Configuration Register 1
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DGAIN : Gain Correction
bits : 0 - 14 (15 bit)
access : read-write
OFFSET : Offset Correction
bits : 16 - 31 (16 bit)
access : read-write
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protect Key
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x414443 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
End of enumeration elements list.
Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only
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