\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection :
Cache Controller Type Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AP : Access Port Access Allowed
bits : 0 - 0 (1 bit)
access : read-only
GCLK : Dynamic Clock Gating Supported
bits : 1 - 1 (1 bit)
access : read-only
RANDP : Random Selection Policy Supported
bits : 2 - 2 (1 bit)
access : read-only
LRUP : Least Recently Used Policy Supported
bits : 3 - 3 (1 bit)
access : read-only
RRP : Random Selection Policy Supported
bits : 4 - 4 (1 bit)
access : read-only
WAYNUM : Number of Ways
bits : 5 - 6 (2 bit)
access : read-only
Enumeration:
0x0 : DMAPPED
Direct Mapped Cache
0x1 : ARCH2WAY
2-way set associative
0x2 : ARCH4WAY
4-way set associative
0x3 : ARCH8WAY
8-way set associative
End of enumeration elements list.
LCKDOWN : Lockdown Supported
bits : 7 - 7 (1 bit)
access : read-only
CSIZE : Data Cache Size
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
0x0 : CSIZE_1KB
Data cache size is 1 Kbyte
0x1 : CSIZE_2KB
Data cache size is 2 Kbytes
0x2 : CSIZE_4KB
Data cache size is 4 Kbytes
0x3 : CSIZE_8KB
Data cache size is 8 Kbytes
End of enumeration elements list.
CLSIZE : Cache LIne Size
bits : 11 - 13 (3 bit)
access : read-only
Enumeration:
0x0 : CLSIZE_1KB
Cache line size is 4 bytes
0x1 : CLSIZE_2KB
Cache line size is 8 bytes
0x2 : CLSIZE_4KB
Cache line size is 16 bytes
0x3 : CLSIZE_8KB
Cache line size is 32 bytes
End of enumeration elements list.
Cache Controller Maintenance Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INVALL : Cache Controller Invalidate All
bits : 0 - 0 (1 bit)
access : write-only
Cache Controller Maintenance Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INDEX : Invalidate Index
bits : 4 - 8 (5 bit)
access : write-only
WAY : Invalidate Way
bits : 30 - 31 (2 bit)
access : write-only
Enumeration:
0x0 : WAY0
Way 0 is selection for index invalidation
0x1 : WAY1
Way 1 is selection for index invalidation
0x2 : WAY2
Way 2 is selection for index invalidation
0x3 : WAY3
Way 3 is selection for index invalidation
End of enumeration elements list.
Cache Controller Monitor Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Cache Controller Monitor Counter Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : CYCLE_COUNT
Cycle counter
0x1 : IHIT_COUNT
Instruction hit counter
0x2 : DHIT_COUNT
Data hit counter
End of enumeration elements list.
Cache Controller Monitor Enable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MENABLE : Cache Controller Monitor Enable
bits : 0 - 0 (1 bit)
access : read-write
Cache Controller Monitor Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Monitor
bits : 0 - 0 (1 bit)
access : write-only
Cache Controller Monitor Status Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EVENT_CNT : Monitor Event Counter
bits : 0 - 31 (32 bit)
access : read-only
Cache Controller Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCLKDIS : Disable Clock Gating
bits : 0 - 0 (1 bit)
access : read-write
ICDIS :
bits : 1 - 1 (1 bit)
access : read-write
DCDIS :
bits : 2 - 2 (1 bit)
access : read-write
PRGCSIZE :
bits : 4 - 6 (3 bit)
access : read-write
Cache Controller Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CEN : Cache Controller Enable
bits : 0 - 0 (1 bit)
access : write-only
Cache Controller Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSTS : Cache Controller Status
bits : 0 - 0 (1 bit)
access : read-only
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