\n
address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IORET : I/O Retention
bits : 2 - 2 (1 bit)
Sleep Configuration
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPMODE : Sleep Mode
bits : 0 - 2 (3 bit)
Enumeration: SLEEPMODESelect
0x0 : IDLE0
CPU clock is OFF
0x1 : IDLE1
AHB clock is OFF
0x2 : IDLE2
APB clock are OFF
0x4 : STANDBY
All Clocks are OFF
0x5 : BACKUP
Only Backup domain is powered ON
0x6 : OFF
All power domains are powered OFF
End of enumeration elements list.
Performance Level Configuration
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSEL : Performance Level Select
bits : 0 - 1 (2 bit)
Enumeration: PLSELSelect
0x0 : PL0
Performance Level 0
0x1 : PL1
Performance Level 1
0x2 : PL2
Performance Level 2
End of enumeration elements list.
PLDIS : Performance Level Disable
bits : 7 - 7 (1 bit)
Interrupt Enable Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLRDY : Performance Level Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
Interrupt Enable Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLRDY : Performance Level Ready interrupt Enable
bits : 0 - 0 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLRDY : Performance Level Ready
bits : 0 - 0 (1 bit)
Standby Configuration
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDCFG : Power Domain Configuration
bits : 0 - 1 (2 bit)
Enumeration: PDCFGSelect
0x0 : DEFAULT
All power domains switching is handled by hardware.
0x1 : PD0
PD0 is forced ACTIVE. PD1 and PD2 power domains switching is handled by hardware.
0x2 : PD01
PD0 and PD1 are forced ACTIVE. PD2 power domain switching is handled by hardware.
0x3 : PD012
All power domains are forced ACTIVE.
End of enumeration elements list.
DPGPD0 : Dynamic Power Gating for PD0
bits : 4 - 4 (1 bit)
DPGPD1 : Dynamic Power Gating for PD1
bits : 5 - 5 (1 bit)
VREGSMOD : Voltage Regulator Standby mode
bits : 6 - 7 (2 bit)
Enumeration: VREGSMODSelect
0x0 : AUTO
Automatic mode
0x1 : PERFORMANCE
Performance oriented
0x2 : LP
Low Power oriented
End of enumeration elements list.
LINKPD : Linked Power Domain
bits : 8 - 9 (2 bit)
Enumeration: LINKPDSelect
0x0 : DEFAULT
Power domains are not linked
0x1 : PD01
PD0 and PD1 power domains are linked
0x2 : PD12
PD1 and PD2 power domains are linked
0x3 : PD012
All power domains are linked
End of enumeration elements list.
BBIASHS : Back Bias for HMCRAMCHS
bits : 10 - 11 (2 bit)
BBIASLP : Back Bias for HMCRAMCLP
bits : 12 - 13 (2 bit)
BBIASPP : Back Bias for PicoPram
bits : 14 - 15 (2 bit)
Power Switch Acknowledge Delay
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLYVAL : Delay Value
bits : 0 - 6 (7 bit)
IGNACK : Ignore Acknowledge
bits : 7 - 7 (1 bit)
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