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TC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TC_COUNT8 - CTRLA

TC_COUNT16 - CTRLA

TC_COUNT32 - CTRLA

CTRLA

TC_COUNT8 - SYNCBUSY

TC_COUNT16 - SYNCBUSY

TC_COUNT32 - SYNCBUSY

SYNCBUSY

TC_COUNT8 - COUNT

TC_COUNT16 - COUNT

TC_COUNT32 - COUNT

COUNT

TC_COUNT8 - PER

PER

CC0

CC1

TC_COUNT8 - PERBUF

PERBUF

CCBUF0

CCBUF1

TC_COUNT8 - CC0

TC_COUNT16 - CC0

TC_COUNT32 - CC0

TC_COUNT8 - CTRLBCLR

TC_COUNT16 - CTRLBCLR

TC_COUNT32 - CTRLBCLR

CTRLBCLR

TC_COUNT8 - CTRLBSET

TC_COUNT16 - CTRLBSET

TC_COUNT32 - CTRLBSET

CTRLBSET

TC_COUNT8 - CC1

TC_COUNT16 - CC1

TC_COUNT32 - CC1

TC_COUNT8 - EVCTRL

TC_COUNT16 - EVCTRL

TC_COUNT32 - EVCTRL

EVCTRL

TC_COUNT8 - CCBUF0

TC_COUNT16 - CCBUF0

TC_COUNT32 - CCBUF0

TC_COUNT8 - INTENCLR

TC_COUNT16 - INTENCLR

TC_COUNT32 - INTENCLR

INTENCLR

TC_COUNT8 - INTENSET

TC_COUNT16 - INTENSET

TC_COUNT32 - INTENSET

INTENSET

TC_COUNT8 - CCBUF1

TC_COUNT16 - CCBUF1

TC_COUNT32 - CCBUF1

TC_COUNT8 - INTFLAG

TC_COUNT16 - INTFLAG

TC_COUNT32 - INTFLAG

INTFLAG

TC_COUNT8 - STATUS

TC_COUNT16 - STATUS

TC_COUNT32 - STATUS

STATUS

TC_COUNT8 - WAVE

TC_COUNT16 - WAVE

TC_COUNT32 - WAVE

WAVE

TC_COUNT8 - DRVCTRL

TC_COUNT16 - DRVCTRL

TC_COUNT32 - DRVCTRL

DRVCTRL

TC_COUNT8 - DBGCTRL

TC_COUNT16 - DBGCTRL

TC_COUNT32 - DBGCTRL

DBGCTRL


TC_COUNT8 - CTRLA

8-bit Counter Mode - - Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - CTRLA TC_COUNT8 - CTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE MODE PRESCSYNC RUNSTDBY ONDEMAND PRESCALER ALOCK CAPTEN0 CAPTEN1 COPEN0 COPEN1

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only

ENABLE : Enable
bits : 1 - 1 (1 bit)

MODE : Timer Counter Mode
bits : 2 - 3 (2 bit)

Enumeration: MODESelect

0x0 : COUNT16

Counter in 16-bit mode

0x1 : COUNT8

Counter in 8-bit mode

0x2 : COUNT32

Counter in 32-bit mode

End of enumeration elements list.

PRESCSYNC : Prescaler and Counter Synchronization
bits : 4 - 5 (2 bit)

Enumeration: PRESCSYNCSelect

0x0 : GCLK

Reload or reset the counter on next generic clock

0x1 : PRESC

Reload or reset the counter on next prescaler clock

0x2 : RESYNC

Reload or reset the counter on next generic clock and reset the prescaler counter

End of enumeration elements list.

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)

ONDEMAND : Clock On Demand
bits : 7 - 7 (1 bit)

PRESCALER : Prescaler
bits : 8 - 10 (3 bit)

Enumeration: PRESCALERSelect

0x0 : DIV1

Prescaler: GCLK_TC

0x1 : DIV2

Prescaler: GCLK_TC/2

0x2 : DIV4

Prescaler: GCLK_TC/4

0x3 : DIV8

Prescaler: GCLK_TC/8

0x4 : DIV16

Prescaler: GCLK_TC/16

0x5 : DIV64

Prescaler: GCLK_TC/64

0x6 : DIV256

Prescaler: GCLK_TC/256

0x7 : DIV1024

Prescaler: GCLK_TC/1024

End of enumeration elements list.

ALOCK : Auto Lock
bits : 11 - 11 (1 bit)

CAPTEN0 : Capture Channel 0 Enable
bits : 16 - 16 (1 bit)

CAPTEN1 : Capture Channel 1 Enable
bits : 17 - 17 (1 bit)

COPEN0 : Capture On Pin 0 Enable
bits : 20 - 20 (1 bit)

COPEN1 : Capture On Pin 1 Enable
bits : 21 - 21 (1 bit)


TC_COUNT16 - CTRLA

16-bit Counter Mode - - Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - CTRLA TC_COUNT16 - CTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE MODE PRESCSYNC RUNSTDBY ONDEMAND PRESCALER ALOCK CAPTEN0 CAPTEN1 COPEN0 COPEN1

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only

ENABLE : Enable
bits : 1 - 1 (1 bit)

MODE : Timer Counter Mode
bits : 2 - 3 (2 bit)

Enumeration: MODESelect

0x0 : COUNT16

Counter in 16-bit mode

0x1 : COUNT8

Counter in 8-bit mode

0x2 : COUNT32

Counter in 32-bit mode

End of enumeration elements list.

PRESCSYNC : Prescaler and Counter Synchronization
bits : 4 - 5 (2 bit)

Enumeration: PRESCSYNCSelect

0x0 : GCLK

Reload or reset the counter on next generic clock

0x1 : PRESC

Reload or reset the counter on next prescaler clock

0x2 : RESYNC

Reload or reset the counter on next generic clock and reset the prescaler counter

End of enumeration elements list.

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)

ONDEMAND : Clock On Demand
bits : 7 - 7 (1 bit)

PRESCALER : Prescaler
bits : 8 - 10 (3 bit)

Enumeration: PRESCALERSelect

0x0 : DIV1

Prescaler: GCLK_TC

0x1 : DIV2

Prescaler: GCLK_TC/2

0x2 : DIV4

Prescaler: GCLK_TC/4

0x3 : DIV8

Prescaler: GCLK_TC/8

0x4 : DIV16

Prescaler: GCLK_TC/16

0x5 : DIV64

Prescaler: GCLK_TC/64

0x6 : DIV256

Prescaler: GCLK_TC/256

0x7 : DIV1024

Prescaler: GCLK_TC/1024

End of enumeration elements list.

ALOCK : Auto Lock
bits : 11 - 11 (1 bit)

CAPTEN0 : Capture Channel 0 Enable
bits : 16 - 16 (1 bit)

CAPTEN1 : Capture Channel 1 Enable
bits : 17 - 17 (1 bit)

COPEN0 : Capture On Pin 0 Enable
bits : 20 - 20 (1 bit)

COPEN1 : Capture On Pin 1 Enable
bits : 21 - 21 (1 bit)


TC_COUNT32 - CTRLA

32-bit Counter Mode - - Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - CTRLA TC_COUNT32 - CTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE MODE PRESCSYNC RUNSTDBY ONDEMAND PRESCALER ALOCK CAPTEN0 CAPTEN1 COPEN0 COPEN1

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only

ENABLE : Enable
bits : 1 - 1 (1 bit)

MODE : Timer Counter Mode
bits : 2 - 3 (2 bit)

Enumeration: MODESelect

0x0 : COUNT16

Counter in 16-bit mode

0x1 : COUNT8

Counter in 8-bit mode

0x2 : COUNT32

Counter in 32-bit mode

End of enumeration elements list.

PRESCSYNC : Prescaler and Counter Synchronization
bits : 4 - 5 (2 bit)

Enumeration: PRESCSYNCSelect

0x0 : GCLK

Reload or reset the counter on next generic clock

0x1 : PRESC

Reload or reset the counter on next prescaler clock

0x2 : RESYNC

Reload or reset the counter on next generic clock and reset the prescaler counter

End of enumeration elements list.

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)

ONDEMAND : Clock On Demand
bits : 7 - 7 (1 bit)

PRESCALER : Prescaler
bits : 8 - 10 (3 bit)

Enumeration: PRESCALERSelect

0x0 : DIV1

Prescaler: GCLK_TC

0x1 : DIV2

Prescaler: GCLK_TC/2

0x2 : DIV4

Prescaler: GCLK_TC/4

0x3 : DIV8

Prescaler: GCLK_TC/8

0x4 : DIV16

Prescaler: GCLK_TC/16

0x5 : DIV64

Prescaler: GCLK_TC/64

0x6 : DIV256

Prescaler: GCLK_TC/256

0x7 : DIV1024

Prescaler: GCLK_TC/1024

End of enumeration elements list.

ALOCK : Auto Lock
bits : 11 - 11 (1 bit)

CAPTEN0 : Capture Channel 0 Enable
bits : 16 - 16 (1 bit)

CAPTEN1 : Capture Channel 1 Enable
bits : 17 - 17 (1 bit)

COPEN0 : Capture On Pin 0 Enable
bits : 20 - 20 (1 bit)

COPEN1 : Capture On Pin 1 Enable
bits : 21 - 21 (1 bit)


CTRLA

Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE MODE PRESCSYNC RUNSTDBY ONDEMAND PRESCALER ALOCK CAPTEN0 CAPTEN1 COPEN0 COPEN1

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only

ENABLE : Enable
bits : 1 - 1 (1 bit)

MODE : Timer Counter Mode
bits : 2 - 3 (2 bit)

Enumeration: MODESelect

0x0 : COUNT16

Counter in 16-bit mode

0x1 : COUNT8

Counter in 8-bit mode

0x2 : COUNT32

Counter in 32-bit mode

End of enumeration elements list.

PRESCSYNC : Prescaler and Counter Synchronization
bits : 4 - 5 (2 bit)

Enumeration: PRESCSYNCSelect

0x0 : GCLK

Reload or reset the counter on next generic clock

0x1 : PRESC

Reload or reset the counter on next prescaler clock

0x2 : RESYNC

Reload or reset the counter on next generic clock and reset the prescaler counter

End of enumeration elements list.

RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)

ONDEMAND : Clock On Demand
bits : 7 - 7 (1 bit)

PRESCALER : Prescaler
bits : 8 - 10 (3 bit)

Enumeration: PRESCALERSelect

0x0 : DIV1

Prescaler: GCLK_TC

0x1 : DIV2

Prescaler: GCLK_TC/2

0x2 : DIV4

Prescaler: GCLK_TC/4

0x3 : DIV8

Prescaler: GCLK_TC/8

0x4 : DIV16

Prescaler: GCLK_TC/16

0x5 : DIV64

Prescaler: GCLK_TC/64

0x6 : DIV256

Prescaler: GCLK_TC/256

0x7 : DIV1024

Prescaler: GCLK_TC/1024

End of enumeration elements list.

ALOCK : Auto Lock
bits : 11 - 11 (1 bit)

CAPTEN0 : Capture Channel 0 Enable
bits : 16 - 16 (1 bit)

CAPTEN1 : Capture Channel 1 Enable
bits : 17 - 17 (1 bit)

COPEN0 : Capture On Pin 0 Enable
bits : 20 - 20 (1 bit)

COPEN1 : Capture On Pin 1 Enable
bits : 21 - 21 (1 bit)


TC_COUNT8 - SYNCBUSY

8-bit Counter Mode - - Synchronization Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - SYNCBUSY TC_COUNT8 - SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE CTRLB STATUS COUNT PER CC0 CC1

SWRST : swrst
bits : 0 - 0 (1 bit)

ENABLE : enable
bits : 1 - 1 (1 bit)

CTRLB : CTRLB
bits : 2 - 2 (1 bit)

STATUS : STATUS
bits : 3 - 3 (1 bit)

COUNT : Counter
bits : 4 - 4 (1 bit)

PER : Period
bits : 5 - 5 (1 bit)

CC0 : Compare Channel 0
bits : 6 - 6 (1 bit)

CC1 : Compare Channel 1
bits : 7 - 7 (1 bit)


TC_COUNT16 - SYNCBUSY

16-bit Counter Mode - - Synchronization Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - SYNCBUSY TC_COUNT16 - SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE CTRLB STATUS COUNT PER CC0 CC1

SWRST : swrst
bits : 0 - 0 (1 bit)

ENABLE : enable
bits : 1 - 1 (1 bit)

CTRLB : CTRLB
bits : 2 - 2 (1 bit)

STATUS : STATUS
bits : 3 - 3 (1 bit)

COUNT : Counter
bits : 4 - 4 (1 bit)

PER : Period
bits : 5 - 5 (1 bit)

CC0 : Compare Channel 0
bits : 6 - 6 (1 bit)

CC1 : Compare Channel 1
bits : 7 - 7 (1 bit)


TC_COUNT32 - SYNCBUSY

32-bit Counter Mode - - Synchronization Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - SYNCBUSY TC_COUNT32 - SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE CTRLB STATUS COUNT PER CC0 CC1

SWRST : swrst
bits : 0 - 0 (1 bit)

ENABLE : enable
bits : 1 - 1 (1 bit)

CTRLB : CTRLB
bits : 2 - 2 (1 bit)

STATUS : STATUS
bits : 3 - 3 (1 bit)

COUNT : Counter
bits : 4 - 4 (1 bit)

PER : Period
bits : 5 - 5 (1 bit)

CC0 : Compare Channel 0
bits : 6 - 6 (1 bit)

CC1 : Compare Channel 1
bits : 7 - 7 (1 bit)


SYNCBUSY

Synchronization Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE CTRLB STATUS COUNT PER CC0 CC1

SWRST : swrst
bits : 0 - 0 (1 bit)

ENABLE : enable
bits : 1 - 1 (1 bit)

CTRLB : CTRLB
bits : 2 - 2 (1 bit)

STATUS : STATUS
bits : 3 - 3 (1 bit)

COUNT : Counter
bits : 4 - 4 (1 bit)

PER : Period
bits : 5 - 5 (1 bit)

CC0 : Compare Channel 0
bits : 6 - 6 (1 bit)

CC1 : Compare Channel 1
bits : 7 - 7 (1 bit)


TC_COUNT8 - COUNT

8-bit Counter Mode - - COUNT8 Count
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - COUNT TC_COUNT8 - COUNT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 0 - 7 (8 bit)


TC_COUNT16 - COUNT

16-bit Counter Mode - - COUNT16 Count
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - COUNT TC_COUNT16 - COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 0 - 15 (16 bit)


TC_COUNT32 - COUNT

32-bit Counter Mode - - COUNT32 Count
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - COUNT TC_COUNT32 - COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 0 - 31 (32 bit)


COUNT

COUNT32 Count
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNT COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 0 - 31 (32 bit)


TC_COUNT8 - PER

8-bit Counter Mode - - COUNT8 Period
address_offset : 0x1B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - PER TC_COUNT8 - PER read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PER

PER : Period Value
bits : 0 - 7 (8 bit)


PER

COUNT8 Period
address_offset : 0x1B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER PER read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PER

PER : Period Value
bits : 0 - 7 (8 bit)


CC0

COUNT32 Compare and Capture
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC0 CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Counter/Compare Value
bits : 0 - 31 (32 bit)


CC1

COUNT32 Compare and Capture
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC1 CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Counter/Compare Value
bits : 0 - 31 (32 bit)


TC_COUNT8 - PERBUF

8-bit Counter Mode - - COUNT8 Period Buffer
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - PERBUF TC_COUNT8 - PERBUF read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PERBUF

PERBUF : Period Buffer Value
bits : 0 - 7 (8 bit)


PERBUF

COUNT8 Period Buffer
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERBUF PERBUF read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PERBUF

PERBUF : Period Buffer Value
bits : 0 - 7 (8 bit)


CCBUF0

COUNT32 Compare and Capture Buffer
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF0 CCBUF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Counter/Compare Buffer Value
bits : 0 - 31 (32 bit)


CCBUF1

COUNT32 Compare and Capture Buffer
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCBUF1 CCBUF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Counter/Compare Buffer Value
bits : 0 - 31 (32 bit)


TC_COUNT8 - CC0

8-bit Counter Mode - - COUNT8 Compare and Capture
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - CC0 TC_COUNT8 - CC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CC

CC : Counter/Compare Value
bits : 0 - 7 (8 bit)


TC_COUNT16 - CC0

16-bit Counter Mode - - COUNT16 Compare and Capture
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - CC0 TC_COUNT16 - CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Counter/Compare Value
bits : 0 - 15 (16 bit)


TC_COUNT32 - CC0

32-bit Counter Mode - - COUNT32 Compare and Capture
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - CC0 TC_COUNT32 - CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Counter/Compare Value
bits : 0 - 31 (32 bit)


TC_COUNT8 - CTRLBCLR

8-bit Counter Mode - - Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - CTRLBCLR TC_COUNT8 - CTRLBCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIR LUPD ONESHOT CMD

DIR : Counter Direction
bits : 0 - 0 (1 bit)

LUPD : Lock Update
bits : 1 - 1 (1 bit)

ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)

CMD : Command
bits : 5 - 7 (3 bit)

Enumeration: CMDSelect

0x0 : NONE

No action

0x1 : RETRIGGER

Force a start, restart or retrigger

0x2 : STOP

Force a stop

0x3 : UPDATE

Force update of double-buffered register

0x4 : READSYNC

Force a read synchronization of COUNT

0x5 : DMAOS

One-shot DMA trigger

End of enumeration elements list.


TC_COUNT16 - CTRLBCLR

16-bit Counter Mode - - Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - CTRLBCLR TC_COUNT16 - CTRLBCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIR LUPD ONESHOT CMD

DIR : Counter Direction
bits : 0 - 0 (1 bit)

LUPD : Lock Update
bits : 1 - 1 (1 bit)

ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)

CMD : Command
bits : 5 - 7 (3 bit)

Enumeration: CMDSelect

0x0 : NONE

No action

0x1 : RETRIGGER

Force a start, restart or retrigger

0x2 : STOP

Force a stop

0x3 : UPDATE

Force update of double-buffered register

0x4 : READSYNC

Force a read synchronization of COUNT

0x5 : DMAOS

One-shot DMA trigger

End of enumeration elements list.


TC_COUNT32 - CTRLBCLR

32-bit Counter Mode - - Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - CTRLBCLR TC_COUNT32 - CTRLBCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIR LUPD ONESHOT CMD

DIR : Counter Direction
bits : 0 - 0 (1 bit)

LUPD : Lock Update
bits : 1 - 1 (1 bit)

ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)

CMD : Command
bits : 5 - 7 (3 bit)

Enumeration: CMDSelect

0x0 : NONE

No action

0x1 : RETRIGGER

Force a start, restart or retrigger

0x2 : STOP

Force a stop

0x3 : UPDATE

Force update of double-buffered register

0x4 : READSYNC

Force a read synchronization of COUNT

0x5 : DMAOS

One-shot DMA trigger

End of enumeration elements list.


CTRLBCLR

Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLBCLR CTRLBCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIR LUPD ONESHOT CMD

DIR : Counter Direction
bits : 0 - 0 (1 bit)

LUPD : Lock Update
bits : 1 - 1 (1 bit)

ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)

CMD : Command
bits : 5 - 7 (3 bit)

Enumeration: CMDSelect

0x0 : NONE

No action

0x1 : RETRIGGER

Force a start, restart or retrigger

0x2 : STOP

Force a stop

0x3 : UPDATE

Force update of double-buffered register

0x4 : READSYNC

Force a read synchronization of COUNT

0x5 : DMAOS

One-shot DMA trigger

End of enumeration elements list.


TC_COUNT8 - CTRLBSET

8-bit Counter Mode - - Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - CTRLBSET TC_COUNT8 - CTRLBSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIR LUPD ONESHOT CMD

DIR : Counter Direction
bits : 0 - 0 (1 bit)

LUPD : Lock Update
bits : 1 - 1 (1 bit)

ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)

CMD : Command
bits : 5 - 7 (3 bit)

Enumeration: CMDSelect

0x0 : NONE

No action

0x1 : RETRIGGER

Force a start, restart or retrigger

0x2 : STOP

Force a stop

0x3 : UPDATE

Force update of double-buffered register

0x4 : READSYNC

Force a read synchronization of COUNT

0x5 : DMAOS

One-shot DMA trigger

End of enumeration elements list.


TC_COUNT16 - CTRLBSET

16-bit Counter Mode - - Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - CTRLBSET TC_COUNT16 - CTRLBSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIR LUPD ONESHOT CMD

DIR : Counter Direction
bits : 0 - 0 (1 bit)

LUPD : Lock Update
bits : 1 - 1 (1 bit)

ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)

CMD : Command
bits : 5 - 7 (3 bit)

Enumeration: CMDSelect

0x0 : NONE

No action

0x1 : RETRIGGER

Force a start, restart or retrigger

0x2 : STOP

Force a stop

0x3 : UPDATE

Force update of double-buffered register

0x4 : READSYNC

Force a read synchronization of COUNT

0x5 : DMAOS

One-shot DMA trigger

End of enumeration elements list.


TC_COUNT32 - CTRLBSET

32-bit Counter Mode - - Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - CTRLBSET TC_COUNT32 - CTRLBSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIR LUPD ONESHOT CMD

DIR : Counter Direction
bits : 0 - 0 (1 bit)

LUPD : Lock Update
bits : 1 - 1 (1 bit)

ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)

CMD : Command
bits : 5 - 7 (3 bit)

Enumeration: CMDSelect

0x0 : NONE

No action

0x1 : RETRIGGER

Force a start, restart or retrigger

0x2 : STOP

Force a stop

0x3 : UPDATE

Force update of double-buffered register

0x4 : READSYNC

Force a read synchronization of COUNT

0x5 : DMAOS

One-shot DMA trigger

End of enumeration elements list.


CTRLBSET

Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLBSET CTRLBSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIR LUPD ONESHOT CMD

DIR : Counter Direction
bits : 0 - 0 (1 bit)

LUPD : Lock Update
bits : 1 - 1 (1 bit)

ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)

CMD : Command
bits : 5 - 7 (3 bit)

Enumeration: CMDSelect

0x0 : NONE

No action

0x1 : RETRIGGER

Force a start, restart or retrigger

0x2 : STOP

Force a stop

0x3 : UPDATE

Force update of double-buffered register

0x4 : READSYNC

Force a read synchronization of COUNT

0x5 : DMAOS

One-shot DMA trigger

End of enumeration elements list.


TC_COUNT8 - CC1

8-bit Counter Mode - - COUNT8 Compare and Capture
address_offset : 0x55 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - CC1 TC_COUNT8 - CC1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CC

CC : Counter/Compare Value
bits : 0 - 7 (8 bit)


TC_COUNT16 - CC1

16-bit Counter Mode - - COUNT16 Compare and Capture
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - CC1 TC_COUNT16 - CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Counter/Compare Value
bits : 0 - 15 (16 bit)


TC_COUNT32 - CC1

32-bit Counter Mode - - COUNT32 Compare and Capture
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - CC1 TC_COUNT32 - CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC

CC : Counter/Compare Value
bits : 0 - 31 (32 bit)


TC_COUNT8 - EVCTRL

8-bit Counter Mode - - Event Control
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - EVCTRL TC_COUNT8 - EVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVACT TCINV TCEI OVFEO MCEO0 MCEO1

EVACT : Event Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : OFF

Event action disabled

0x1 : RETRIGGER

Start, restart or retrigger TC on event

0x2 : COUNT

Count on event

0x3 : START

Start TC on event

0x4 : STAMP

Time stamp capture

0x5 : PPW

Period catured in CC0, pulse width in CC1

0x6 : PWP

Period catured in CC1, pulse width in CC0

0x7 : PW

Pulse width capture

End of enumeration elements list.

TCINV : TC Event Input Polarity
bits : 4 - 4 (1 bit)

TCEI : TC Event Enable
bits : 5 - 5 (1 bit)

OVFEO : Event Output Enable
bits : 8 - 8 (1 bit)

MCEO0 : MC Event Output Enable 0
bits : 12 - 12 (1 bit)

MCEO1 : MC Event Output Enable 1
bits : 13 - 13 (1 bit)


TC_COUNT16 - EVCTRL

16-bit Counter Mode - - Event Control
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - EVCTRL TC_COUNT16 - EVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVACT TCINV TCEI OVFEO MCEO0 MCEO1

EVACT : Event Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : OFF

Event action disabled

0x1 : RETRIGGER

Start, restart or retrigger TC on event

0x2 : COUNT

Count on event

0x3 : START

Start TC on event

0x4 : STAMP

Time stamp capture

0x5 : PPW

Period catured in CC0, pulse width in CC1

0x6 : PWP

Period catured in CC1, pulse width in CC0

0x7 : PW

Pulse width capture

End of enumeration elements list.

TCINV : TC Event Input Polarity
bits : 4 - 4 (1 bit)

TCEI : TC Event Enable
bits : 5 - 5 (1 bit)

OVFEO : Event Output Enable
bits : 8 - 8 (1 bit)

MCEO0 : MC Event Output Enable 0
bits : 12 - 12 (1 bit)

MCEO1 : MC Event Output Enable 1
bits : 13 - 13 (1 bit)


TC_COUNT32 - EVCTRL

32-bit Counter Mode - - Event Control
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - EVCTRL TC_COUNT32 - EVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVACT TCINV TCEI OVFEO MCEO0 MCEO1

EVACT : Event Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : OFF

Event action disabled

0x1 : RETRIGGER

Start, restart or retrigger TC on event

0x2 : COUNT

Count on event

0x3 : START

Start TC on event

0x4 : STAMP

Time stamp capture

0x5 : PPW

Period catured in CC0, pulse width in CC1

0x6 : PWP

Period catured in CC1, pulse width in CC0

0x7 : PW

Pulse width capture

End of enumeration elements list.

TCINV : TC Event Input Polarity
bits : 4 - 4 (1 bit)

TCEI : TC Event Enable
bits : 5 - 5 (1 bit)

OVFEO : Event Output Enable
bits : 8 - 8 (1 bit)

MCEO0 : MC Event Output Enable 0
bits : 12 - 12 (1 bit)

MCEO1 : MC Event Output Enable 1
bits : 13 - 13 (1 bit)


EVCTRL

Event Control
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCTRL EVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVACT TCINV TCEI OVFEO MCEO0 MCEO1

EVACT : Event Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : OFF

Event action disabled

0x1 : RETRIGGER

Start, restart or retrigger TC on event

0x2 : COUNT

Count on event

0x3 : START

Start TC on event

0x4 : STAMP

Time stamp capture

0x5 : PPW

Period captured in CC0, pulse width in CC1

0x6 : PWP

Period captured in CC1, pulse width in CC0

0x7 : PW

Pulse width capture

End of enumeration elements list.

TCINV : TC Event Input Polarity
bits : 4 - 4 (1 bit)

TCEI : TC Event Enable
bits : 5 - 5 (1 bit)

OVFEO : Event Output Enable
bits : 8 - 8 (1 bit)

MCEO0 : MC Event Output Enable 0
bits : 12 - 12 (1 bit)

MCEO1 : MC Event Output Enable 1
bits : 13 - 13 (1 bit)


TC_COUNT8 - CCBUF0

8-bit Counter Mode - - COUNT8 Compare and Capture Buffer
address_offset : 0x60 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - CCBUF0 TC_COUNT8 - CCBUF0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Counter/Compare Buffer Value
bits : 0 - 7 (8 bit)


TC_COUNT16 - CCBUF0

16-bit Counter Mode - - COUNT16 Compare and Capture Buffer
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - CCBUF0 TC_COUNT16 - CCBUF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Counter/Compare Buffer Value
bits : 0 - 15 (16 bit)


TC_COUNT32 - CCBUF0

32-bit Counter Mode - - COUNT32 Compare and Capture Buffer
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - CCBUF0 TC_COUNT32 - CCBUF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Counter/Compare Buffer Value
bits : 0 - 31 (32 bit)


TC_COUNT8 - INTENCLR

8-bit Counter Mode - - Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - INTENCLR TC_COUNT8 - INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR MC0 MC1

OVF : OVF Interrupt Disable
bits : 0 - 0 (1 bit)

ERR : ERR Interrupt Disable
bits : 1 - 1 (1 bit)

MC0 : MC Interrupt Disable 0
bits : 4 - 4 (1 bit)

MC1 : MC Interrupt Disable 1
bits : 5 - 5 (1 bit)


TC_COUNT16 - INTENCLR

16-bit Counter Mode - - Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - INTENCLR TC_COUNT16 - INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR MC0 MC1

OVF : OVF Interrupt Disable
bits : 0 - 0 (1 bit)

ERR : ERR Interrupt Disable
bits : 1 - 1 (1 bit)

MC0 : MC Interrupt Disable 0
bits : 4 - 4 (1 bit)

MC1 : MC Interrupt Disable 1
bits : 5 - 5 (1 bit)


TC_COUNT32 - INTENCLR

32-bit Counter Mode - - Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - INTENCLR TC_COUNT32 - INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR MC0 MC1

OVF : OVF Interrupt Disable
bits : 0 - 0 (1 bit)

ERR : ERR Interrupt Disable
bits : 1 - 1 (1 bit)

MC0 : MC Interrupt Disable 0
bits : 4 - 4 (1 bit)

MC1 : MC Interrupt Disable 1
bits : 5 - 5 (1 bit)


INTENCLR

Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR MC0 MC1

OVF : OVF Interrupt Disable
bits : 0 - 0 (1 bit)

ERR : ERR Interrupt Disable
bits : 1 - 1 (1 bit)

MC0 : MC Interrupt Disable 0
bits : 4 - 4 (1 bit)

MC1 : MC Interrupt Disable 1
bits : 5 - 5 (1 bit)


TC_COUNT8 - INTENSET

8-bit Counter Mode - - Interrupt Enable Set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - INTENSET TC_COUNT8 - INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR MC0 MC1

OVF : OVF Interrupt Enable
bits : 0 - 0 (1 bit)

ERR : ERR Interrupt Enable
bits : 1 - 1 (1 bit)

MC0 : MC Interrupt Enable 0
bits : 4 - 4 (1 bit)

MC1 : MC Interrupt Enable 1
bits : 5 - 5 (1 bit)


TC_COUNT16 - INTENSET

16-bit Counter Mode - - Interrupt Enable Set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - INTENSET TC_COUNT16 - INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR MC0 MC1

OVF : OVF Interrupt Enable
bits : 0 - 0 (1 bit)

ERR : ERR Interrupt Enable
bits : 1 - 1 (1 bit)

MC0 : MC Interrupt Enable 0
bits : 4 - 4 (1 bit)

MC1 : MC Interrupt Enable 1
bits : 5 - 5 (1 bit)


TC_COUNT32 - INTENSET

32-bit Counter Mode - - Interrupt Enable Set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - INTENSET TC_COUNT32 - INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR MC0 MC1

OVF : OVF Interrupt Enable
bits : 0 - 0 (1 bit)

ERR : ERR Interrupt Enable
bits : 1 - 1 (1 bit)

MC0 : MC Interrupt Enable 0
bits : 4 - 4 (1 bit)

MC1 : MC Interrupt Enable 1
bits : 5 - 5 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR MC0 MC1

OVF : OVF Interrupt Enable
bits : 0 - 0 (1 bit)

ERR : ERR Interrupt Enable
bits : 1 - 1 (1 bit)

MC0 : MC Interrupt Enable 0
bits : 4 - 4 (1 bit)

MC1 : MC Interrupt Enable 1
bits : 5 - 5 (1 bit)


TC_COUNT8 - CCBUF1

8-bit Counter Mode - - COUNT8 Compare and Capture Buffer
address_offset : 0x91 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - CCBUF1 TC_COUNT8 - CCBUF1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Counter/Compare Buffer Value
bits : 0 - 7 (8 bit)


TC_COUNT16 - CCBUF1

16-bit Counter Mode - - COUNT16 Compare and Capture Buffer
address_offset : 0x92 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - CCBUF1 TC_COUNT16 - CCBUF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Counter/Compare Buffer Value
bits : 0 - 15 (16 bit)


TC_COUNT32 - CCBUF1

32-bit Counter Mode - - COUNT32 Compare and Capture Buffer
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - CCBUF1 TC_COUNT32 - CCBUF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCBUF

CCBUF : Counter/Compare Buffer Value
bits : 0 - 31 (32 bit)


TC_COUNT8 - INTFLAG

8-bit Counter Mode - - Interrupt Flag Status and Clear
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - INTFLAG TC_COUNT8 - INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR MC0 MC1

OVF : OVF Interrupt Flag
bits : 0 - 0 (1 bit)

ERR : ERR Interrupt Flag
bits : 1 - 1 (1 bit)

MC0 : MC Interrupt Flag 0
bits : 4 - 4 (1 bit)

MC1 : MC Interrupt Flag 1
bits : 5 - 5 (1 bit)


TC_COUNT16 - INTFLAG

16-bit Counter Mode - - Interrupt Flag Status and Clear
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - INTFLAG TC_COUNT16 - INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR MC0 MC1

OVF : OVF Interrupt Flag
bits : 0 - 0 (1 bit)

ERR : ERR Interrupt Flag
bits : 1 - 1 (1 bit)

MC0 : MC Interrupt Flag 0
bits : 4 - 4 (1 bit)

MC1 : MC Interrupt Flag 1
bits : 5 - 5 (1 bit)


TC_COUNT32 - INTFLAG

32-bit Counter Mode - - Interrupt Flag Status and Clear
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - INTFLAG TC_COUNT32 - INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR MC0 MC1

OVF : OVF Interrupt Flag
bits : 0 - 0 (1 bit)

ERR : ERR Interrupt Flag
bits : 1 - 1 (1 bit)

MC0 : MC Interrupt Flag 0
bits : 4 - 4 (1 bit)

MC1 : MC Interrupt Flag 1
bits : 5 - 5 (1 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF ERR MC0 MC1

OVF : OVF Interrupt Flag
bits : 0 - 0 (1 bit)

ERR : ERR Interrupt Flag
bits : 1 - 1 (1 bit)

MC0 : MC Interrupt Flag 0
bits : 4 - 4 (1 bit)

MC1 : MC Interrupt Flag 1
bits : 5 - 5 (1 bit)


TC_COUNT8 - STATUS

8-bit Counter Mode - - Status
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - STATUS TC_COUNT8 - STATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STOP SLAVE PERBUFV CCBUFV0 CCBUFV1

STOP : Stop Status Flag
bits : 0 - 0 (1 bit)
access : read-only

SLAVE : Slave Status Flag
bits : 1 - 1 (1 bit)
access : read-only

PERBUFV : Synchronization Busy Status
bits : 3 - 3 (1 bit)

CCBUFV0 : Compare channel buffer 0 valid
bits : 4 - 4 (1 bit)

CCBUFV1 : Compare channel buffer 1 valid
bits : 5 - 5 (1 bit)


TC_COUNT16 - STATUS

16-bit Counter Mode - - Status
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - STATUS TC_COUNT16 - STATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STOP SLAVE PERBUFV CCBUFV0 CCBUFV1

STOP : Stop Status Flag
bits : 0 - 0 (1 bit)
access : read-only

SLAVE : Slave Status Flag
bits : 1 - 1 (1 bit)
access : read-only

PERBUFV : Synchronization Busy Status
bits : 3 - 3 (1 bit)

CCBUFV0 : Compare channel buffer 0 valid
bits : 4 - 4 (1 bit)

CCBUFV1 : Compare channel buffer 1 valid
bits : 5 - 5 (1 bit)


TC_COUNT32 - STATUS

32-bit Counter Mode - - Status
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - STATUS TC_COUNT32 - STATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STOP SLAVE PERBUFV CCBUFV0 CCBUFV1

STOP : Stop Status Flag
bits : 0 - 0 (1 bit)
access : read-only

SLAVE : Slave Status Flag
bits : 1 - 1 (1 bit)
access : read-only

PERBUFV : Synchronization Busy Status
bits : 3 - 3 (1 bit)

CCBUFV0 : Compare channel buffer 0 valid
bits : 4 - 4 (1 bit)

CCBUFV1 : Compare channel buffer 1 valid
bits : 5 - 5 (1 bit)


STATUS

Status
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STOP SLAVE PERBUFV CCBUFV0 CCBUFV1

STOP : Stop Status Flag
bits : 0 - 0 (1 bit)
access : read-only

SLAVE : Slave Status Flag
bits : 1 - 1 (1 bit)
access : read-only

PERBUFV : Synchronization Busy Status
bits : 3 - 3 (1 bit)

CCBUFV0 : Compare channel buffer 0 valid
bits : 4 - 4 (1 bit)

CCBUFV1 : Compare channel buffer 1 valid
bits : 5 - 5 (1 bit)


TC_COUNT8 - WAVE

8-bit Counter Mode - - Waveform Generation Control
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - WAVE TC_COUNT8 - WAVE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WAVEGEN

WAVEGEN : Waveform Generation Mode
bits : 0 - 1 (2 bit)

Enumeration: WAVEGENSelect

0x0 : NFRQ

Normal frequency

0x1 : MFRQ

Match frequency

0x2 : NPWM

Normal PWM

0x3 : MPWM

Match PWM

End of enumeration elements list.


TC_COUNT16 - WAVE

16-bit Counter Mode - - Waveform Generation Control
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - WAVE TC_COUNT16 - WAVE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WAVEGEN

WAVEGEN : Waveform Generation Mode
bits : 0 - 1 (2 bit)

Enumeration: WAVEGENSelect

0x0 : NFRQ

Normal frequency

0x1 : MFRQ

Match frequency

0x2 : NPWM

Normal PWM

0x3 : MPWM

Match PWM

End of enumeration elements list.


TC_COUNT32 - WAVE

32-bit Counter Mode - - Waveform Generation Control
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - WAVE TC_COUNT32 - WAVE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WAVEGEN

WAVEGEN : Waveform Generation Mode
bits : 0 - 1 (2 bit)

Enumeration: WAVEGENSelect

0x0 : NFRQ

Normal frequency

0x1 : MFRQ

Match frequency

0x2 : NPWM

Normal PWM

0x3 : MPWM

Match PWM

End of enumeration elements list.


WAVE

Waveform Generation Control
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAVE WAVE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WAVEGEN

WAVEGEN : Waveform Generation Mode
bits : 0 - 1 (2 bit)

Enumeration: WAVEGENSelect

0x0 : NFRQ

Normal frequency

0x1 : MFRQ

Match frequency

0x2 : NPWM

Normal PWM

0x3 : MPWM

Match PWM

End of enumeration elements list.


TC_COUNT8 - DRVCTRL

8-bit Counter Mode - - Control C
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - DRVCTRL TC_COUNT8 - DRVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INVEN0 INVEN1

INVEN0 : Output Waveform Invert Enable 0
bits : 0 - 0 (1 bit)

INVEN1 : Output Waveform Invert Enable 1
bits : 1 - 1 (1 bit)


TC_COUNT16 - DRVCTRL

16-bit Counter Mode - - Control C
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - DRVCTRL TC_COUNT16 - DRVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INVEN0 INVEN1

INVEN0 : Output Waveform Invert Enable 0
bits : 0 - 0 (1 bit)

INVEN1 : Output Waveform Invert Enable 1
bits : 1 - 1 (1 bit)


TC_COUNT32 - DRVCTRL

32-bit Counter Mode - - Control C
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - DRVCTRL TC_COUNT32 - DRVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INVEN0 INVEN1

INVEN0 : Output Waveform Invert Enable 0
bits : 0 - 0 (1 bit)

INVEN1 : Output Waveform Invert Enable 1
bits : 1 - 1 (1 bit)


DRVCTRL

Control C
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRVCTRL DRVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INVEN0 INVEN1

INVEN0 : Output Waveform Invert Enable 0
bits : 0 - 0 (1 bit)

INVEN1 : Output Waveform Invert Enable 1
bits : 1 - 1 (1 bit)


TC_COUNT8 - DBGCTRL

8-bit Counter Mode - - Debug Control
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT8 - DBGCTRL TC_COUNT8 - DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Run During Debug
bits : 0 - 0 (1 bit)


TC_COUNT16 - DBGCTRL

16-bit Counter Mode - - Debug Control
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT16 - DBGCTRL TC_COUNT16 - DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Run During Debug
bits : 0 - 0 (1 bit)


TC_COUNT32 - DBGCTRL

32-bit Counter Mode - - Debug Control
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC_COUNT32 - DBGCTRL TC_COUNT32 - DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Run During Debug
bits : 0 - 0 (1 bit)


DBGCTRL

Debug Control
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCTRL DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Run During Debug
bits : 0 - 0 (1 bit)



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