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PAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

WRCTRL

INTFLAGAHB

INTFLAGA

INTFLAGB

INTFLAGC

INTFLAGD

INTFLAGE

STATUSA

STATUSB

STATUSC

EVCTRL

STATUSD

STATUSE

INTENCLR

INTENSET


WRCTRL

Write control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRCTRL WRCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERID KEY

PERID : Peripheral identifier
bits : 0 - 15 (16 bit)

KEY : Peripheral access control key
bits : 16 - 23 (8 bit)

Enumeration: KEYSelect

0x0 : OFF

No action

0x1 : CLR

Clear protection

0x2 : SET

Set protection

0x3 : SETLCK

Set and lock protection

End of enumeration elements list.


INTFLAGAHB

Bridge interrupt flag status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAGAHB INTFLAGAHB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_ HSRAMCM0P_ HSRAMDSU_ HPB1_ H2LBRIDGES_ HPB0_ HPB2_ HPB3_ HPB4_ PICOPRAM_ LPRAMHS_ LPRAMPICOP_ LPRAMDMAC_ L2HBRIDGES_ HSRAMLP_

FLASH_ : FLASH
bits : 0 - 0 (1 bit)

HSRAMCM0P_ : HSRAMCM0P
bits : 1 - 1 (1 bit)

HSRAMDSU_ : HSRAMDSU
bits : 2 - 2 (1 bit)

HPB1_ : HPB1
bits : 3 - 3 (1 bit)

H2LBRIDGES_ : H2LBRIDGES
bits : 4 - 4 (1 bit)

HPB0_ : HPB0
bits : 16 - 16 (1 bit)

HPB2_ : HPB2
bits : 17 - 17 (1 bit)

HPB3_ : HPB3
bits : 18 - 18 (1 bit)

HPB4_ : HPB4
bits : 19 - 19 (1 bit)

PICOPRAM_ : PICOPRAM
bits : 20 - 20 (1 bit)

LPRAMHS_ : LPRAMHS
bits : 21 - 21 (1 bit)

LPRAMPICOP_ : LPRAMPICOP
bits : 22 - 22 (1 bit)

LPRAMDMAC_ : LPRAMDMAC
bits : 23 - 23 (1 bit)

L2HBRIDGES_ : L2HBRIDGES
bits : 24 - 24 (1 bit)

HSRAMLP_ : HSRAMLP
bits : 25 - 25 (1 bit)


INTFLAGA

Peripheral interrupt flag status - Bridge A
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAGA INTFLAGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PM_ MCLK_ RSTC_ OSCCTRL_ OSC32KCTRL_ SUPC_ GCLK_ WDT_ RTC_ EIC_ PORT_ TAL_

PM_ : PM
bits : 0 - 0 (1 bit)

MCLK_ : MCLK
bits : 1 - 1 (1 bit)

RSTC_ : RSTC
bits : 2 - 2 (1 bit)

OSCCTRL_ : OSCCTRL
bits : 3 - 3 (1 bit)

OSC32KCTRL_ : OSC32KCTRL
bits : 4 - 4 (1 bit)

SUPC_ : SUPC
bits : 5 - 5 (1 bit)

GCLK_ : GCLK
bits : 6 - 6 (1 bit)

WDT_ : WDT
bits : 7 - 7 (1 bit)

RTC_ : RTC
bits : 8 - 8 (1 bit)

EIC_ : EIC
bits : 9 - 9 (1 bit)

PORT_ : PORT
bits : 10 - 10 (1 bit)

TAL_ : TAL
bits : 11 - 11 (1 bit)


INTFLAGB

Peripheral interrupt flag status - Bridge B
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAGB INTFLAGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_ DSU_ NVMCTRL_ MTB_

USB_ : USB
bits : 0 - 0 (1 bit)

DSU_ : DSU
bits : 1 - 1 (1 bit)

NVMCTRL_ : NVMCTRL
bits : 2 - 2 (1 bit)

MTB_ : MTB
bits : 3 - 3 (1 bit)


INTFLAGC

Peripheral interrupt flag status - Bridge C
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAGC INTFLAGC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SERCOM0_ SERCOM1_ SERCOM2_ SERCOM3_ SERCOM4_ TCC0_ TCC1_ TCC2_ TC0_ TC1_ DAC_ AES_ TRNG_

SERCOM0_ : SERCOM0
bits : 0 - 0 (1 bit)

SERCOM1_ : SERCOM1
bits : 1 - 1 (1 bit)

SERCOM2_ : SERCOM2
bits : 2 - 2 (1 bit)

SERCOM3_ : SERCOM3
bits : 3 - 3 (1 bit)

SERCOM4_ : SERCOM4
bits : 4 - 4 (1 bit)

TCC0_ : TCC0
bits : 5 - 5 (1 bit)

TCC1_ : TCC1
bits : 6 - 6 (1 bit)

TCC2_ : TCC2
bits : 7 - 7 (1 bit)

TC0_ : TC0
bits : 8 - 8 (1 bit)

TC1_ : TC1
bits : 9 - 9 (1 bit)

DAC_ : DAC
bits : 12 - 12 (1 bit)

AES_ : AES
bits : 13 - 13 (1 bit)

TRNG_ : TRNG
bits : 14 - 14 (1 bit)


INTFLAGD

Peripheral interrupt flag status - Bridge D
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAGD INTFLAGD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVSYS_ SERCOM5_ TC4_ ADC_ AC_ PTC_ OPAMP_ CCL_

EVSYS_ : EVSYS
bits : 0 - 0 (1 bit)

SERCOM5_ : SERCOM5
bits : 1 - 1 (1 bit)

TC4_ : TC4
bits : 2 - 2 (1 bit)

ADC_ : ADC
bits : 3 - 3 (1 bit)

AC_ : AC
bits : 4 - 4 (1 bit)

PTC_ : PTC
bits : 5 - 5 (1 bit)

OPAMP_ : OPAMP
bits : 6 - 6 (1 bit)

CCL_ : CCL
bits : 7 - 7 (1 bit)


INTFLAGE

Peripheral interrupt flag status - Bridge E
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAGE INTFLAGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAC_ DMAC_

PAC_ : PAC
bits : 0 - 0 (1 bit)

DMAC_ : DMAC
bits : 1 - 1 (1 bit)


STATUSA

Peripheral write protection status - Bridge A
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUSA STATUSA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PM_ MCLK_ RSTC_ OSCCTRL_ OSC32KCTRL_ SUPC_ GCLK_ WDT_ RTC_ EIC_ PORT_ TAL_

PM_ : PM APB Protect Enable
bits : 0 - 0 (1 bit)

MCLK_ : MCLK APB Protect Enable
bits : 1 - 1 (1 bit)

RSTC_ : RSTC APB Protect Enable
bits : 2 - 2 (1 bit)

OSCCTRL_ : OSCCTRL APB Protect Enable
bits : 3 - 3 (1 bit)

OSC32KCTRL_ : OSC32KCTRL APB Protect Enable
bits : 4 - 4 (1 bit)

SUPC_ : SUPC APB Protect Enable
bits : 5 - 5 (1 bit)

GCLK_ : GCLK APB Protect Enable
bits : 6 - 6 (1 bit)

WDT_ : WDT APB Protect Enable
bits : 7 - 7 (1 bit)

RTC_ : RTC APB Protect Enable
bits : 8 - 8 (1 bit)

EIC_ : EIC APB Protect Enable
bits : 9 - 9 (1 bit)

PORT_ : PORT APB Protect Enable
bits : 10 - 10 (1 bit)

TAL_ : TAL APB Protect Enable
bits : 11 - 11 (1 bit)


STATUSB

Peripheral write protection status - Bridge B
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUSB STATUSB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_ DSU_ NVMCTRL_ MTB_

USB_ : USB APB Protect Enable
bits : 0 - 0 (1 bit)

DSU_ : DSU APB Protect Enable
bits : 1 - 1 (1 bit)

NVMCTRL_ : NVMCTRL APB Protect Enable
bits : 2 - 2 (1 bit)

MTB_ : MTB APB Protect Enable
bits : 3 - 3 (1 bit)


STATUSC

Peripheral write protection status - Bridge C
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUSC STATUSC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SERCOM0_ SERCOM1_ SERCOM2_ SERCOM3_ SERCOM4_ TCC0_ TCC1_ TCC2_ TC0_ TC1_ DAC_ AES_ TRNG_

SERCOM0_ : SERCOM0 APB Protect Enable
bits : 0 - 0 (1 bit)

SERCOM1_ : SERCOM1 APB Protect Enable
bits : 1 - 1 (1 bit)

SERCOM2_ : SERCOM2 APB Protect Enable
bits : 2 - 2 (1 bit)

SERCOM3_ : SERCOM3 APB Protect Enable
bits : 3 - 3 (1 bit)

SERCOM4_ : SERCOM4 APB Protect Enable
bits : 4 - 4 (1 bit)

TCC0_ : TCC0 APB Protect Enable
bits : 5 - 5 (1 bit)

TCC1_ : TCC1 APB Protect Enable
bits : 6 - 6 (1 bit)

TCC2_ : TCC2 APB Protect Enable
bits : 7 - 7 (1 bit)

TC0_ : TC0 APB Protect Enable
bits : 8 - 8 (1 bit)

TC1_ : TC1 APB Protect Enable
bits : 9 - 9 (1 bit)

DAC_ : DAC APB Protect Enable
bits : 12 - 12 (1 bit)

AES_ : AES APB Protect Enable
bits : 13 - 13 (1 bit)

TRNG_ : TRNG APB Protect Enable
bits : 14 - 14 (1 bit)


EVCTRL

Event control
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCTRL EVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ERREO

ERREO : Peripheral acess error event output
bits : 0 - 0 (1 bit)


STATUSD

Peripheral write protection status - Bridge D
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUSD STATUSD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVSYS_ SERCOM5_ TC4_ ADC_ AC_ PTC_ OPAMP_ CCL_

EVSYS_ : EVSYS APB Protect Enable
bits : 0 - 0 (1 bit)

SERCOM5_ : SERCOM5 APB Protect Enable
bits : 1 - 1 (1 bit)

TC4_ : TC4 APB Protect Enable
bits : 2 - 2 (1 bit)

ADC_ : ADC APB Protect Enable
bits : 3 - 3 (1 bit)

AC_ : AC APB Protect Enable
bits : 4 - 4 (1 bit)

PTC_ : PTC APB Protect Enable
bits : 5 - 5 (1 bit)

OPAMP_ : OPAMP APB Protect Enable
bits : 6 - 6 (1 bit)

CCL_ : CCL APB Protect Enable
bits : 7 - 7 (1 bit)


STATUSE

Peripheral write protection status - Bridge E
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUSE STATUSE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAC_ DMAC_

PAC_ : PAC APB Protect Enable
bits : 0 - 0 (1 bit)

DMAC_ : DMAC APB Protect Enable
bits : 1 - 1 (1 bit)


INTENCLR

Interrupt enable clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ERR

ERR : Peripheral access error interrupt disable
bits : 0 - 0 (1 bit)


INTENSET

Interrupt enable set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ERR

ERR : Peripheral access error interrupt enable
bits : 0 - 0 (1 bit)



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