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DAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRLA

CTRLB

DACCTRL0

DBGCTRL

EVCTRL

DATA0

DACCTRL1

DATABUF0

DATA1

DATABUF1

INTENCLR

INTENSET

INTFLAG

STATUS

SYNCBUSY


CTRLA

Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST ENABLE

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable DAC Controller
bits : 1 - 1 (1 bit)


CTRLB

Control B
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLB CTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DIFF REFSEL

DIFF : Differential mode enable
bits : 0 - 0 (1 bit)

REFSEL : Reference Selection for DAC0/1
bits : 1 - 2 (2 bit)

Enumeration: REFSELSelect

0x0 : VREFPU

External reference unbuffered

0x1 : VDDANA

Analog supply

0x2 : VREFPB

External reference buffered

0x3 : INTREF

Internal bandgap reference

End of enumeration elements list.


DACCTRL0

DAC n Control
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACCTRL0 DACCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEFTADJ ENABLE CCTRL RUNSTDBY DITHER REFRESH

LEFTADJ : Left Adjusted Data
bits : 0 - 0 (1 bit)

ENABLE : Enable DAC0
bits : 1 - 1 (1 bit)

CCTRL : Current Control
bits : 2 - 3 (2 bit)

Enumeration: CCTRLSelect

0x0 : CC12M

1MHz

0x1 : CC1M

100kHz

0x2 : CC100K

10kHz

0x3 : CC10K

GCLK_DAC<100kHz

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

DITHER : Dithering Mode
bits : 7 - 7 (1 bit)

REFRESH : Refresh period
bits : 8 - 11 (4 bit)


DBGCTRL

Debug Control
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCTRL DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Debug Run
bits : 0 - 0 (1 bit)


EVCTRL

Event Control
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCTRL EVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STARTEI0 STARTEI1 EMPTYEO0 EMPTYEO1 INVEI0 INVEI1

STARTEI0 : Start Conversion Event Input DAC 0
bits : 0 - 0 (1 bit)

STARTEI1 : Start Conversion Event Input DAC 1
bits : 1 - 1 (1 bit)

EMPTYEO0 : Data Buffer Empty Event Output DAC 0
bits : 2 - 2 (1 bit)

EMPTYEO1 : Data Buffer Empty Event Output DAC 1
bits : 3 - 3 (1 bit)

INVEI0 : Enable Invertion of DAC 0 input event
bits : 4 - 4 (1 bit)

INVEI1 : Enable Invertion of DAC 1 input event
bits : 5 - 5 (1 bit)


DATA0

DAC n Data
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATA0 DATA0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DAC0 Data
bits : 0 - 15 (16 bit)
access : write-only


DACCTRL1

DAC n Control
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DACCTRL1 DACCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEFTADJ ENABLE CCTRL RUNSTDBY DITHER REFRESH

LEFTADJ : Left Adjusted Data
bits : 0 - 0 (1 bit)

ENABLE : Enable DAC0
bits : 1 - 1 (1 bit)

CCTRL : Current Control
bits : 2 - 3 (2 bit)

Enumeration: CCTRLSelect

0x0 : CC12M

1MHz

0x1 : CC1M

100kHz

0x2 : CC100K

10kHz

0x3 : CC10K

GCLK_DAC<100kHz

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

DITHER : Dithering Mode
bits : 7 - 7 (1 bit)

REFRESH : Refresh period
bits : 8 - 11 (4 bit)


DATABUF0

DAC n Data Buffer
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATABUF0 DATABUF0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATABUF

DATABUF : DAC0 Data Buffer
bits : 0 - 15 (16 bit)
access : write-only


DATA1

DAC n Data
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATA1 DATA1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DAC0 Data
bits : 0 - 15 (16 bit)
access : write-only


DATABUF1

DAC n Data Buffer
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DATABUF1 DATABUF1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATABUF

DATABUF : DAC0 Data Buffer
bits : 0 - 15 (16 bit)
access : write-only


INTENCLR

Interrupt Enable Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UNDERRUN0 UNDERRUN1 EMPTY0 EMPTY1

UNDERRUN0 : Underrun Interrupt Enable for DAC 0
bits : 0 - 0 (1 bit)

UNDERRUN1 : Underrun Interrupt Enable for DAC 1
bits : 1 - 1 (1 bit)

EMPTY0 : Data Buffer 0 Empty Interrupt Enable
bits : 2 - 2 (1 bit)

EMPTY1 : Data Buffer 1 Empty Interrupt Enable
bits : 3 - 3 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UNDERRUN0 UNDERRUN1 EMPTY0 EMPTY1

UNDERRUN0 : Underrun Interrupt Enable for DAC 0
bits : 0 - 0 (1 bit)

UNDERRUN1 : Underrun Interrupt Enable for DAC 1
bits : 1 - 1 (1 bit)

EMPTY0 : Data Buffer 0 Empty Interrupt Enable
bits : 2 - 2 (1 bit)

EMPTY1 : Data Buffer 1 Empty Interrupt Enable
bits : 3 - 3 (1 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UNDERRUN0 UNDERRUN1 EMPTY0 EMPTY1

UNDERRUN0 : DAC 0 Underrun
bits : 0 - 0 (1 bit)

UNDERRUN1 : DAC 1 Underrun
bits : 1 - 1 (1 bit)

EMPTY0 : Data Buffer 0 Empty
bits : 2 - 2 (1 bit)

EMPTY1 : Data Buffer 1 Empty
bits : 3 - 3 (1 bit)


STATUS

Status
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 READY0 READY1 EOC0 EOC1

READY0 : DAC 0 Startup Ready
bits : 0 - 0 (1 bit)
access : read-only

READY1 : DAC 1 Startup Ready
bits : 1 - 1 (1 bit)
access : read-only

EOC0 : DAC 0 End of Conversion
bits : 2 - 2 (1 bit)
access : read-only

EOC1 : DAC 1 End of Conversion
bits : 3 - 3 (1 bit)
access : read-only


SYNCBUSY

Synchronization Busy
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE DATA0 DATA1 DATABUF0 DATABUF1

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : read-only

ENABLE : DAC Enable Status
bits : 1 - 1 (1 bit)
access : read-only

DATA0 : Data DAC 0
bits : 2 - 2 (1 bit)
access : read-only

DATA1 : Data DAC 1
bits : 3 - 3 (1 bit)
access : read-only

DATABUF0 : Data Buffer DAC 0
bits : 4 - 4 (1 bit)
access : read-only

DATABUF1 : Data Buffer DAC 1
bits : 5 - 5 (1 bit)
access : read-only



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