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RSTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RCAUSE

WKCAUSE

BKUPEXIT

WKDBCONF

WKPOL

WKEN


RCAUSE

Reset Cause
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RCAUSE RCAUSE read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 POR BOD12 BOD33 EXT WDT SYST BACKUP

POR : Power On Reset
bits : 0 - 0 (1 bit)

BOD12 : Brown Out 12 Detector Reset
bits : 1 - 1 (1 bit)

BOD33 : Brown Out 33 Detector Reset
bits : 2 - 2 (1 bit)

EXT : External Reset
bits : 4 - 4 (1 bit)

WDT : Watchdog Reset
bits : 5 - 5 (1 bit)

SYST : System Reset Request
bits : 6 - 6 (1 bit)

BACKUP : Backup Reset
bits : 7 - 7 (1 bit)


WKCAUSE

Wakeup Cause
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKCAUSE WKCAUSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKCAUSE

WKCAUSE : Wakeup Cause
bits : 0 - 15 (16 bit)
access : read-only


BKUPEXIT

Backup Exit Source
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BKUPEXIT BKUPEXIT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EXTWAKE RTC BBPS

EXTWAKE : External Wakeup
bits : 0 - 0 (1 bit)
access : read-only

RTC : Real Timer Counter Interrupt
bits : 1 - 1 (1 bit)
access : read-only

BBPS : Battery Backup Power Switch
bits : 2 - 2 (1 bit)
access : read-only


WKDBCONF

Wakeup Debounce Configuration
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKDBCONF WKDBCONF read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WKDBCNT

WKDBCNT : Wakeup Debounce Counter
bits : 0 - 4 (5 bit)

Enumeration: WKDBCNTSelect

0x0 : OFF

No debouncing.Input pin is low or high level sensitive depending on its WKPOLx bit.

0x1 : 2CK32

Input pin shall be active for at least two 32kHz clock period.

0x2 : 3CK32

Input pin shall be active for at least three 32kHz clock period.

0x3 : 32CK32

Input pin shall be active for at least 32 32kHz clock period.

0x4 : 512CK32

Input pin shall be active for at least 512 32kHz clock period.

0x5 : 4096CK32

Input pin shall be active for at least 4096 32kHz clock period.

0x6 : 32768CK32

Input pin shall be active for at least 32768 32kHz clock period.

End of enumeration elements list.


WKPOL

Wakeup Polarity
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKPOL WKPOL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKPOL

WKPOL : Wakeup Polarity
bits : 0 - 7 (8 bit)


WKEN

Wakeup Enable
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WKEN WKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKEN

WKEN : Wakeup Enable
bits : 0 - 7 (8 bit)



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