\n
address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
Interrupt Enable Clear
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XOSCRDY : XOSC Ready Interrupt Enable
bits : 0 - 0 (1 bit)
OSC16MRDY : OSC16M Ready Interrupt Enable
bits : 4 - 4 (1 bit)
DFLLRDY : DFLL Ready Interrupt Enable
bits : 8 - 8 (1 bit)
DFLLOOB : DFLL Out Of Bounds Interrupt Enable
bits : 9 - 9 (1 bit)
DFLLLCKF : DFLL Lock Fine Interrupt Enable
bits : 10 - 10 (1 bit)
DFLLLCKC : DFLL Lock Coarse Interrupt Enable
bits : 11 - 11 (1 bit)
DFLLRCS : DFLL Reference Clock Stopped Interrupt Enable
bits : 12 - 12 (1 bit)
DPLLLCKR : DPLL Lock Rise Interrupt Enable
bits : 16 - 16 (1 bit)
DPLLLCKF : DPLL Lock Fall Interrupt Enable
bits : 17 - 17 (1 bit)
DPLLLTO : DPLL Time Out Interrupt Enable
bits : 18 - 18 (1 bit)
DPLLLDRTO : DPLL Ratio Ready Interrupt Enable
bits : 19 - 19 (1 bit)
External Multipurpose Crystal Oscillator (XOSC) Control
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Oscillator Enable
bits : 1 - 1 (1 bit)
XTALEN : Crystal Oscillator Enable
bits : 2 - 2 (1 bit)
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
GAIN : Oscillator Gain
bits : 8 - 10 (3 bit)
AMPGC : Automatic Amplitude Gain Control
bits : 11 - 11 (1 bit)
STARTUP : Start-Up Time
bits : 12 - 15 (4 bit)
16MHz Internal Oscillator (OSC16M) Control
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Oscillator Enable
bits : 1 - 1 (1 bit)
FSEL : Oscillator Frequency Select
bits : 2 - 3 (2 bit)
Enumeration: FSELSelect
0x0 : 4
4MHz
0x1 : 8
8MHz
0x2 : 12
12MHz
0x3 : 16
16MHz
End of enumeration elements list.
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
DFLL48M Control
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DFLL Enable
bits : 1 - 1 (1 bit)
MODE : Operating Mode Selection
bits : 2 - 2 (1 bit)
STABLE : Stable DFLL Frequency
bits : 3 - 3 (1 bit)
LLAW : Lose Lock After Wake
bits : 4 - 4 (1 bit)
USBCRM : USB Clock Recovery Mode
bits : 5 - 5 (1 bit)
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
CCDIS : Chill Cycle Disable
bits : 8 - 8 (1 bit)
QLDIS : Quick Lock Disable
bits : 9 - 9 (1 bit)
BPLCKC : Bypass Coarse Lock
bits : 10 - 10 (1 bit)
WAITLOCK : Wait Lock
bits : 11 - 11 (1 bit)
DFLL48M Value
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FINE : Fine Value
bits : 0 - 9 (10 bit)
COARSE : Coarse Value
bits : 10 - 15 (6 bit)
DIFF : Multiplication Ratio Difference
bits : 16 - 31 (16 bit)
access : read-only
DFLL48M Multiplier
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUL : DFLL Multiply Factor
bits : 0 - 15 (16 bit)
FSTEP : Fine Maximum Step
bits : 16 - 25 (10 bit)
CSTEP : Coarse Maximum Step
bits : 26 - 31 (6 bit)
DFLL48M Synchronization
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READREQ : Read Request
bits : 7 - 7 (1 bit)
access : write-only
DPLL Control
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand
bits : 7 - 7 (1 bit)
DPLL Ratio Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDR : Loop Divider Ratio
bits : 0 - 11 (12 bit)
LDRFRAC : Loop Divider Ratio Fractional Part
bits : 16 - 19 (4 bit)
Digital Core Configuration
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER : Proportional Integral Filter Selection
bits : 0 - 1 (2 bit)
LPEN : Low-Power Enable
bits : 2 - 2 (1 bit)
WUF : Wake Up Fast
bits : 3 - 3 (1 bit)
REFCLK : Reference Clock Selection
bits : 4 - 5 (2 bit)
LTIME : Lock Time
bits : 8 - 10 (3 bit)
LBYPASS : Lock Bypass
bits : 12 - 12 (1 bit)
DIV : Clock Divider
bits : 16 - 26 (11 bit)
DPLL Prescaler
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : Output Clock Prescaler
bits : 0 - 1 (2 bit)
Enumeration: PRESCSelect
0x0 : DIV1
DPLL output is divided by 1
0x1 : DIV2
DPLL output is divided by 2
0x2 : DIV4
DPLL output is divided by 4
End of enumeration elements list.
DPLL Synchronization Busy
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DPLL Enable Synchronization Status
bits : 1 - 1 (1 bit)
access : read-only
DPLLRATIO : DPLL Ratio Synchronization Status
bits : 2 - 2 (1 bit)
access : read-only
DPLLPRESC : DPLL Prescaler Synchronization Status
bits : 3 - 3 (1 bit)
access : read-only
DPLL Status
address_offset : 0x3C Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOCK : DPLL Lock Status
bits : 0 - 0 (1 bit)
access : read-only
CLKRDY : DPLL Clock Ready
bits : 1 - 1 (1 bit)
access : read-only
Interrupt Enable Set
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XOSCRDY : XOSC Ready Interrupt Enable
bits : 0 - 0 (1 bit)
OSC16MRDY : OSC16M Ready Interrupt Enable
bits : 4 - 4 (1 bit)
DFLLRDY : DFLL Ready Interrupt Enable
bits : 8 - 8 (1 bit)
DFLLOOB : DFLL Out Of Bounds Interrupt Enable
bits : 9 - 9 (1 bit)
DFLLLCKF : DFLL Lock Fine Interrupt Enable
bits : 10 - 10 (1 bit)
DFLLLCKC : DFLL Lock Coarse Interrupt Enable
bits : 11 - 11 (1 bit)
DFLLRCS : DFLL Reference Clock Stopped Interrupt Enable
bits : 12 - 12 (1 bit)
DPLLLCKR : DPLL Lock Rise Interrupt Enable
bits : 16 - 16 (1 bit)
DPLLLCKF : DPLL Lock Fall Interrupt Enable
bits : 17 - 17 (1 bit)
DPLLLTO : DPLL Time Out Interrupt Enable
bits : 18 - 18 (1 bit)
DPLLLDRTO : DPLL Ratio Ready Interrupt Enable
bits : 19 - 19 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XOSCRDY : XOSC Ready
bits : 0 - 0 (1 bit)
OSC16MRDY : OSC16M Ready
bits : 4 - 4 (1 bit)
DFLLRDY : DFLL Ready
bits : 8 - 8 (1 bit)
DFLLOOB : DFLL Out Of Bounds
bits : 9 - 9 (1 bit)
DFLLLCKF : DFLL Lock Fine
bits : 10 - 10 (1 bit)
DFLLLCKC : DFLL Lock Coarse
bits : 11 - 11 (1 bit)
DFLLRCS : DFLL Reference Clock Stopped
bits : 12 - 12 (1 bit)
DPLLLCKR : DPLL Lock Rise
bits : 16 - 16 (1 bit)
DPLLLCKF : DPLL Lock Fall
bits : 17 - 17 (1 bit)
DPLLLTO : DPLL Timeout
bits : 18 - 18 (1 bit)
DPLLLDRTO : DPLL Ratio Ready
bits : 19 - 19 (1 bit)
Power and Clocks Status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
XOSCRDY : XOSC Ready
bits : 0 - 0 (1 bit)
access : read-only
OSC16MRDY : OSC16M Ready
bits : 4 - 4 (1 bit)
access : read-only
DFLLRDY : DFLL Ready
bits : 8 - 8 (1 bit)
access : read-only
DFLLOOB : DFLL Out Of Bounds
bits : 9 - 9 (1 bit)
access : read-only
DFLLLCKF : DFLL Lock Fine
bits : 10 - 10 (1 bit)
access : read-only
DFLLLCKC : DFLL Lock Coarse
bits : 11 - 11 (1 bit)
access : read-only
DFLLRCS : DFLL Reference Clock Stopped
bits : 12 - 12 (1 bit)
access : read-only
DPLLLCKR : DPLL Lock Rise
bits : 16 - 16 (1 bit)
access : read-only
DPLLLCKF : DPLL Lock Fall
bits : 17 - 17 (1 bit)
access : read-only
DPLLTO : DPLL Timeout
bits : 18 - 18 (1 bit)
access : read-only
DPLLLDRTO : DPLL Ratio Ready
bits : 19 - 19 (1 bit)
access : read-only
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