\n
address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable DAC Controller
bits : 1 - 1 (1 bit)
Control B
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIFF : Differential mode enable
bits : 0 - 0 (1 bit)
REFSEL : Reference Selection for DAC0/1
bits : 1 - 2 (2 bit)
Enumeration: REFSELSelect
0x0 : VREFPU
External reference unbuffered
0x1 : VDDANA
Analog supply
0x2 : VREFPB
External reference buffered
0x3 : INTREF
Internal bandgap reference
End of enumeration elements list.
DAC n Control
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEFTADJ : Left Adjusted Data
bits : 0 - 0 (1 bit)
ENABLE : Enable DAC0
bits : 1 - 1 (1 bit)
CCTRL : Current Control
bits : 2 - 3 (2 bit)
Enumeration: CCTRLSelect
0x0 : CC12M
1MHz
0x1 : CC1M
100kHz
0x2 : CC100K
10kHz
0x3 : CC10K
GCLK_DAC<100kHz
End of enumeration elements list.
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
DITHER : Dithering Mode
bits : 7 - 7 (1 bit)
REFRESH : Refresh period
bits : 8 - 11 (4 bit)
Debug Control
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGRUN : Debug Run
bits : 0 - 0 (1 bit)
Event Control
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTEI0 : Start Conversion Event Input DAC 0
bits : 0 - 0 (1 bit)
STARTEI1 : Start Conversion Event Input DAC 1
bits : 1 - 1 (1 bit)
EMPTYEO0 : Data Buffer Empty Event Output DAC 0
bits : 2 - 2 (1 bit)
EMPTYEO1 : Data Buffer Empty Event Output DAC 1
bits : 3 - 3 (1 bit)
INVEI0 : Enable Invertion of DAC 0 input event
bits : 4 - 4 (1 bit)
INVEI1 : Enable Invertion of DAC 1 input event
bits : 5 - 5 (1 bit)
DAC n Data
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : DAC0 Data
bits : 0 - 15 (16 bit)
access : write-only
DAC n Control
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEFTADJ : Left Adjusted Data
bits : 0 - 0 (1 bit)
ENABLE : Enable DAC0
bits : 1 - 1 (1 bit)
CCTRL : Current Control
bits : 2 - 3 (2 bit)
Enumeration: CCTRLSelect
0x0 : CC12M
1MHz
0x1 : CC1M
100kHz
0x2 : CC100K
10kHz
0x3 : CC10K
GCLK_DAC<100kHz
End of enumeration elements list.
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
DITHER : Dithering Mode
bits : 7 - 7 (1 bit)
REFRESH : Refresh period
bits : 8 - 11 (4 bit)
DAC n Data Buffer
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF : DAC0 Data Buffer
bits : 0 - 15 (16 bit)
access : write-only
DAC n Data
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : DAC0 Data
bits : 0 - 15 (16 bit)
access : write-only
DAC n Data Buffer
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATABUF : DAC0 Data Buffer
bits : 0 - 15 (16 bit)
access : write-only
Interrupt Enable Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UNDERRUN0 : Underrun Interrupt Enable for DAC 0
bits : 0 - 0 (1 bit)
UNDERRUN1 : Underrun Interrupt Enable for DAC 1
bits : 1 - 1 (1 bit)
EMPTY0 : Data Buffer 0 Empty Interrupt Enable
bits : 2 - 2 (1 bit)
EMPTY1 : Data Buffer 1 Empty Interrupt Enable
bits : 3 - 3 (1 bit)
Interrupt Enable Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UNDERRUN0 : Underrun Interrupt Enable for DAC 0
bits : 0 - 0 (1 bit)
UNDERRUN1 : Underrun Interrupt Enable for DAC 1
bits : 1 - 1 (1 bit)
EMPTY0 : Data Buffer 0 Empty Interrupt Enable
bits : 2 - 2 (1 bit)
EMPTY1 : Data Buffer 1 Empty Interrupt Enable
bits : 3 - 3 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UNDERRUN0 : DAC 0 Underrun
bits : 0 - 0 (1 bit)
UNDERRUN1 : DAC 1 Underrun
bits : 1 - 1 (1 bit)
EMPTY0 : Data Buffer 0 Empty
bits : 2 - 2 (1 bit)
EMPTY1 : Data Buffer 1 Empty
bits : 3 - 3 (1 bit)
Status
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READY0 : DAC 0 Startup Ready
bits : 0 - 0 (1 bit)
access : read-only
READY1 : DAC 1 Startup Ready
bits : 1 - 1 (1 bit)
access : read-only
EOC0 : DAC 0 End of Conversion
bits : 2 - 2 (1 bit)
access : read-only
EOC1 : DAC 1 End of Conversion
bits : 3 - 3 (1 bit)
access : read-only
Synchronization Busy
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : read-only
ENABLE : DAC Enable Status
bits : 1 - 1 (1 bit)
access : read-only
DATA0 : Data DAC 0
bits : 2 - 2 (1 bit)
access : read-only
DATA1 : Data DAC 1
bits : 3 - 3 (1 bit)
access : read-only
DATABUF0 : Data Buffer DAC 0
bits : 4 - 4 (1 bit)
access : read-only
DATABUF1 : Data Buffer DAC 1
bits : 5 - 5 (1 bit)
access : read-only
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