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RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

MODE0 - CTRLA

MODE1 - CTRLA

MODE2 - CTRLA

CTRLA

MODE0 - SYNCBUSY

MODE1 - SYNCBUSY

MODE2 - SYNCBUSY

SYNCBUSY

MODE0 - GP2

MODE1 - GP2

MODE2 - GP2

MODE0 - FREQCORR

MODE1 - FREQCORR

MODE2 - FREQCORR

FREQCORR

MODE0 - GP3

MODE1 - GP3

MODE2 - GP3

MODE0 - COUNT

MODE1 - COUNT

MODE2 - CLOCK

COUNT

CLOCK

MODE1 - PER

PER

COMP0

ALARM1

COMP1

MASK1

MODE0 - EVCTRL

MODE1 - EVCTRL

MODE2 - EVCTRL

EVCTRL

MODE0 - COMP0

MODE1 - COMP0

MODE2 - ALARM0

GP0

GP1

MODE2 - MASK0

GP2

GP3

MODE1 - COMP1

MODE0 - INTENCLR

MODE1 - INTENCLR

MODE2 - INTENCLR

INTENCLR

MODE0 - GP0

MODE1 - GP0

MODE2 - GP0

MODE0 - INTENSET

MODE1 - INTENSET

MODE2 - INTENSET

INTENSET

MODE0 - INTFLAG

MODE1 - INTFLAG

MODE2 - INTFLAG

INTFLAG

MODE0 - GP1

MODE1 - GP1

MODE2 - GP1

MODE0 - DBGCTRL

MODE1 - DBGCTRL

MODE2 - DBGCTRL

DBGCTRL


MODE0 - CTRLA

32-bit Counter with Single 32-bit Compare - - MODE0 Control A
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 - CTRLA MODE0 - CTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE MODE MATCHCLR PRESCALER COUNTSYNC

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only

ENABLE : Enable
bits : 1 - 1 (1 bit)

MODE : Operating Mode
bits : 2 - 3 (2 bit)

Enumeration: MODESelect

0x0 : COUNT32

Mode 0: 32-bit Counter

0x1 : COUNT16

Mode 1: 16-bit Counter

0x2 : CLOCK

Mode 2: Clock/Calendar

End of enumeration elements list.

MATCHCLR : Clear on Match
bits : 7 - 7 (1 bit)

PRESCALER : Prescaler
bits : 8 - 11 (4 bit)

Enumeration: PRESCALERSelect

0x0 : OFF

CLK_RTC_CNT = GCLK_RTC/1

0x1 : DIV1

CLK_RTC_CNT = GCLK_RTC/1

0x2 : DIV2

CLK_RTC_CNT = GCLK_RTC/2

0x3 : DIV4

CLK_RTC_CNT = GCLK_RTC/4

0x4 : DIV8

CLK_RTC_CNT = GCLK_RTC/8

0x5 : DIV16

CLK_RTC_CNT = GCLK_RTC/16

0x6 : DIV32

CLK_RTC_CNT = GCLK_RTC/32

0x7 : DIV64

CLK_RTC_CNT = GCLK_RTC/64

0x8 : DIV128

CLK_RTC_CNT = GCLK_RTC/128

0x9 : DIV256

CLK_RTC_CNT = GCLK_RTC/256

0xa : DIV512

CLK_RTC_CNT = GCLK_RTC/512

0xb : DIV1024

CLK_RTC_CNT = GCLK_RTC/1024

End of enumeration elements list.

COUNTSYNC : Count Read Synchronization Enable
bits : 15 - 15 (1 bit)


MODE1 - CTRLA

16-bit Counter with Two 16-bit Compares - - MODE1 Control A
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - CTRLA MODE1 - CTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE MODE PRESCALER COUNTSYNC

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only

ENABLE : Enable
bits : 1 - 1 (1 bit)

MODE : Operating Mode
bits : 2 - 3 (2 bit)

Enumeration: MODESelect

0x0 : COUNT32

Mode 0: 32-bit Counter

0x1 : COUNT16

Mode 1: 16-bit Counter

0x2 : CLOCK

Mode 2: Clock/Calendar

End of enumeration elements list.

PRESCALER : Prescaler
bits : 8 - 11 (4 bit)

Enumeration: PRESCALERSelect

0x0 : OFF

CLK_RTC_CNT = GCLK_RTC/1

0x1 : DIV1

CLK_RTC_CNT = GCLK_RTC/1

0x2 : DIV2

CLK_RTC_CNT = GCLK_RTC/2

0x3 : DIV4

CLK_RTC_CNT = GCLK_RTC/4

0x4 : DIV8

CLK_RTC_CNT = GCLK_RTC/8

0x5 : DIV16

CLK_RTC_CNT = GCLK_RTC/16

0x6 : DIV32

CLK_RTC_CNT = GCLK_RTC/32

0x7 : DIV64

CLK_RTC_CNT = GCLK_RTC/64

0x8 : DIV128

CLK_RTC_CNT = GCLK_RTC/128

0x9 : DIV256

CLK_RTC_CNT = GCLK_RTC/256

0xa : DIV512

CLK_RTC_CNT = GCLK_RTC/512

0xb : DIV1024

CLK_RTC_CNT = GCLK_RTC/1024

End of enumeration elements list.

COUNTSYNC : Count Read Synchronization Enable
bits : 15 - 15 (1 bit)


MODE2 - CTRLA

Clock/Calendar with Alarm - - MODE2 Control A
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 - CTRLA MODE2 - CTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE MODE CLKREP MATCHCLR PRESCALER CLOCKSYNC

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only

ENABLE : Enable
bits : 1 - 1 (1 bit)

MODE : Operating Mode
bits : 2 - 3 (2 bit)

Enumeration: MODESelect

0x0 : COUNT32

Mode 0: 32-bit Counter

0x1 : COUNT16

Mode 1: 16-bit Counter

0x2 : CLOCK

Mode 2: Clock/Calendar

End of enumeration elements list.

CLKREP : Clock Representation
bits : 6 - 6 (1 bit)

MATCHCLR : Clear on Match
bits : 7 - 7 (1 bit)

PRESCALER : Prescaler
bits : 8 - 11 (4 bit)

Enumeration: PRESCALERSelect

0x0 : OFF

CLK_RTC_CNT = GCLK_RTC/1

0x1 : DIV1

CLK_RTC_CNT = GCLK_RTC/1

0x2 : DIV2

CLK_RTC_CNT = GCLK_RTC/2

0x3 : DIV4

CLK_RTC_CNT = GCLK_RTC/4

0x4 : DIV8

CLK_RTC_CNT = GCLK_RTC/8

0x5 : DIV16

CLK_RTC_CNT = GCLK_RTC/16

0x6 : DIV32

CLK_RTC_CNT = GCLK_RTC/32

0x7 : DIV64

CLK_RTC_CNT = GCLK_RTC/64

0x8 : DIV128

CLK_RTC_CNT = GCLK_RTC/128

0x9 : DIV256

CLK_RTC_CNT = GCLK_RTC/256

0xa : DIV512

CLK_RTC_CNT = GCLK_RTC/512

0xb : DIV1024

CLK_RTC_CNT = GCLK_RTC/1024

End of enumeration elements list.

CLOCKSYNC : Clock Read Synchronization Enable
bits : 15 - 15 (1 bit)


CTRLA

MODE2 Control A
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE MODE CLKREP MATCHCLR PRESCALER COUNTSYNC CLOCKSYNC

SWRST : Software Reset
bits : 0 - 0 (1 bit)
access : write-only

ENABLE : Enable
bits : 1 - 1 (1 bit)

MODE : Operating Mode
bits : 2 - 3 (2 bit)

Enumeration: MODESelect

0x0 : COUNT32

Mode 0: 32-bit Counter

0x1 : COUNT16

Mode 1: 16-bit Counter

0x2 : CLOCK

Mode 2: Clock/Calendar

End of enumeration elements list.

CLKREP : Clock Representation
bits : 6 - 6 (1 bit)

MATCHCLR : Clear on Match
bits : 7 - 7 (1 bit)

PRESCALER : Prescaler
bits : 8 - 11 (4 bit)

Enumeration: PRESCALERSelect

0x0 : OFF

CLK_RTC_CNT = GCLK_RTC/1

0x1 : DIV1

CLK_RTC_CNT = GCLK_RTC/1

0x2 : DIV2

CLK_RTC_CNT = GCLK_RTC/2

0x3 : DIV4

CLK_RTC_CNT = GCLK_RTC/4

0x4 : DIV8

CLK_RTC_CNT = GCLK_RTC/8

0x5 : DIV16

CLK_RTC_CNT = GCLK_RTC/16

0x6 : DIV32

CLK_RTC_CNT = GCLK_RTC/32

0x7 : DIV64

CLK_RTC_CNT = GCLK_RTC/64

0x8 : DIV128

CLK_RTC_CNT = GCLK_RTC/128

0x9 : DIV256

CLK_RTC_CNT = GCLK_RTC/256

0xa : DIV512

CLK_RTC_CNT = GCLK_RTC/512

0xb : DIV1024

CLK_RTC_CNT = GCLK_RTC/1024

End of enumeration elements list.

COUNTSYNC : Count Read Synchronization Enable
bits : 15 - 15 (1 bit)

CLOCKSYNC : Clock Read Synchronization Enable
bits : 15 - 15 (1 bit)


MODE0 - SYNCBUSY

32-bit Counter with Single 32-bit Compare - - MODE0 Synchronization Busy Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MODE0 - SYNCBUSY MODE0 - SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE FREQCORR COUNT COMP0 COUNTSYNC

SWRST : Software Reset Busy
bits : 0 - 0 (1 bit)
access : read-only

ENABLE : Enable Bit Busy
bits : 1 - 1 (1 bit)
access : read-only

FREQCORR : FREQCORR Register Busy
bits : 2 - 2 (1 bit)
access : read-only

COUNT : COUNT Register Busy
bits : 3 - 3 (1 bit)
access : read-only

COMP0 : COMP 0 Register Busy
bits : 5 - 5 (1 bit)
access : read-only

COUNTSYNC : Count Read Synchronization Enable Bit Busy
bits : 15 - 15 (1 bit)
access : read-only


MODE1 - SYNCBUSY

16-bit Counter with Two 16-bit Compares - - MODE1 Synchronization Busy Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MODE1 - SYNCBUSY MODE1 - SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE FREQCORR COUNT PER COMP0 COMP1 COUNTSYNC

SWRST : Software Reset Bit Busy
bits : 0 - 0 (1 bit)
access : read-only

ENABLE : Enable Bit Busy
bits : 1 - 1 (1 bit)
access : read-only

FREQCORR : FREQCORR Register Busy
bits : 2 - 2 (1 bit)
access : read-only

COUNT : COUNT Register Busy
bits : 3 - 3 (1 bit)
access : read-only

PER : PER Register Busy
bits : 4 - 4 (1 bit)
access : read-only

COMP0 : COMP 0 Register Busy
bits : 5 - 5 (1 bit)
access : read-only

COMP1 : COMP 1 Register Busy
bits : 6 - 6 (1 bit)
access : read-only

COUNTSYNC : Count Read Synchronization Enable Bit Busy
bits : 15 - 15 (1 bit)
access : read-only


MODE2 - SYNCBUSY

Clock/Calendar with Alarm - - MODE2 Synchronization Busy Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MODE2 - SYNCBUSY MODE2 - SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE FREQCORR CLOCK ALARM0 MASK0 CLOCKSYNC

SWRST : Software Reset Bit Busy
bits : 0 - 0 (1 bit)
access : read-only

ENABLE : Enable Bit Busy
bits : 1 - 1 (1 bit)
access : read-only

FREQCORR : FREQCORR Register Busy
bits : 2 - 2 (1 bit)
access : read-only

CLOCK : CLOCK Register Busy
bits : 3 - 3 (1 bit)
access : read-only

ALARM0 : ALARM 0 Register Busy
bits : 5 - 5 (1 bit)
access : read-only

MASK0 : MASK 0 Register Busy
bits : 11 - 11 (1 bit)
access : read-only

CLOCKSYNC : Clock Read Synchronization Enable Bit Busy
bits : 15 - 15 (1 bit)
access : read-only


SYNCBUSY

MODE2 Synchronization Busy Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE FREQCORR COUNT CLOCK PER COMP0 ALARM0 COMP1 MASK0 COUNTSYNC CLOCKSYNC

SWRST : Software Reset Bit Busy
bits : 0 - 0 (1 bit)
access : read-only

ENABLE : Enable Bit Busy
bits : 1 - 1 (1 bit)
access : read-only

FREQCORR : FREQCORR Register Busy
bits : 2 - 2 (1 bit)
access : read-only

COUNT : COUNT Register Busy
bits : 3 - 3 (1 bit)
access : read-only

CLOCK : CLOCK Register Busy
bits : 3 - 3 (1 bit)
access : read-only

PER : PER Register Busy
bits : 4 - 4 (1 bit)
access : read-only

COMP0 : COMP 0 Register Busy
bits : 5 - 5 (1 bit)
access : read-only

ALARM0 : ALARM 0 Register Busy
bits : 5 - 5 (1 bit)
access : read-only

COMP1 : COMP 1 Register Busy
bits : 6 - 6 (1 bit)
access : read-only

MASK0 : MASK 0 Register Busy
bits : 11 - 11 (1 bit)
access : read-only

COUNTSYNC : Count Read Synchronization Enable Bit Busy
bits : 15 - 15 (1 bit)
access : read-only

CLOCKSYNC : Clock Read Synchronization Enable Bit Busy
bits : 15 - 15 (1 bit)
access : read-only


MODE0 - GP2

32-bit Counter with Single 32-bit Compare - - General Purpose
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 - GP2 MODE0 - GP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE1 - GP2

16-bit Counter with Two 16-bit Compares - - General Purpose
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - GP2 MODE1 - GP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE2 - GP2

Clock/Calendar with Alarm - - General Purpose
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 - GP2 MODE2 - GP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE0 - FREQCORR

32-bit Counter with Single 32-bit Compare - - Frequency Correction
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 - FREQCORR MODE0 - FREQCORR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VALUE SIGN

VALUE : Correction Value
bits : 0 - 6 (7 bit)

SIGN : Correction Sign
bits : 7 - 7 (1 bit)


MODE1 - FREQCORR

16-bit Counter with Two 16-bit Compares - - Frequency Correction
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - FREQCORR MODE1 - FREQCORR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VALUE SIGN

VALUE : Correction Value
bits : 0 - 6 (7 bit)

SIGN : Correction Sign
bits : 7 - 7 (1 bit)


MODE2 - FREQCORR

Clock/Calendar with Alarm - - Frequency Correction
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 - FREQCORR MODE2 - FREQCORR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VALUE SIGN

VALUE : Correction Value
bits : 0 - 6 (7 bit)

SIGN : Correction Sign
bits : 7 - 7 (1 bit)


FREQCORR

Frequency Correction
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FREQCORR FREQCORR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VALUE SIGN

VALUE : Correction Value
bits : 0 - 6 (7 bit)

SIGN : Correction Sign
bits : 7 - 7 (1 bit)


MODE0 - GP3

32-bit Counter with Single 32-bit Compare - - General Purpose
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 - GP3 MODE0 - GP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE1 - GP3

16-bit Counter with Two 16-bit Compares - - General Purpose
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - GP3 MODE1 - GP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE2 - GP3

Clock/Calendar with Alarm - - General Purpose
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 - GP3 MODE2 - GP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE0 - COUNT

32-bit Counter with Single 32-bit Compare - - MODE0 Counter Value
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 - COUNT MODE0 - COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 0 - 31 (32 bit)


MODE1 - COUNT

16-bit Counter with Two 16-bit Compares - - MODE1 Counter Value
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - COUNT MODE1 - COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 0 - 15 (16 bit)


MODE2 - CLOCK

Clock/Calendar with Alarm - - MODE2 Clock Value
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 - CLOCK MODE2 - CLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECOND MINUTE HOUR DAY MONTH YEAR

SECOND : Second
bits : 0 - 5 (6 bit)

MINUTE : Minute
bits : 6 - 11 (6 bit)

HOUR : Hour
bits : 12 - 16 (5 bit)

DAY : Day
bits : 17 - 21 (5 bit)

MONTH : Month
bits : 22 - 25 (4 bit)

YEAR : Year
bits : 26 - 31 (6 bit)


COUNT

MODE1 Counter Value
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNT COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Counter Value
bits : 0 - 15 (16 bit)


CLOCK

MODE2 Clock Value
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLOCK CLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECOND MINUTE HOUR DAY MONTH YEAR

SECOND : Second
bits : 0 - 5 (6 bit)

MINUTE : Minute
bits : 6 - 11 (6 bit)

HOUR : Hour
bits : 12 - 16 (5 bit)

Enumeration: HOURSelect

0x0 : AM

AM when CLKREP in 12-hour

0x10 : PM

PM when CLKREP in 12-hour

End of enumeration elements list.

DAY : Day
bits : 17 - 21 (5 bit)

MONTH : Month
bits : 22 - 25 (4 bit)

YEAR : Year
bits : 26 - 31 (6 bit)


MODE1 - PER

16-bit Counter with Two 16-bit Compares - - MODE1 Counter Period
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - PER MODE1 - PER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER

PER : Counter Period
bits : 0 - 15 (16 bit)


PER

MODE1 Counter Period
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER PER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER

PER : Counter Period
bits : 0 - 15 (16 bit)


COMP0

MODE1 Compare n Value
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP0 COMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP

COMP : Compare Value
bits : 0 - 15 (16 bit)


ALARM1

MODE2 Alarm n Value
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALARM1 ALARM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECOND MINUTE HOUR DAY MONTH YEAR

SECOND : Second
bits : 0 - 5 (6 bit)

MINUTE : Minute
bits : 6 - 11 (6 bit)

HOUR : Hour
bits : 12 - 16 (5 bit)

Enumeration: HOURSelect

0x0 : AM

Morning hour

0x10 : PM

Afternoon hour

End of enumeration elements list.

DAY : Day
bits : 17 - 21 (5 bit)

MONTH : Month
bits : 22 - 25 (4 bit)

YEAR : Year
bits : 26 - 31 (6 bit)


COMP1

MODE1 Compare n Value
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP1 COMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP

COMP : Compare Value
bits : 0 - 15 (16 bit)


MASK1

MODE2 Alarm n Mask
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASK1 MASK1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEL

SEL : Alarm Mask Selection
bits : 0 - 2 (3 bit)

Enumeration: SELSelect

0x0 : OFF

Alarm Disabled

0x1 : SS

Match seconds only

0x2 : MMSS

Match seconds and minutes only

0x3 : HHMMSS

Match seconds, minutes, and hours only

0x4 : DDHHMMSS

Match seconds, minutes, hours, and days only

0x5 : MMDDHHMMSS

Match seconds, minutes, hours, days, and months only

0x6 : YYMMDDHHMMSS

Match seconds, minutes, hours, days, months, and years

End of enumeration elements list.


MODE0 - EVCTRL

32-bit Counter with Single 32-bit Compare - - MODE0 Event Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 - EVCTRL MODE0 - EVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEREO0 PEREO1 PEREO2 PEREO3 PEREO4 PEREO5 PEREO6 PEREO7 CMPEO0 OVFEO

PEREO0 : Periodic Interval 0 Event Output Enable
bits : 0 - 0 (1 bit)

PEREO1 : Periodic Interval 1 Event Output Enable
bits : 1 - 1 (1 bit)

PEREO2 : Periodic Interval 2 Event Output Enable
bits : 2 - 2 (1 bit)

PEREO3 : Periodic Interval 3 Event Output Enable
bits : 3 - 3 (1 bit)

PEREO4 : Periodic Interval 4 Event Output Enable
bits : 4 - 4 (1 bit)

PEREO5 : Periodic Interval 5 Event Output Enable
bits : 5 - 5 (1 bit)

PEREO6 : Periodic Interval 6 Event Output Enable
bits : 6 - 6 (1 bit)

PEREO7 : Periodic Interval 7 Event Output Enable
bits : 7 - 7 (1 bit)

CMPEO0 : Compare 0 Event Output Enable
bits : 8 - 8 (1 bit)

OVFEO : Overflow Event Output Enable
bits : 15 - 15 (1 bit)


MODE1 - EVCTRL

16-bit Counter with Two 16-bit Compares - - MODE1 Event Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - EVCTRL MODE1 - EVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEREO0 PEREO1 PEREO2 PEREO3 PEREO4 PEREO5 PEREO6 PEREO7 CMPEO0 CMPEO1 OVFEO

PEREO0 : Periodic Interval 0 Event Output Enable
bits : 0 - 0 (1 bit)

PEREO1 : Periodic Interval 1 Event Output Enable
bits : 1 - 1 (1 bit)

PEREO2 : Periodic Interval 2 Event Output Enable
bits : 2 - 2 (1 bit)

PEREO3 : Periodic Interval 3 Event Output Enable
bits : 3 - 3 (1 bit)

PEREO4 : Periodic Interval 4 Event Output Enable
bits : 4 - 4 (1 bit)

PEREO5 : Periodic Interval 5 Event Output Enable
bits : 5 - 5 (1 bit)

PEREO6 : Periodic Interval 6 Event Output Enable
bits : 6 - 6 (1 bit)

PEREO7 : Periodic Interval 7 Event Output Enable
bits : 7 - 7 (1 bit)

CMPEO0 : Compare 0 Event Output Enable
bits : 8 - 8 (1 bit)

CMPEO1 : Compare 1 Event Output Enable
bits : 9 - 9 (1 bit)

OVFEO : Overflow Event Output Enable
bits : 15 - 15 (1 bit)


MODE2 - EVCTRL

Clock/Calendar with Alarm - - MODE2 Event Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 - EVCTRL MODE2 - EVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEREO0 PEREO1 PEREO2 PEREO3 PEREO4 PEREO5 PEREO6 PEREO7 ALARMEO0 OVFEO

PEREO0 : Periodic Interval 0 Event Output Enable
bits : 0 - 0 (1 bit)

PEREO1 : Periodic Interval 1 Event Output Enable
bits : 1 - 1 (1 bit)

PEREO2 : Periodic Interval 2 Event Output Enable
bits : 2 - 2 (1 bit)

PEREO3 : Periodic Interval 3 Event Output Enable
bits : 3 - 3 (1 bit)

PEREO4 : Periodic Interval 4 Event Output Enable
bits : 4 - 4 (1 bit)

PEREO5 : Periodic Interval 5 Event Output Enable
bits : 5 - 5 (1 bit)

PEREO6 : Periodic Interval 6 Event Output Enable
bits : 6 - 6 (1 bit)

PEREO7 : Periodic Interval 7 Event Output Enable
bits : 7 - 7 (1 bit)

ALARMEO0 : Alarm 0 Event Output Enable
bits : 8 - 8 (1 bit)

OVFEO : Overflow Event Output Enable
bits : 15 - 15 (1 bit)


EVCTRL

MODE2 Event Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCTRL EVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEREO0 PEREO1 PEREO2 PEREO3 PEREO4 PEREO5 PEREO6 PEREO7 CMPEO0 ALARMEO0 CMPEO1 OVFEO

PEREO0 : Periodic Interval 0 Event Output Enable
bits : 0 - 0 (1 bit)

PEREO1 : Periodic Interval 1 Event Output Enable
bits : 1 - 1 (1 bit)

PEREO2 : Periodic Interval 2 Event Output Enable
bits : 2 - 2 (1 bit)

PEREO3 : Periodic Interval 3 Event Output Enable
bits : 3 - 3 (1 bit)

PEREO4 : Periodic Interval 4 Event Output Enable
bits : 4 - 4 (1 bit)

PEREO5 : Periodic Interval 5 Event Output Enable
bits : 5 - 5 (1 bit)

PEREO6 : Periodic Interval 6 Event Output Enable
bits : 6 - 6 (1 bit)

PEREO7 : Periodic Interval 7 Event Output Enable
bits : 7 - 7 (1 bit)

CMPEO0 : Compare 0 Event Output Enable
bits : 8 - 8 (1 bit)

ALARMEO0 : Alarm 0 Event Output Enable
bits : 8 - 8 (1 bit)

CMPEO1 : Compare 1 Event Output Enable
bits : 9 - 9 (1 bit)

OVFEO : Overflow Event Output Enable
bits : 15 - 15 (1 bit)


MODE0 - COMP0

32-bit Counter with Single 32-bit Compare - - MODE0 Compare n Value
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 - COMP0 MODE0 - COMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP

COMP : Compare Value
bits : 0 - 31 (32 bit)


MODE1 - COMP0

16-bit Counter with Two 16-bit Compares - - MODE1 Compare n Value
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - COMP0 MODE1 - COMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP

COMP : Compare Value
bits : 0 - 15 (16 bit)


MODE2 - ALARM0

Clock/Calendar with Alarm - - MODE2 Alarm n Value
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 - ALARM0 MODE2 - ALARM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECOND MINUTE HOUR DAY MONTH YEAR

SECOND : Second
bits : 0 - 5 (6 bit)

MINUTE : Minute
bits : 6 - 11 (6 bit)

HOUR : Hour
bits : 12 - 16 (5 bit)

DAY : Day
bits : 17 - 21 (5 bit)

MONTH : Month
bits : 22 - 25 (4 bit)

YEAR : Year
bits : 26 - 31 (6 bit)


GP0

General Purpose
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP0 GP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GP1

General Purpose
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP1 GP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE2 - MASK0

Clock/Calendar with Alarm - - MODE2 Alarm n Mask
address_offset : 0x48 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 - MASK0 MODE2 - MASK0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SEL

SEL : Alarm Mask Selection
bits : 0 - 2 (3 bit)

Enumeration: SELSelect

0x0 : OFF

Alarm Disabled

0x1 : SS

Match seconds only

0x2 : MMSS

Match seconds and minutes only

0x3 : HHMMSS

Match seconds, minutes, and hours only

0x4 : DDHHMMSS

Match seconds, minutes, hours, and days only

0x5 : MMDDHHMMSS

Match seconds, minutes, hours, days, and months only

0x6 : YYMMDDHHMMSS

Match seconds, minutes, hours, days, months, and years

End of enumeration elements list.


GP2

General Purpose
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP2 GP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GP3

General Purpose
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP3 GP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE1 - COMP1

16-bit Counter with Two 16-bit Compares - - MODE1 Compare n Value
address_offset : 0x62 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - COMP1 MODE1 - COMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP

COMP : Compare Value
bits : 0 - 15 (16 bit)


MODE0 - INTENCLR

32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 - INTENCLR MODE0 - INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 CMP0 OVF

PER0 : Periodic Interval 0 Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

PER1 : Periodic Interval 1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

PER2 : Periodic Interval 2 Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

PER3 : Periodic Interval 3 Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

PER4 : Periodic Interval 4 Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

PER5 : Periodic Interval 5 Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

PER6 : Periodic Interval 6 Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

PER7 : Periodic Interval 7 Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

CMP0 : Compare 0 Interrupt Enable
bits : 8 - 8 (1 bit)

OVF : Overflow Interrupt Enable
bits : 15 - 15 (1 bit)


MODE1 - INTENCLR

16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - INTENCLR MODE1 - INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 CMP0 CMP1 OVF

PER0 : Periodic Interval 0 Interrupt Enable
bits : 0 - 0 (1 bit)

PER1 : Periodic Interval 1 Interrupt Enable
bits : 1 - 1 (1 bit)

PER2 : Periodic Interval 2 Interrupt Enable
bits : 2 - 2 (1 bit)

PER3 : Periodic Interval 3 Interrupt Enable
bits : 3 - 3 (1 bit)

PER4 : Periodic Interval 4 Interrupt Enable
bits : 4 - 4 (1 bit)

PER5 : Periodic Interval 5 Interrupt Enable
bits : 5 - 5 (1 bit)

PER6 : Periodic Interval 6 Interrupt Enable
bits : 6 - 6 (1 bit)

PER7 : Periodic Interval 7 Interrupt Enable
bits : 7 - 7 (1 bit)

CMP0 : Compare 0 Interrupt Enable
bits : 8 - 8 (1 bit)

CMP1 : Compare 1 Interrupt Enable
bits : 9 - 9 (1 bit)

OVF : Overflow Interrupt Enable
bits : 15 - 15 (1 bit)


MODE2 - INTENCLR

Clock/Calendar with Alarm - - MODE2 Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 - INTENCLR MODE2 - INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 ALARM0 OVF

PER0 : Periodic Interval 0 Interrupt Enable
bits : 0 - 0 (1 bit)

PER1 : Periodic Interval 1 Interrupt Enable
bits : 1 - 1 (1 bit)

PER2 : Periodic Interval 2 Interrupt Enable
bits : 2 - 2 (1 bit)

PER3 : Periodic Interval 3 Interrupt Enable
bits : 3 - 3 (1 bit)

PER4 : Periodic Interval 4 Interrupt Enable
bits : 4 - 4 (1 bit)

PER5 : Periodic Interval 5 Interrupt Enable
bits : 5 - 5 (1 bit)

PER6 : Periodic Interval 6 Interrupt Enable
bits : 6 - 6 (1 bit)

PER7 : Periodic Interval 7 Interrupt Enable
bits : 7 - 7 (1 bit)

ALARM0 : Alarm 0 Interrupt Enable
bits : 8 - 8 (1 bit)

OVF : Overflow Interrupt Enable
bits : 15 - 15 (1 bit)


INTENCLR

MODE2 Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 CMP0 ALARM0 CMP1 OVF

PER0 : Periodic Interval 0 Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

PER1 : Periodic Interval 1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

PER2 : Periodic Interval 2 Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

PER3 : Periodic Interval 3 Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

PER4 : Periodic Interval 4 Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

PER5 : Periodic Interval 5 Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

PER6 : Periodic Interval 6 Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

PER7 : Periodic Interval 7 Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

CMP0 : Compare 0 Interrupt Enable
bits : 8 - 8 (1 bit)

ALARM0 : Alarm 0 Interrupt Enable
bits : 8 - 8 (1 bit)

CMP1 : Compare 1 Interrupt Enable
bits : 9 - 9 (1 bit)

OVF : Overflow Interrupt Enable
bits : 15 - 15 (1 bit)


MODE0 - GP0

32-bit Counter with Single 32-bit Compare - - General Purpose
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 - GP0 MODE0 - GP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE1 - GP0

16-bit Counter with Two 16-bit Compares - - General Purpose
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - GP0 MODE1 - GP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE2 - GP0

Clock/Calendar with Alarm - - General Purpose
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 - GP0 MODE2 - GP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE0 - INTENSET

32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Enable Set
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 - INTENSET MODE0 - INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 CMP0 OVF

PER0 : Periodic Interval 0 Interrupt Enable
bits : 0 - 0 (1 bit)

PER1 : Periodic Interval 1 Interrupt Enable
bits : 1 - 1 (1 bit)

PER2 : Periodic Interval 2 Interrupt Enable
bits : 2 - 2 (1 bit)

PER3 : Periodic Interval 3 Interrupt Enable
bits : 3 - 3 (1 bit)

PER4 : Periodic Interval 4 Interrupt Enable
bits : 4 - 4 (1 bit)

PER5 : Periodic Interval 5 Interrupt Enable
bits : 5 - 5 (1 bit)

PER6 : Periodic Interval 6 Interrupt Enable
bits : 6 - 6 (1 bit)

PER7 : Periodic Interval 7 Interrupt Enable
bits : 7 - 7 (1 bit)

CMP0 : Compare 0 Interrupt Enable
bits : 8 - 8 (1 bit)

OVF : Overflow Interrupt Enable
bits : 15 - 15 (1 bit)


MODE1 - INTENSET

16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Enable Set
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - INTENSET MODE1 - INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 CMP0 CMP1 OVF

PER0 : Periodic Interval 0 Interrupt Enable
bits : 0 - 0 (1 bit)

PER1 : Periodic Interval 1 Interrupt Enable
bits : 1 - 1 (1 bit)

PER2 : Periodic Interval 2 Interrupt Enable
bits : 2 - 2 (1 bit)

PER3 : Periodic Interval 3 Interrupt Enable
bits : 3 - 3 (1 bit)

PER4 : Periodic Interval 4 Interrupt Enable
bits : 4 - 4 (1 bit)

PER5 : Periodic Interval 5 Interrupt Enable
bits : 5 - 5 (1 bit)

PER6 : Periodic Interval 6 Interrupt Enable
bits : 6 - 6 (1 bit)

PER7 : Periodic Interval 7 Interrupt Enable
bits : 7 - 7 (1 bit)

CMP0 : Compare 0 Interrupt Enable
bits : 8 - 8 (1 bit)

CMP1 : Compare 1 Interrupt Enable
bits : 9 - 9 (1 bit)

OVF : Overflow Interrupt Enable
bits : 15 - 15 (1 bit)


MODE2 - INTENSET

Clock/Calendar with Alarm - - MODE2 Interrupt Enable Set
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 - INTENSET MODE2 - INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 ALARM0 OVF

PER0 : Periodic Interval 0 Enable
bits : 0 - 0 (1 bit)

PER1 : Periodic Interval 1 Enable
bits : 1 - 1 (1 bit)

PER2 : Periodic Interval 2 Enable
bits : 2 - 2 (1 bit)

PER3 : Periodic Interval 3 Enable
bits : 3 - 3 (1 bit)

PER4 : Periodic Interval 4 Enable
bits : 4 - 4 (1 bit)

PER5 : Periodic Interval 5 Enable
bits : 5 - 5 (1 bit)

PER6 : Periodic Interval 6 Enable
bits : 6 - 6 (1 bit)

PER7 : Periodic Interval 7 Enable
bits : 7 - 7 (1 bit)

ALARM0 : Alarm 0 Interrupt Enable
bits : 8 - 8 (1 bit)

OVF : Overflow Interrupt Enable
bits : 15 - 15 (1 bit)


INTENSET

MODE2 Interrupt Enable Set
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 CMP0 ALARM0 CMP1 OVF

PER0 : Periodic Interval 0 Enable
bits : 0 - 0 (1 bit)

PER1 : Periodic Interval 1 Enable
bits : 1 - 1 (1 bit)

PER2 : Periodic Interval 2 Enable
bits : 2 - 2 (1 bit)

PER3 : Periodic Interval 3 Enable
bits : 3 - 3 (1 bit)

PER4 : Periodic Interval 4 Enable
bits : 4 - 4 (1 bit)

PER5 : Periodic Interval 5 Enable
bits : 5 - 5 (1 bit)

PER6 : Periodic Interval 6 Enable
bits : 6 - 6 (1 bit)

PER7 : Periodic Interval 7 Enable
bits : 7 - 7 (1 bit)

CMP0 : Compare 0 Interrupt Enable
bits : 8 - 8 (1 bit)

ALARM0 : Alarm 0 Interrupt Enable
bits : 8 - 8 (1 bit)

CMP1 : Compare 1 Interrupt Enable
bits : 9 - 9 (1 bit)

OVF : Overflow Interrupt Enable
bits : 15 - 15 (1 bit)


MODE0 - INTFLAG

32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Flag Status and Clear
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 - INTFLAG MODE0 - INTFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 CMP0 OVF

PER0 : Periodic Interval 0
bits : 0 - 0 (1 bit)

PER1 : Periodic Interval 1
bits : 1 - 1 (1 bit)

PER2 : Periodic Interval 2
bits : 2 - 2 (1 bit)

PER3 : Periodic Interval 3
bits : 3 - 3 (1 bit)

PER4 : Periodic Interval 4
bits : 4 - 4 (1 bit)

PER5 : Periodic Interval 5
bits : 5 - 5 (1 bit)

PER6 : Periodic Interval 6
bits : 6 - 6 (1 bit)

PER7 : Periodic Interval 7
bits : 7 - 7 (1 bit)

CMP0 : Compare 0
bits : 8 - 8 (1 bit)

OVF : Overflow
bits : 15 - 15 (1 bit)


MODE1 - INTFLAG

16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Flag Status and Clear
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - INTFLAG MODE1 - INTFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 CMP0 CMP1 OVF

PER0 : Periodic Interval 0
bits : 0 - 0 (1 bit)

PER1 : Periodic Interval 1
bits : 1 - 1 (1 bit)

PER2 : Periodic Interval 2
bits : 2 - 2 (1 bit)

PER3 : Periodic Interval 3
bits : 3 - 3 (1 bit)

PER4 : Periodic Interval 4
bits : 4 - 4 (1 bit)

PER5 : Periodic Interval 5
bits : 5 - 5 (1 bit)

PER6 : Periodic Interval 6
bits : 6 - 6 (1 bit)

PER7 : Periodic Interval 7
bits : 7 - 7 (1 bit)

CMP0 : Compare 0
bits : 8 - 8 (1 bit)

CMP1 : Compare 1
bits : 9 - 9 (1 bit)

OVF : Overflow
bits : 15 - 15 (1 bit)


MODE2 - INTFLAG

Clock/Calendar with Alarm - - MODE2 Interrupt Flag Status and Clear
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 - INTFLAG MODE2 - INTFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 ALARM0 OVF

PER0 : Periodic Interval 0
bits : 0 - 0 (1 bit)

PER1 : Periodic Interval 1
bits : 1 - 1 (1 bit)

PER2 : Periodic Interval 2
bits : 2 - 2 (1 bit)

PER3 : Periodic Interval 3
bits : 3 - 3 (1 bit)

PER4 : Periodic Interval 4
bits : 4 - 4 (1 bit)

PER5 : Periodic Interval 5
bits : 5 - 5 (1 bit)

PER6 : Periodic Interval 6
bits : 6 - 6 (1 bit)

PER7 : Periodic Interval 7
bits : 7 - 7 (1 bit)

ALARM0 : Alarm 0
bits : 8 - 8 (1 bit)

OVF : Overflow
bits : 15 - 15 (1 bit)


INTFLAG

MODE2 Interrupt Flag Status and Clear
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 CMP0 ALARM0 CMP1 OVF

PER0 : Periodic Interval 0
bits : 0 - 0 (1 bit)

PER1 : Periodic Interval 1
bits : 1 - 1 (1 bit)

PER2 : Periodic Interval 2
bits : 2 - 2 (1 bit)

PER3 : Periodic Interval 3
bits : 3 - 3 (1 bit)

PER4 : Periodic Interval 4
bits : 4 - 4 (1 bit)

PER5 : Periodic Interval 5
bits : 5 - 5 (1 bit)

PER6 : Periodic Interval 6
bits : 6 - 6 (1 bit)

PER7 : Periodic Interval 7
bits : 7 - 7 (1 bit)

CMP0 : Compare 0
bits : 8 - 8 (1 bit)

ALARM0 : Alarm 0
bits : 8 - 8 (1 bit)

CMP1 : Compare 1
bits : 9 - 9 (1 bit)

OVF : Overflow
bits : 15 - 15 (1 bit)


MODE0 - GP1

32-bit Counter with Single 32-bit Compare - - General Purpose
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 - GP1 MODE0 - GP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE1 - GP1

16-bit Counter with Two 16-bit Compares - - General Purpose
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - GP1 MODE1 - GP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE2 - GP1

Clock/Calendar with Alarm - - General Purpose
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 - GP1 MODE2 - GP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MODE0 - DBGCTRL

32-bit Counter with Single 32-bit Compare - - Debug Control
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 - DBGCTRL MODE0 - DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Run During Debug
bits : 0 - 0 (1 bit)


MODE1 - DBGCTRL

16-bit Counter with Two 16-bit Compares - - Debug Control
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 - DBGCTRL MODE1 - DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Run During Debug
bits : 0 - 0 (1 bit)


MODE2 - DBGCTRL

Clock/Calendar with Alarm - - Debug Control
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 - DBGCTRL MODE2 - DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Run During Debug
bits : 0 - 0 (1 bit)


DBGCTRL

Debug Control
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCTRL DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Run During Debug
bits : 0 - 0 (1 bit)



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