\n
address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
Peripheral Clock Control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x10D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x11B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Generic Clock Generator Control
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Peripheral Clock Control
address_offset : 0x1294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x137C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x1468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Generic Clock Generator Control
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Peripheral Clock Control
address_offset : 0x1558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x164C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x1744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x1840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Generic Clock Generator Control
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Peripheral Clock Control
address_offset : 0x1940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x1A44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x1B4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x1C58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Generic Clock Generator Control
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Peripheral Clock Control
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Synchronization Busy
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Synchroniation Busy bit
bits : 0 - 0 (1 bit)
access : read-only
GENCTRL : Generic Clock Generator Control Synchronization Busy bits
bits : 2 - 10 (9 bit)
access : read-only
Enumeration: GENCTRLSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
Generic Clock Generator Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Peripheral Clock Control
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Generic Clock Generator Control
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Peripheral Clock Control
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Generic Clock Generator Control
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Peripheral Clock Control
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Generic Clock Generator Control
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Peripheral Clock Control
address_offset : 0xBE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xCAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xD78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xE48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Generic Clock Generator Control
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Peripheral Clock Control
address_offset : 0xF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
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