\n
address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 0x2E byte (0x0)
mem_usage : registers
protection :
Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
SLAVEEN : Slave Enable
bits : 5 - 5 (1 bit)
RUNSTDBY : Run During Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
Control B
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESCALER : Prescaler Configuration
bits : 0 - 2 (3 bit)
Enumeration: PRESCALERSelect
0x0 : DIV2
Peripheral clock divided by 2
0x1 : DIV4
Peripheral clock divided by 4
0x2 : DIV8
Peripheral clock divided by 8
0x3 : DIV16
Peripheral clock divided by 16
0x4 : DIV32
Peripheral clock divided by 32
0x5 : DIV64
Peripheral clock divided by 64
0x6 : DIV128
Peripheral clock divided by 128
0x7 : DIV256
Peripheral clock divided by 256
End of enumeration elements list.
Window Monitor Upper Threshold
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WINUT : Window Upper Threshold
bits : 0 - 15 (16 bit)
Gain Correction
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAINCORR : Gain Correction Value
bits : 0 - 11 (12 bit)
Offset Correction
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSETCORR : Offset Correction Value
bits : 0 - 11 (12 bit)
Software Trigger
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLUSH : ADC Flush
bits : 0 - 0 (1 bit)
START : Start ADC Conversion
bits : 1 - 1 (1 bit)
Debug Control
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGRUN : Debug Run
bits : 0 - 0 (1 bit)
Reference Control
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFSEL : Reference Selection
bits : 0 - 3 (4 bit)
Enumeration: REFSELSelect
0x0 : INTREF
Internal Bandgap Reference
0x1 : INTVCC0
1/1.6 VDDANA
0x2 : INTVCC1
1/2 VDDANA
0x3 : AREFA
External Reference
0x4 : AREFB
External Reference
0x5 : INTVCC2
VCCANA
End of enumeration elements list.
REFCOMP : Reference Buffer Offset Compensation Enable
bits : 7 - 7 (1 bit)
Synchronization Busy
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : SWRST Synchronization Busy
bits : 0 - 0 (1 bit)
access : read-only
ENABLE : ENABLE Synchronization Busy
bits : 1 - 1 (1 bit)
access : read-only
INPUTCTRL : INPUTCTRL Synchronization Busy
bits : 2 - 2 (1 bit)
access : read-only
CTRLC : CTRLC Synchronization Busy
bits : 3 - 3 (1 bit)
access : read-only
AVGCTRL : AVGCTRL Synchronization Busy
bits : 4 - 4 (1 bit)
access : read-only
SAMPCTRL : SAMPCTRL Synchronization Busy
bits : 5 - 5 (1 bit)
access : read-only
WINLT : WINLT Synchronization Busy
bits : 6 - 6 (1 bit)
access : read-only
WINUT : WINUT Synchronization Busy
bits : 7 - 7 (1 bit)
access : read-only
GAINCORR : GAINCORR Synchronization Busy
bits : 8 - 8 (1 bit)
access : read-only
OFFSETCORR : OFFSETCTRL Synchronization Busy
bits : 9 - 9 (1 bit)
access : read-only
SWTRIG : SWTRG Synchronization Busy
bits : 10 - 10 (1 bit)
access : read-only
Result
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : Result Value
bits : 0 - 15 (16 bit)
access : read-only
Sequence Control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQEN : Enable Positive Input in the Sequence
bits : 0 - 31 (32 bit)
Calibration
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIASCOMP : Bias Comparator Scaling
bits : 0 - 2 (3 bit)
BIASREFBUF : Bias Reference Buffer Scaling
bits : 8 - 10 (3 bit)
Event Control
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLUSHEI : Flush Event Input Enable
bits : 0 - 0 (1 bit)
STARTEI : Start Conversion Event Input Enable
bits : 1 - 1 (1 bit)
FLUSHINV : Flush Event Invert Enable
bits : 2 - 2 (1 bit)
STARTINV : Satrt Event Invert Enable
bits : 3 - 3 (1 bit)
RESRDYEO : Result Ready Event Out
bits : 4 - 4 (1 bit)
WINMONEO : Window Monitor Event Out
bits : 5 - 5 (1 bit)
Interrupt Enable Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESRDY : Result Ready Interrupt Disable
bits : 0 - 0 (1 bit)
OVERRUN : Overrun Interrupt Disable
bits : 1 - 1 (1 bit)
WINMON : Window Monitor Interrupt Disable
bits : 2 - 2 (1 bit)
Interrupt Enable Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESRDY : Result Ready Interrupt Enable
bits : 0 - 0 (1 bit)
OVERRUN : Overrun Interrupt Enable
bits : 1 - 1 (1 bit)
WINMON : Window Monitor Interrupt Enable
bits : 2 - 2 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESRDY : Result Ready Interrupt Flag
bits : 0 - 0 (1 bit)
OVERRUN : Overrun Interrupt Flag
bits : 1 - 1 (1 bit)
WINMON : Window Monitor Interrupt Flag
bits : 2 - 2 (1 bit)
Sequence Status
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEQSTATE : Sequence State
bits : 0 - 4 (5 bit)
access : read-only
SEQBUSY : Sequence Busy
bits : 7 - 7 (1 bit)
access : read-only
Input Control
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUXPOS : Positive Mux Input Selection
bits : 0 - 4 (5 bit)
Enumeration: MUXPOSSelect
0x0 : AIN0
ADC AIN0 Pin
0x1 : AIN1
ADC AIN1 Pin
0x2 : AIN2
ADC AIN2 Pin
0x3 : AIN3
ADC AIN3 Pin
0x4 : AIN4
ADC AIN4 Pin
0x5 : AIN5
ADC AIN5 Pin
0x6 : AIN6
ADC AIN6 Pin
0x7 : AIN7
ADC AIN7 Pin
0x8 : AIN8
ADC AIN8 Pin
0x9 : AIN9
ADC AIN9 Pin
0xa : AIN10
ADC AIN10 Pin
0xb : AIN11
ADC AIN11 Pin
0xc : AIN12
ADC AIN12 Pin
0xd : AIN13
ADC AIN13 Pin
0xe : AIN14
ADC AIN14 Pin
0xf : AIN15
ADC AIN15 Pin
0x10 : AIN16
ADC AIN16 Pin
0x11 : AIN17
ADC AIN17 Pin
0x12 : AIN18
ADC AIN18 Pin
0x13 : AIN19
ADC AIN19 Pin
0x18 : TEMP
Temperature Sensor
0x19 : BANDGAP
Bandgap Voltage
0x1a : SCALEDCOREVCC
1/4 Scaled Core Supply
0x1b : SCALEDIOVCC
1/4 Scaled I/O Supply
0x1d : SCALEDVBAT
1/4 Scaled VBAT Supply
0x1e : CTAT
CTAT output
End of enumeration elements list.
MUXNEG : Negative Mux Input Selection
bits : 8 - 12 (5 bit)
Enumeration: MUXNEGSelect
0x0 : AIN0
ADC AIN0 Pin
0x1 : AIN1
ADC AIN1 Pin
0x2 : AIN2
ADC AIN2 Pin
0x3 : AIN3
ADC AIN3 Pin
0x4 : AIN4
ADC AIN4 Pin
0x5 : AIN5
ADC AIN5 Pin
0x6 : AIN6
ADC AIN6 Pin
0x7 : AIN7
ADC AIN7 Pin
End of enumeration elements list.
Control C
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIFFMODE : Differential Mode
bits : 0 - 0 (1 bit)
LEFTADJ : Left-Adjusted Result
bits : 1 - 1 (1 bit)
FREERUN : Free Running Mode
bits : 2 - 2 (1 bit)
CORREN : Digital Correction Logic Enable
bits : 3 - 3 (1 bit)
RESSEL : Conversion Result Resolution
bits : 4 - 5 (2 bit)
Enumeration: RESSELSelect
0x0 : 12BIT
12-bit result
0x1 : 16BIT
For averaging mode output
0x2 : 10BIT
10-bit result
0x3 : 8BIT
8-bit result
End of enumeration elements list.
R2R : Rail-to-Rail mode enable
bits : 7 - 7 (1 bit)
WINMODE : Window Monitor Mode
bits : 8 - 10 (3 bit)
Enumeration: WINMODESelect
0x0 : DISABLE
No window mode (default)
0x1 : MODE1
RESULT > WINLT
0x2 : MODE2
RESULT < WINUT
0x3 : MODE3
WINLT < RESULT < WINUT
0x4 : MODE4
!(WINLT < RESULT < WINUT)
End of enumeration elements list.
DUALSEL : Dual Mode Trigger Selection
bits : 12 - 13 (2 bit)
Enumeration: DUALSELSelect
0x0 : BOTH
Start event or software trigger will start a conversion on both ADCs
0x1 : INTERLEAVE
START event or software trigger will alternatingly start a conversion on ADC0 and ADC1
End of enumeration elements list.
Average Control
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAMPLENUM : Number of Samples to be Collected
bits : 0 - 3 (4 bit)
Enumeration: SAMPLENUMSelect
0x0 : 1
1 sample
0x1 : 2
2 samples
0x2 : 4
4 samples
0x3 : 8
8 samples
0x4 : 16
16 samples
0x5 : 32
32 samples
0x6 : 64
64 samples
0x7 : 128
128 samples
0x8 : 256
256 samples
0x9 : 512
512 samples
0xa : 1024
1024 samples
End of enumeration elements list.
ADJRES : Adjusting Result / Division Coefficient
bits : 4 - 6 (3 bit)
Sample Time Control
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAMPLEN : Sampling Time Length
bits : 0 - 5 (6 bit)
OFFCOMP : Comparator Offset Compensation Enable
bits : 7 - 7 (1 bit)
Window Monitor Lower Threshold
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WINLT : Window Lower Threshold
bits : 0 - 15 (16 bit)
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