\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 0x86 byte (0x0)
mem_usage : registers
protection :
Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
DUTY : Duty Ratio
bits : 2 - 4 (3 bit)
Enumeration: DUTYSelect
0x0 : STATIC
Static duty
0x1 : HALF
1/2 duty
0x2 : THIRD
1/3 duty
0x3 : FOURTH
1/4 duty
0x4 : SIXTH
1/6 duty
0x5 : EIGHT
1/8 duty
End of enumeration elements list.
WMOD : Waveform Mode
bits : 5 - 5 (1 bit)
Enumeration: WMODSelect
0x0 : LP
Low Power Waveform Mode
0x1 : STD
Standard Waveform Mode
End of enumeration elements list.
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
PRESC : Clock Prescaler
bits : 8 - 9 (2 bit)
Enumeration: PRESCSelect
0x0 : PRESC16
16
0x1 : PRESC32
32
0x2 : PRESC64
64
0x3 : PRESC128
128
End of enumeration elements list.
CKDIV : Clock Divider
bits : 12 - 14 (3 bit)
BIAS : Bias Setting
bits : 16 - 17 (2 bit)
Enumeration: BIASSelect
0x0 : STATIC
Static
0x1 : HALF
1/2 bias
0x2 : THIRD
1/3 bias
0x3 : FOURTH
1/4 bias
End of enumeration elements list.
XVLCD : External VLCD
bits : 19 - 19 (1 bit)
PRF : Power Refresh Frequency
bits : 20 - 21 (2 bit)
Enumeration: PRFSelect
0x0 : PR2000
2kHz
0x1 : PR1000
1kHz
0x2 : PR500
500Hz
0x3 : PR250
250Hz
End of enumeration elements list.
DMFCS : Display Memory Update Frame Counter Selection
bits : 22 - 23 (2 bit)
Enumeration: DMFCSSelect
0x0 : FC0
Frame Counter 0
0x1 : FC1
Frame Counter 1
0x2 : FC2
Frame Counter 2
0x3 : NFC
Frame Counter event to DMU is forced to 0
End of enumeration elements list.
RRF : Reference Refresh Frequency
bits : 24 - 26 (3 bit)
Enumeration: RRFSelect
0x0 : RR2000
2kHz
0x1 : RR1000
1kHz
0x2 : RR500
500Hz
0x3 : RR250
250Hz
0x4 : RR125
125Hz
0x5 : RR62
62.5Hz
End of enumeration elements list.
Status
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VLCDR : VLCD Ready
bits : 0 - 0 (1 bit)
access : read-only
PRUN : LCD Charge Pump is Running
bits : 1 - 1 (1 bit)
access : read-only
VLCDS : VLCD Status
bits : 2 - 2 (1 bit)
access : read-only
CMWRBUSY : Character mapping write busy
bits : 3 - 3 (1 bit)
access : read-only
ACMBUSY : ACM state machine busy
bits : 4 - 4 (1 bit)
access : read-only
ABMBUSY : ABM state machine busy
bits : 5 - 5 (1 bit)
access : read-only
Synchronization Busy
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
CTRLD : Control D
bits : 2 - 2 (1 bit)
Frame Counter 0 Configuration
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Frame Counter Overflow Value
bits : 0 - 4 (5 bit)
PB : Prescaler Bypass
bits : 7 - 7 (1 bit)
Frame Counter 1 Configuration
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Frame Counter Overflow Value
bits : 0 - 4 (5 bit)
PB : Prescaler Bypass
bits : 7 - 7 (1 bit)
Frame Counter 2 Configuration
address_offset : 0x1A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : Frame Counter Overflow Value
bits : 0 - 4 (5 bit)
PB : Prescaler Bypass
bits : 7 - 7 (1 bit)
LCD Pin Enable Low
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPEN : LCD Pin Enable
bits : 0 - 31 (32 bit)
LCD Pin Enable High
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPEN : LCD Pin Enable
bits : 0 - 19 (20 bit)
Segments Data Low for COM0 Line
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 31 (32 bit)
Segments Data High for COM0 Line
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 11 (12 bit)
Segments Data Low for COM1 Line
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 31 (32 bit)
Segments Data High for COM1 Line
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 11 (12 bit)
Segments Data Low for COM2 Line
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 31 (32 bit)
Segments Data High for COM2 Line
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 11 (12 bit)
Segments Data Low for COM3 Line
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 31 (32 bit)
Control B
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBD : Bias Buffer Enable Duration
bits : 0 - 3 (4 bit)
EXTBIAS : External Bias Capacitor
bits : 6 - 6 (1 bit)
BBEN : Bias Buffer Enable
bits : 7 - 7 (1 bit)
LRD : Low Resistance Enable Duration
bits : 8 - 11 (4 bit)
LREN : Low Resistance Enable
bits : 15 - 15 (1 bit)
Segments Data High for COM3 Line
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 11 (12 bit)
Segments Data Low for COM4 Line
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 31 (32 bit)
Segments Data High for COM4 Line
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 9 (10 bit)
Segments Data Low for COM5 Line
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 31 (32 bit)
Segments Data High for COM5 Line
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 9 (10 bit)
Segments Data Low for COM6 Line
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 31 (32 bit)
Segments Data High for COM6 Line
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 7 (8 bit)
Segments Data Low for COM7 Line
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 31 (32 bit)
Control C
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLEAR : Clear Display Memory
bits : 0 - 0 (1 bit)
LOCK : Lock Shadow Memory
bits : 1 - 1 (1 bit)
ABMEN : Automated Bit Mapping Enable
bits : 2 - 2 (1 bit)
ACMEN : Automated Character Mapping Enable
bits : 3 - 3 (1 bit)
CTST : Contrast Adjustment
bits : 4 - 7 (4 bit)
LPPM : LCD Power Macro Power mode
bits : 8 - 9 (2 bit)
Enumeration: LPPMSelect
0x0 : AUTO
LCD power automatically select regualation mode or pump mode
0x1 : STEPUP
LCD power use step-up pump loop only
0x2 : STEPDOWN
LCD power use step-down drop-out regulation loop only
End of enumeration elements list.
Segments Data High for COM7 Line
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 7 (8 bit)
Indirect Segments Data Access
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 7 (8 bit)
SDMASK : Segments Data Mask
bits : 8 - 15 (8 bit)
OFF : Byte Offset
bits : 16 - 21 (6 bit)
Blink Configuration
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Blinking Mode
bits : 0 - 0 (1 bit)
Enumeration: MODESelect
0x0 : BLINKALL
Blink all segments
0x1 : BLINKSEL
Blink selected segments
End of enumeration elements list.
FCS : Frame Counter Selection
bits : 1 - 2 (2 bit)
Enumeration: FCSSelect
0x0 : FC0
Frame Counter 0
0x1 : FC1
Frame Counter 1
0x2 : FC2
Frame Counter 2
End of enumeration elements list.
BSS0 : Blink Segment Selection 0
bits : 8 - 15 (8 bit)
BSS1 : Blink Segment Selection 1
bits : 16 - 23 (8 bit)
Circular Shift Register Configuration
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Direction
bits : 0 - 0 (1 bit)
FCS : Frame Counter Selection
bits : 1 - 2 (2 bit)
Enumeration: FCSSelect
0x0 : FC0
Frame Counter 0
0x1 : FC1
Frame Counter 1
0x2 : FC2
Frame Counter 2
End of enumeration elements list.
SIZE : Circular Shift Register Size
bits : 4 - 7 (4 bit)
DATA : Circular Shift Register Value
bits : 8 - 23 (16 bit)
Character Mapping Configuration
address_offset : 0x70 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSEG : Number of SEG lines
bits : 0 - 2 (3 bit)
DEC : Decrement SEG Line Index
bits : 3 - 3 (1 bit)
Automated Character Mapping Configuration
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NCOM : COM Lines per Row
bits : 0 - 2 (3 bit)
NDIG : Number of Digit
bits : 4 - 7 (4 bit)
STEPS : Scrolling Steps
bits : 8 - 15 (8 bit)
NDROW : Number of Digit per Row
bits : 16 - 21 (6 bit)
MODE : Mode
bits : 23 - 23 (1 bit)
Enumeration: MODESelect
0x0 : SEQ
Sequential Display Mode
0x1 : SCROLL
Scrolling Display Mode
End of enumeration elements list.
STSEG : Start SEG Line
bits : 24 - 29 (6 bit)
FCS : Frame Counter Selection
bits : 30 - 31 (2 bit)
Enumeration: FCSSelect
0x0 : FC0
Frame Counter 0
0x1 : FC1
Frame Counter 1
0x2 : FC2
Frame Counter 2
End of enumeration elements list.
Automated Bit Mapping Configuration
address_offset : 0x78 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCS : Frame Counter Selection
bits : 0 - 1 (2 bit)
Enumeration: FCSSelect
0x0 : FC0
Frame Counter 0
0x1 : FC1
Frame Counter 1
0x2 : FC2
Frame Counter 2
End of enumeration elements list.
SIZE : Size
bits : 2 - 7 (6 bit)
Character Mapping Segments Data
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SDATA : Segments Data
bits : 0 - 23 (24 bit)
Control D
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLANK : Blank LCD
bits : 0 - 0 (1 bit)
BLINK : Blinking Enable
bits : 1 - 1 (1 bit)
CSREN : Circular Shift Register Enable
bits : 2 - 2 (1 bit)
FC0EN : Frame Counter 0 Enable
bits : 4 - 4 (1 bit)
FC1EN : Frame Counter 1 Enable
bits : 5 - 5 (1 bit)
FC2EN : Frame Counter 2 Enable
bits : 6 - 6 (1 bit)
DISPEN : Display enable
bits : 7 - 7 (1 bit)
Character Mapping Segments Data Mask
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDMASK : Segments Data Mask
bits : 0 - 23 (24 bit)
Character Mapping SEG/COM Index
address_offset : 0x84 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINDEX : SEG Line Index
bits : 0 - 5 (6 bit)
CINDEX : COM Line Index
bits : 8 - 10 (3 bit)
Event Control
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FC0OEO : Frame Counter 0 Overflow Event Output Enable
bits : 0 - 0 (1 bit)
FC1OEO : Frame Counter 1 Overflow Event Output Enable
bits : 1 - 1 (1 bit)
FC2OEO : Frame Counter 2 Overflow Event Output Enable
bits : 2 - 2 (1 bit)
Interrupt Enable Clear
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FC0O : Frame Counter 0 Overflow Interrupt Disable
bits : 0 - 0 (1 bit)
FC1O : Frame Counter 1 Overflow Interrupt Disable
bits : 1 - 1 (1 bit)
FC2O : Frame Counter 2 Overflow Interrupt Disable
bits : 2 - 2 (1 bit)
VLCDRT : VLCD Ready Toggle Interrupt Disable
bits : 3 - 3 (1 bit)
VLCDST : VLCD Status Toggle Interrupt Disable
bits : 4 - 4 (1 bit)
PRST : Pump Run Status Toggle Interrupt Disable
bits : 5 - 5 (1 bit)
Interrupt Enable Set
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FC0O : Frame Counter 0 Overflow Interrupt Enable
bits : 0 - 0 (1 bit)
FC1O : Frame Counter 1 Overflow Interrupt Enable
bits : 1 - 1 (1 bit)
FC2O : Frame Counter 2 Overflow Interrupt Enable
bits : 2 - 2 (1 bit)
VLCDRT : VLCD Ready Toggle Interrupt Enable
bits : 3 - 3 (1 bit)
VLCDST : VLCD Status Toggle Interrupt Enable
bits : 4 - 4 (1 bit)
PRST : Pump Run Status Toggle Interrupt Enable
bits : 5 - 5 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FC0O : Frame Counter 0 Overflow
bits : 0 - 0 (1 bit)
FC1O : Frame Counter 1 Overflow
bits : 1 - 1 (1 bit)
FC2O : Frame Counter 2 Overflow
bits : 2 - 2 (1 bit)
VLCDRT : VLCD Ready Toggle
bits : 3 - 3 (1 bit)
VLCDST : VLCD Status Toggle
bits : 4 - 4 (1 bit)
PRST : Pump Run Status Toggle
bits : 5 - 5 (1 bit)
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