\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Interrupt mask register (EXTI_IMR)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IM0 : Interrupt Mask on line 0
bits : 0 - 0 (1 bit)
IM1 : Interrupt Mask on line 1
bits : 1 - 1 (1 bit)
IM2 : Interrupt Mask on line 2
bits : 2 - 2 (1 bit)
IM3 : Interrupt Mask on line 3
bits : 3 - 3 (1 bit)
IM4 : Interrupt Mask on line 4
bits : 4 - 4 (1 bit)
IM5 : Interrupt Mask on line 5
bits : 5 - 5 (1 bit)
IM6 : Interrupt Mask on line 6
bits : 6 - 6 (1 bit)
IM7 : Interrupt Mask on line 7
bits : 7 - 7 (1 bit)
IM8 : Interrupt Mask on line 8
bits : 8 - 8 (1 bit)
IM9 : Interrupt Mask on line 9
bits : 9 - 9 (1 bit)
IM10 : Interrupt Mask on line 10
bits : 10 - 10 (1 bit)
IM11 : Interrupt Mask on line 11
bits : 11 - 11 (1 bit)
IM12 : Interrupt Mask on line 12
bits : 12 - 12 (1 bit)
IM13 : Interrupt Mask on line 13
bits : 13 - 13 (1 bit)
IM14 : Interrupt Mask on line 14
bits : 14 - 14 (1 bit)
IM15 : Interrupt Mask on line 15
bits : 15 - 15 (1 bit)
IM16 : Interrupt Mask on line 16
bits : 16 - 16 (1 bit)
IM17 : Interrupt Mask on line 17
bits : 17 - 17 (1 bit)
IM18 : Interrupt Mask on line 18
bits : 18 - 18 (1 bit)
IM19 : Interrupt Mask on line 19
bits : 19 - 19 (1 bit)
IM20 : Interrupt Mask on line 20
bits : 20 - 20 (1 bit)
IM21 : Interrupt Mask on line 21
bits : 21 - 21 (1 bit)
IM22 : Interrupt Mask on line 22
bits : 22 - 22 (1 bit)
IM23 : Interrupt Mask on line 23
bits : 23 - 23 (1 bit)
IM24 : Interrupt Mask on line 24
bits : 24 - 24 (1 bit)
IM25 : Interrupt Mask on line 25
bits : 25 - 25 (1 bit)
IM26 : Interrupt Mask on line 27
bits : 26 - 26 (1 bit)
IM28 : Interrupt Mask on line 27
bits : 28 - 28 (1 bit)
IM29 : Interrupt Mask on line 27
bits : 29 - 29 (1 bit)
Software interrupt event register (EXTI_SWIER)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWI0 : Software Interrupt on line 0
bits : 0 - 0 (1 bit)
SWI1 : Software Interrupt on line 1
bits : 1 - 1 (1 bit)
SWI2 : Software Interrupt on line 2
bits : 2 - 2 (1 bit)
SWI3 : Software Interrupt on line 3
bits : 3 - 3 (1 bit)
SWI4 : Software Interrupt on line 4
bits : 4 - 4 (1 bit)
SWI5 : Software Interrupt on line 5
bits : 5 - 5 (1 bit)
SWI6 : Software Interrupt on line 6
bits : 6 - 6 (1 bit)
SWI7 : Software Interrupt on line 7
bits : 7 - 7 (1 bit)
SWI8 : Software Interrupt on line 8
bits : 8 - 8 (1 bit)
SWI9 : Software Interrupt on line 9
bits : 9 - 9 (1 bit)
SWI10 : Software Interrupt on line 10
bits : 10 - 10 (1 bit)
SWI11 : Software Interrupt on line 11
bits : 11 - 11 (1 bit)
SWI12 : Software Interrupt on line 12
bits : 12 - 12 (1 bit)
SWI13 : Software Interrupt on line 13
bits : 13 - 13 (1 bit)
SWI14 : Software Interrupt on line 14
bits : 14 - 14 (1 bit)
SWI15 : Software Interrupt on line 15
bits : 15 - 15 (1 bit)
SWI16 : Software Interrupt on line 16
bits : 16 - 16 (1 bit)
SWI17 : Software Interrupt on line 17
bits : 17 - 17 (1 bit)
SWI19 : Software Interrupt on line 19
bits : 19 - 19 (1 bit)
SWI20 : Software Interrupt on line 20
bits : 20 - 20 (1 bit)
SWI21 : Software Interrupt on line 21
bits : 21 - 21 (1 bit)
SWI22 : Software Interrupt on line 22
bits : 22 - 22 (1 bit)
Pending register (EXTI_PR)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIF0 : Pending bit 0
bits : 0 - 0 (1 bit)
PIF1 : Pending bit 1
bits : 1 - 1 (1 bit)
PIF2 : Pending bit 2
bits : 2 - 2 (1 bit)
PIF3 : Pending bit 3
bits : 3 - 3 (1 bit)
PIF4 : Pending bit 4
bits : 4 - 4 (1 bit)
PIF5 : Pending bit 5
bits : 5 - 5 (1 bit)
PIF6 : Pending bit 6
bits : 6 - 6 (1 bit)
PIF7 : Pending bit 7
bits : 7 - 7 (1 bit)
PIF8 : Pending bit 8
bits : 8 - 8 (1 bit)
PIF9 : Pending bit 9
bits : 9 - 9 (1 bit)
PIF10 : Pending bit 10
bits : 10 - 10 (1 bit)
PIF11 : Pending bit 11
bits : 11 - 11 (1 bit)
PIF12 : Pending bit 12
bits : 12 - 12 (1 bit)
PIF13 : Pending bit 13
bits : 13 - 13 (1 bit)
PIF14 : Pending bit 14
bits : 14 - 14 (1 bit)
PIF15 : Pending bit 15
bits : 15 - 15 (1 bit)
PIF16 : Pending bit 16
bits : 16 - 16 (1 bit)
PIF17 : Pending bit 17
bits : 17 - 17 (1 bit)
PIF19 : Pending bit 19
bits : 19 - 19 (1 bit)
PIF20 : Pending bit 20
bits : 20 - 20 (1 bit)
PIF21 : Pending bit 21
bits : 21 - 21 (1 bit)
PIF22 : Pending bit 22
bits : 22 - 22 (1 bit)
Event mask register (EXTI_EMR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EM0 : Event Mask on line 0
bits : 0 - 0 (1 bit)
EM1 : Event Mask on line 1
bits : 1 - 1 (1 bit)
EM2 : Event Mask on line 2
bits : 2 - 2 (1 bit)
EM3 : Event Mask on line 3
bits : 3 - 3 (1 bit)
EM4 : Event Mask on line 4
bits : 4 - 4 (1 bit)
EM5 : Event Mask on line 5
bits : 5 - 5 (1 bit)
EM6 : Event Mask on line 6
bits : 6 - 6 (1 bit)
EM7 : Event Mask on line 7
bits : 7 - 7 (1 bit)
EM8 : Event Mask on line 8
bits : 8 - 8 (1 bit)
EM9 : Event Mask on line 9
bits : 9 - 9 (1 bit)
EM10 : Event Mask on line 10
bits : 10 - 10 (1 bit)
EM11 : Event Mask on line 11
bits : 11 - 11 (1 bit)
EM12 : Event Mask on line 12
bits : 12 - 12 (1 bit)
EM13 : Event Mask on line 13
bits : 13 - 13 (1 bit)
EM14 : Event Mask on line 14
bits : 14 - 14 (1 bit)
EM15 : Event Mask on line 15
bits : 15 - 15 (1 bit)
EM16 : Event Mask on line 16
bits : 16 - 16 (1 bit)
EM17 : Event Mask on line 17
bits : 17 - 17 (1 bit)
EM18 : Event Mask on line 18
bits : 18 - 18 (1 bit)
EM19 : Event Mask on line 19
bits : 19 - 19 (1 bit)
EM20 : Event Mask on line 20
bits : 20 - 20 (1 bit)
EM21 : Event Mask on line 21
bits : 21 - 21 (1 bit)
EM22 : Event Mask on line 22
bits : 22 - 22 (1 bit)
EM23 : Event Mask on line 23
bits : 23 - 23 (1 bit)
EM24 : Event Mask on line 24
bits : 24 - 24 (1 bit)
EM25 : Event Mask on line 25
bits : 25 - 25 (1 bit)
EM26 : Event Mask on line 26
bits : 26 - 26 (1 bit)
EM28 : Event Mask on line 28
bits : 28 - 28 (1 bit)
EM29 : Event Mask on line 29
bits : 29 - 29 (1 bit)
Rising Trigger selection register (EXTI_RTSR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RT0 : Rising trigger event configuration of line 0
bits : 0 - 0 (1 bit)
RT1 : Rising trigger event configuration of line 1
bits : 1 - 1 (1 bit)
RT2 : Rising trigger event configuration of line 2
bits : 2 - 2 (1 bit)
RT3 : Rising trigger event configuration of line 3
bits : 3 - 3 (1 bit)
RT4 : Rising trigger event configuration of line 4
bits : 4 - 4 (1 bit)
RT5 : Rising trigger event configuration of line 5
bits : 5 - 5 (1 bit)
RT6 : Rising trigger event configuration of line 6
bits : 6 - 6 (1 bit)
RT7 : Rising trigger event configuration of line 7
bits : 7 - 7 (1 bit)
RT8 : Rising trigger event configuration of line 8
bits : 8 - 8 (1 bit)
RT9 : Rising trigger event configuration of line 9
bits : 9 - 9 (1 bit)
RT10 : Rising trigger event configuration of line 10
bits : 10 - 10 (1 bit)
RT11 : Rising trigger event configuration of line 11
bits : 11 - 11 (1 bit)
RT12 : Rising trigger event configuration of line 12
bits : 12 - 12 (1 bit)
RT13 : Rising trigger event configuration of line 13
bits : 13 - 13 (1 bit)
RT14 : Rising trigger event configuration of line 14
bits : 14 - 14 (1 bit)
RT15 : Rising trigger event configuration of line 15
bits : 15 - 15 (1 bit)
RT16 : Rising trigger event configuration of line 16
bits : 16 - 16 (1 bit)
RT17 : Rising trigger event configuration of line 17
bits : 17 - 17 (1 bit)
RT19 : Rising trigger event configuration of line 19
bits : 19 - 19 (1 bit)
RT20 : Rising trigger event configuration of line 20
bits : 20 - 20 (1 bit)
RT21 : Rising trigger event configuration of line 21
bits : 21 - 21 (1 bit)
RT22 : Rising trigger event configuration of line 22
bits : 22 - 22 (1 bit)
Falling Trigger selection register (EXTI_FTSR)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FT0 : Falling trigger event configuration of line 0
bits : 0 - 0 (1 bit)
FT1 : Falling trigger event configuration of line 1
bits : 1 - 1 (1 bit)
FT2 : Falling trigger event configuration of line 2
bits : 2 - 2 (1 bit)
FT3 : Falling trigger event configuration of line 3
bits : 3 - 3 (1 bit)
FT4 : Falling trigger event configuration of line 4
bits : 4 - 4 (1 bit)
FT5 : Falling trigger event configuration of line 5
bits : 5 - 5 (1 bit)
FT6 : Falling trigger event configuration of line 6
bits : 6 - 6 (1 bit)
FT7 : Falling trigger event configuration of line 7
bits : 7 - 7 (1 bit)
FT8 : Falling trigger event configuration of line 8
bits : 8 - 8 (1 bit)
FT9 : Falling trigger event configuration of line 9
bits : 9 - 9 (1 bit)
FT10 : Falling trigger event configuration of line 10
bits : 10 - 10 (1 bit)
FT11 : Falling trigger event configuration of line 11
bits : 11 - 11 (1 bit)
FT12 : Falling trigger event configuration of line 12
bits : 12 - 12 (1 bit)
FT13 : Falling trigger event configuration of line 13
bits : 13 - 13 (1 bit)
FT14 : Falling trigger event configuration of line 14
bits : 14 - 14 (1 bit)
FT15 : Falling trigger event configuration of line 15
bits : 15 - 15 (1 bit)
FT16 : Falling trigger event configuration of line 16
bits : 16 - 16 (1 bit)
FT17 : Falling trigger event configuration of line 17
bits : 17 - 17 (1 bit)
FT19 : Falling trigger event configuration of line 19
bits : 19 - 19 (1 bit)
FT20 : Falling trigger event configuration of line 20
bits : 20 - 20 (1 bit)
FT21 : Falling trigger event configuration of line 21
bits : 21 - 21 (1 bit)
FT22 : Falling trigger event configuration of line 22
bits : 22 - 22 (1 bit)
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