\n
address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 0x22 byte (0x0)
mem_usage : registers
protection :
Control A
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Command
bits : 0 - 6 (7 bit)
Enumeration: CMDSelect
0x2 : ER
Erase Row - Erases the row addressed by the ADDR register.
0x4 : WP
Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.
0x5 : EAR
Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.
0x6 : WAP
Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.
0xa : SF
Security Flow Command
0xf : WL
Write lockbits
0x1a : RWWEEER
RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register.
0x1c : RWWEEWP
RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.
0x40 : LR
Lock Region - Locks the region containing the address location in the ADDR register.
0x41 : UR
Unlock Region - Unlocks the region containing the address location in the ADDR register.
0x42 : SPRM
Sets the power reduction mode.
0x43 : CPRM
Clears the power reduction mode.
0x44 : PBC
Page Buffer Clear - Clears the page buffer.
0x45 : SSB
Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.
0x46 : INVALL
Invalidate all cache lines.
End of enumeration elements list.
CMDEX : Command Execution
bits : 8 - 15 (8 bit)
Enumeration: CMDEXSelect
0xa5 : KEY
Execution Key
End of enumeration elements list.
Interrupt Enable Set
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READY : NVM Ready Interrupt Enable
bits : 0 - 0 (1 bit)
ERROR : Error Interrupt Enable
bits : 1 - 1 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READY : NVM Ready
bits : 0 - 0 (1 bit)
ERROR : Error
bits : 1 - 1 (1 bit)
Status
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRM : Power Reduction Mode
bits : 0 - 0 (1 bit)
access : read-only
LOAD : NVM Page Buffer Active Loading
bits : 1 - 1 (1 bit)
PROGE : Programming Error Status
bits : 2 - 2 (1 bit)
LOCKE : Lock Error Status
bits : 3 - 3 (1 bit)
NVME : NVM Error
bits : 4 - 4 (1 bit)
SB : Security Bit Status
bits : 8 - 8 (1 bit)
access : read-only
Address
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : NVM Address
bits : 0 - 21 (22 bit)
Lock Section
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : Region Lock Bits
bits : 0 - 15 (16 bit)
access : read-only
Control B
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWS : NVM Read Wait States
bits : 1 - 4 (4 bit)
Enumeration: RWSSelect
0x0 : SINGLE
Single Auto Wait State
0x1 : HALF
Half Auto Wait State
0x2 : DUAL
Dual Auto Wait State
End of enumeration elements list.
MANW : Manual Write
bits : 7 - 7 (1 bit)
SLEEPPRM : Power Reduction Mode during Sleep
bits : 8 - 9 (2 bit)
Enumeration: SLEEPPRMSelect
0x0 : WAKEONACCESS
NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.
0x1 : WAKEUPINSTANT
NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.
0x3 : DISABLED
Auto power reduction disabled.
End of enumeration elements list.
FWUP : fast wake-up
bits : 11 - 11 (1 bit)
READMODE : NVMCTRL Read Mode
bits : 16 - 17 (2 bit)
Enumeration: READMODESelect
0x0 : NO_MISS_PENALTY
The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.
0x1 : LOW_POWER
Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.
0x2 : DETERMINISTIC
The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.
End of enumeration elements list.
CACHEDIS : Cache Disable
bits : 18 - 18 (1 bit)
NVM Parameter
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVMP : NVM Pages
bits : 0 - 15 (16 bit)
access : read-only
PSZ : Page Size
bits : 16 - 18 (3 bit)
access : read-only
Enumeration: PSZSelect
0x0 : 8
8 bytes
0x1 : 16
16 bytes
0x2 : 32
32 bytes
0x3 : 64
64 bytes
0x4 : 128
128 bytes
0x5 : 256
256 bytes
0x6 : 512
512 bytes
0x7 : 1024
1024 bytes
End of enumeration elements list.
RWWEEP : RWW EEPROM Pages
bits : 20 - 31 (12 bit)
access : read-only
Interrupt Enable Clear
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
READY : NVM Ready Interrupt Enable
bits : 0 - 0 (1 bit)
ERROR : Error Interrupt Enable
bits : 1 - 1 (1 bit)
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