\n
address_offset : 0x0 Bytes (0x0)
size : 0x1058 byte (0x0)
mem_usage : registers
protection : not protected
MAC Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RE : Receiver Enable
bits : 2 - 1 (0 bit)
access : read-write
TE : Transmitter Enable
bits : 3 - 2 (0 bit)
access : read-write
DC : Deferral Check
bits : 4 - 3 (0 bit)
access : read-write
BL : Back-off Limit
bits : 5 - 5 (1 bit)
access : read-write
ACS : Automatic Pad/CRC Stripping
bits : 7 - 6 (0 bit)
access : read-write
LUD : Link Up/Down in RGMII
bits : 8 - 7 (0 bit)
access : read-write
DR : Disable Retry
bits : 9 - 8 (0 bit)
access : read-write
IPC : Checksum Offload
bits : 10 - 9 (0 bit)
access : read-write
DM : Duplex mode
bits : 11 - 10 (0 bit)
access : read-write
LM : Loop-back Mode
bits : 12 - 11 (0 bit)
access : read-write
DO : Disable Receive Own
bits : 13 - 12 (0 bit)
access : read-write
FES : Speed
bits : 14 - 13 (0 bit)
access : read-write
PS : Port Select
bits : 15 - 14 (0 bit)
access : read-write
DCRS : Disable Carrier Sense During Transaction
bits : 16 - 15 (0 bit)
access : read-write
IFG : Inter-Frame GAP
bits : 17 - 18 (2 bit)
access : read-write
JE : Jumbo Frame Enable
bits : 20 - 19 (0 bit)
access : read-write
BE : Frame Burst Enable
bits : 21 - 20 (0 bit)
access : read-write
JD : Jabber Disable
bits : 22 - 21 (0 bit)
access : read-write
WD : Watchdog Disable
bits : 23 - 22 (0 bit)
access : read-write
TC : Transmit Configuration in RGMII
bits : 24 - 23 (0 bit)
access : read-write
CST : CRC stripping for Type frames
bits : 25 - 24 (0 bit)
access : read-write
GMII/MII Address Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GB : GMII/MII Busy
bits : 0 - -1 (0 bit)
access : read-write
GW : GMII/MII Write
bits : 1 - 0 (0 bit)
access : read-write
CR : Application Clock Range
bits : 2 - 4 (3 bit)
access : read-write
GR : GMII Register
bits : 6 - 9 (4 bit)
access : read-write
PA : Physical Layer Address
bits : 11 - 14 (4 bit)
access : read-write
MMC Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Bus Mode Register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWR : Software Reset
bits : 0 - -1 (0 bit)
access : read-write
DA : DMA Arbitration scheme
bits : 1 - 0 (0 bit)
access : read-write
DSL : Descriptor Skip Length
bits : 2 - 5 (4 bit)
access : read-write
ATDS : Alternate Descriptor Size
bits : 7 - 6 (0 bit)
access : read-write
PBL : Programmable Burst Length
bits : 8 - 12 (5 bit)
access : read-write
PR : Rx:Tx priority ratio
bits : 14 - 14 (1 bit)
access : read-write
FB : Fixed Burst
bits : 16 - 15 (0 bit)
access : read-write
RPBL : RxDMA PBL
bits : 17 - 21 (5 bit)
access : read-write
USP : Use Separate PBL
bits : 23 - 22 (0 bit)
access : read-write
_8XPBL : 8xPBL Mode
bits : 24 - 23 (0 bit)
access : read-write
AAL : Address-Aligned Beats
bits : 25 - 24 (0 bit)
access : read-write
MB : Mixed Burst
bits : 26 - 25 (0 bit)
access : read-write
TXPR : Transmit Priority
bits : 27 - 26 (0 bit)
access : read-write
Transmit Poll Demand Register)
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPD : Transmit Poll Demand
bits : 0 - 30 (31 bit)
access : read-write
Receive Poll Demand Register
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPD : Receive Poll Demand
bits : 0 - 30 (31 bit)
access : read-write
Receive Descriptor List Address Register)
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRL : Start of Receive List
bits : 2 - 30 (29 bit)
access : read-write
Transmit Descriptor List Address Register
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STL : Start of Transmit List
bits : 2 - 30 (29 bit)
access : read-write
Status Register
address_offset : 0x1014 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TI : Transmit Interrupt
bits : 0 - -1 (0 bit)
access : read-only
TPS : Transmit Process Stopped
bits : 1 - 0 (0 bit)
access : read-only
TU : Transmit Buffer Unavailable
bits : 2 - 1 (0 bit)
access : read-only
TJT : Transmit Jabber Timeout
bits : 3 - 2 (0 bit)
access : read-only
OVF : Receive Overflow
bits : 4 - 3 (0 bit)
access : read-only
UNF : Transmit underflow
bits : 5 - 4 (0 bit)
access : read-only
RI : Receive Interrupt
bits : 6 - 5 (0 bit)
access : read-only
RU : Receive Buffer Unavailable
bits : 7 - 6 (0 bit)
access : read-only
RPS : Receive process Stopped
bits : 8 - 7 (0 bit)
access : read-only
RWT : Receive Watchdog Timeout
bits : 9 - 8 (0 bit)
access : read-only
ETI : Early Transmit Interrupt
bits : 10 - 9 (0 bit)
access : read-only
FBI : Fatal Bus Error Interrupt
bits : 13 - 12 (0 bit)
access : read-only
ERI : Early Receive Interrupt
bits : 14 - 13 (0 bit)
access : read-only
AIS : Abnormal Interrupt Summary
bits : 15 - 14 (0 bit)
access : read-only
NIS : Normal Interrupt Summary
bits : 16 - 15 (0 bit)
access : read-only
RS : Receive Process State
bits : 17 - 18 (2 bit)
access : read-only
TS : Transmit Process State
bits : 20 - 21 (2 bit)
access : read-only
EB : Error Bits
bits : 23 - 24 (2 bit)
access : read-only
GLI : GMAC Line interface Interrupt
bits : 26 - 25 (0 bit)
access : read-only
GMI : GMAC MMC Interrupt
bits : 27 - 26 (0 bit)
access : read-only
GPI : GMAC PMT Interrupt
bits : 28 - 27 (0 bit)
access : read-only
TTI : Time-Stamp Trigger Interrupt
bits : 29 - 28 (0 bit)
access : read-only
GLPII : GMAC LPI Interrupt
bits : 30 - 29 (0 bit)
access : read-only
Operation Mode Register
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SR : Start/Stop Receive
bits : 1 - 0 (0 bit)
access : read-write
OSF : Operate on Second Frame
bits : 2 - 1 (0 bit)
access : read-write
RTC : Receive Threshold Control
bits : 3 - 3 (1 bit)
access : read-write
FUF : Forward Undersized Good Frames
bits : 6 - 5 (0 bit)
access : read-write
FEF : Forward Error Frames
bits : 7 - 6 (0 bit)
access : read-write
ST : Start/Stop Transmission Command
bits : 13 - 12 (0 bit)
access : read-write
TTC : Transmit Threshold Control
bits : 14 - 15 (2 bit)
access : read-write
FTF : Flush Transmit FIFO
bits : 20 - 19 (0 bit)
access : read-write
TSF : Transmit Store Forward
bits : 21 - 20 (0 bit)
access : read-write
DFF : Disable Flushing of Received Frames
bits : 24 - 23 (0 bit)
access : read-write
RSF : Receive Store and Forward
bits : 25 - 24 (0 bit)
access : read-write
DT : Disable Dropping of TCP/IP Checksum Error Frames
bits : 26 - 25 (0 bit)
access : read-write
Interrupt Enable Register
address_offset : 0x101C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIE : Transmit Interrupt
bits : 0 - -1 (0 bit)
access : read-write
TSE : Transmit Process Stopped
bits : 1 - 0 (0 bit)
access : read-write
TUE : Transmit Buffer Unavailable
bits : 2 - 1 (0 bit)
access : read-write
TJE : Transmit Jabber Timeout
bits : 3 - 2 (0 bit)
access : read-write
OVE : Receive Overflow Enable
bits : 4 - 3 (0 bit)
access : read-only
UNE : Transmit underflow Enable
bits : 5 - 4 (0 bit)
access : read-write
RIE : Receive Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
RUE : Receive Buffer Unavailable Enable
bits : 7 - 6 (0 bit)
access : read-write
RSE : Receive Process Stopped Enable
bits : 8 - 7 (0 bit)
access : read-write
RWE : Receive Watchdog Timeout Enable
bits : 9 - 8 (0 bit)
access : read-write
ETE : Early Transmit Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
FBE : Fatal Bus Error Enable
bits : 13 - 12 (0 bit)
access : read-write
ERE : Early Receive Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
AIE : Abnormal Interrupt Summary Enable
bits : 15 - 14 (0 bit)
access : read-write
NIE : Normal Interrupt Summary Enable
bits : 16 - 15 (0 bit)
access : read-write
Missed Frame and Buffer Overflow Counter Register
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NMFH : Number of Missed frame by HOST
bits : 0 - 14 (15 bit)
access : read-only
ONMFH : Overflow NMFH
bits : 16 - 15 (0 bit)
access : read-only
NMFF : Number of Missed frame by Ethernet-MAC
bits : 17 - 26 (10 bit)
access : read-only
ONMFF : Overflow NMFF
bits : 28 - 27 (0 bit)
access : read-only
Receive Interrupt Watchdog Timer Register
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RIWT : RI Watchdog Timer count
bits : 0 - 6 (7 bit)
access : read-only
AHB Status Register
address_offset : 0x102C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AHBS : AHB Status
bits : 0 - -1 (0 bit)
access : read-only
Receive Interrupt Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Current Host Transmit Descriptor Register
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HTDAP : Host Transmit Descriptor Address Pointer
bits : 0 - 30 (31 bit)
access : read-only
Current Host Receive Descriptor Register
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HRDAP : Host Receive Descriptor Address Pointer
bits : 0 - 30 (31 bit)
access : read-only
Current Host Transmit Buffer Address Register
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HTBAR : Host Transmit Buffer Address Register
bits : 0 - 30 (31 bit)
access : read-only
Current Host Receive Buffer Address Register
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HRBAR : Host Receive Buffer Address Register
bits : 0 - 30 (31 bit)
access : read-only
MMC Transmit Interrupt Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MMC Receive Interrupt Mask Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MMC Transmit Interrupt Mask Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Number of bytes transmitted, exclusive of preamble and retried bytes, in good and bad frames
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad frames transmitted, exclusive of retried frames
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good broadcast frames transmitted
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good multicast frames transmitted
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad frames transmitted with length of 64 bytes, exclusive of preamble and retried frames
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad frames transmitted with length between 512 and 1023 (inclusive) bytes, exclusive of preamble and retried frames
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad frames transmitted with length between 1024 and Maxsize (inclusive) bytes, exclusive of preamble and retried frames
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad unicast frames transmitted
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GMII/MII Data Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GD : GMII/MII Data Register
bits : 0 - 14 (15 bit)
access : read-write
Number of good and bad multicast frames transmitted
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad broadcast frames transmitted
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of frames aborted due to frame underflow error
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of successfully transmitted frames after a single collision in Half-duplex mode
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of successfully transmitted frames after more than a single collision in Half-duplex mode
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of successfully transmitted frames after a deferral in Half-duplex mode.
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of frames aborted due to late collision error.
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of frames aborted due to excessive (16) collision errors.
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of frames aborted due to carrier sense error (no carrier or loss of carrier).
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes transmitted, exclusive of preamble, in good frames only.
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good frames transmitted.
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of frames aborted due to excessive deferral error (deferred for more than two max-sized frame times).
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good PAUSE frames transmitted.
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good VLAN frames transmitted, exclusive of retried frames.
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Flow Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCB_BPA : Flow Control Busy/Backpressure Activate
bits : 0 - -1 (0 bit)
access : read-write
TFE : Transmit Flow Control Enable
bits : 1 - 0 (0 bit)
access : read-write
RFE : Receive Flow Control Enable
bits : 2 - 1 (0 bit)
access : read-write
UP : Unicast Pause Frame detect
bits : 3 - 2 (0 bit)
access : read-write
PLT : Pause Low Threshold
bits : 4 - 4 (1 bit)
access : read-write
DZPQ : Disable Zero-Quanta Pause
bits : 7 - 6 (0 bit)
access : read-write
PT : Pause Time
bits : 16 - 30 (15 bit)
access : read-write
Number of good and bad frames received.
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received, exclusive of preamble, in good and bad frames.
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received, exclusive of preamble, only in good frames.
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good broadcast frames received.
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good multicast frames received.
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of frames received with CRC error.
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of frames received with alignment (dribble) error. Valid only in 10/100 mode.
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of frames received with runt (64 bytes and CRC error) error.
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of frames received with length greater than 1518 bytes with CRC error.
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of frames received with length less than 64 bytes, without any errors.
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of frames received with length greater than the maxsize without error.
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad frames received with length 64 bytes, exclusive of preamble.
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble.
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble.
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad frames received with length between 256 and 511 (inclusive) bytes, exclusive of preamble.
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad frames received with length between 512 and 1023 (inclusive) bytes, exclusive of preamble.
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VLAN TAG Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VL : VLAN Tag Identifier
bits : 0 - 14 (15 bit)
access : read-write
ETV : Enable 12-Bit VLAN Tag Comparison
bits : 16 - 15 (0 bit)
access : read-write
Number of good and bad frames received with length between 1024 and maxsize (inclusive) bytes, exclusive of preamble.
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good unicast frames received.
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of frames received with length error (Length type field is not the frame size), for all frames with valid length field.
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of frames received with length/type field not equal to the valid frame size (>1500)
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and valid PAUSE frames received.
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of missed received frames due to FIFO overflow.
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good and bad VLAN frames received.
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of frames received with error due to watchdog timeout error (frames with a data load larger than 2048 bytes).
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MMC Receive Checksum Offload Interrupt Mask Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MMC Receive Checksum Offload Interrupt Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of IPv4 datagrams received with header errors (checksum, length, or version mismatch)
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good IPv4 datagrams with fragmentation
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good IPv4 datagrams received that had a UDP payload with checksum disabled
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of IPv6 datagrams received with header errors (length or version mismatch)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good IP datagrams with a good UDP payload. This counter is not updated when the rxipv4_udsbl_frms counter is incremented.
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good IP datagrams whose UDP payload has a checksum error
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good IP datagrams with a good TCP payload
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good IP datagrams whose TCP payload has a checksum error
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good IP datagrams with a good ICMP payload
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of good IP datagrams whose ICMP payload has a checksum error
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter or in the octet counters listed below).
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter.
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 header's Length field is used to update this counter.
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 header's Length field is used to update this counter.
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes.
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received in IPv6 datagrams with header errors (length, version mismatch). The value in the IPv6 header's Length field is used to update this counter.
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 header's Length field is used to update this counter.
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received in a good UDP segment. This counter (and the counters below) does not count IP header bytes.
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received in a UDP segment that had checksum errors
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received in a good TCP segment
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received in a TCP segment with checksum errors
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Remote Wake-up Frame Filter Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWFFR : Remote Wake-up Frame Filter Register
bits : 0 - 30 (31 bit)
access : read-write
Number of bytes received in a good ICMP segment
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Number of bytes received in an ICMP segment with checksum errors
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PMT Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD : Power Down
bits : 0 - -1 (0 bit)
access : read-write
MPE : Magic Packet Enable
bits : 1 - 0 (0 bit)
access : read-write
WFE : Wake-Up Frame Enable
bits : 2 - 1 (0 bit)
access : read-write
MPR : Magic Packet Received
bits : 5 - 4 (0 bit)
access : read-write
WPR : Wake Up Frame Receive
bits : 6 - 5 (0 bit)
access : read-write
GU : Global Unicast
bits : 9 - 8 (0 bit)
access : read-write
RWFFRPR : Remote Wake-up Frame Filter Register Pointer Reset
bits : 31 - 30 (0 bit)
access : read-write
LPI Control and Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TLPIEN : Transmit LPI Entry
bits : 0 - -1 (0 bit)
access : read-only
TLPIEX : Transmit LPI Exit
bits : 1 - 0 (0 bit)
access : read-only
RLPIEN : Receive LPI Entry
bits : 2 - 1 (0 bit)
access : read-only
RLPIEX : Receive LPI Exit
bits : 3 - 2 (0 bit)
access : read-only
TLPIST : Transmit LPI State
bits : 8 - 7 (0 bit)
access : read-only
RLPIST : Receive LPI State
bits : 9 - 8 (0 bit)
access : read-only
LPIEN : LPI Enable
bits : 16 - 15 (0 bit)
access : read-write
PLS : PHY Link Status
bits : 17 - 16 (0 bit)
access : read-write
PLSEN : PHY Link Status Enable
bits : 18 - 17 (0 bit)
access : read-write
LPITXA : LPI TX Automate
bits : 19 - 18 (0 bit)
access : read-write
LPI Timers Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TWT : LPI TW TIMER
bits : 0 - 14 (15 bit)
access : read-write
LIT : LPI LS TIMER
bits : 16 - 24 (9 bit)
access : read-write
Interrupt Status Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RGIS : RGMII Interrupt Status
bits : 0 - -1 (0 bit)
access : read-only
PIS : PMT Interrupt Status
bits : 3 - 2 (0 bit)
access : read-only
MIS : MMC Interrupt Status
bits : 4 - 3 (0 bit)
access : read-only
RIS : MMC Receive Interrupt Status
bits : 5 - 4 (0 bit)
access : read-only
TIS : MMC Transmit Interrupt Status
bits : 6 - 5 (0 bit)
access : read-only
COIS : MMC Receive Checksum Offload Interrupt Status
bits : 7 - 6 (0 bit)
access : read-only
TSIS : Time Stamp Interrupt Status
bits : 9 - 8 (0 bit)
access : read-only
LPIIS : LPI Interrupt Status
bits : 10 - 9 (0 bit)
access : read-only
Interrupt Mask Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RGIM : RGMII Interrupt Mask
bits : 0 - -1 (0 bit)
access : read-write
PIM : PMT Interrupt Mask
bits : 3 - 2 (0 bit)
access : read-write
TSIM : Time Stamp Interrupt Mask
bits : 9 - 8 (0 bit)
access : read-write
LPIIM : LPI Interrupt Mask
bits : 10 - 9 (0 bit)
access : read-write
MAC Frame Filter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PR : Promiscuous Mode
bits : 0 - -1 (0 bit)
access : read-write
HUC : Hash Unicast
bits : 1 - 0 (0 bit)
access : read-write
HMC : Hash Multicast
bits : 2 - 1 (0 bit)
access : read-write
DAIF : DA Inverse Filtering
bits : 3 - 2 (0 bit)
access : read-write
PM : Pass All Multicast
bits : 4 - 3 (0 bit)
access : read-write
DB : Disable Broadcast Frames
bits : 5 - 4 (0 bit)
access : read-write
PCF : Pass Control Frames
bits : 6 - 6 (1 bit)
access : read-write
SAIF : Source Address Inverse Filter
bits : 8 - 7 (0 bit)
access : read-write
SAF : Source Address Filter
bits : 9 - 8 (0 bit)
access : read-write
HPF : Hash or Perfect Filter
bits : 10 - 9 (0 bit)
access : read-write
RA : Receive All
bits : 31 - 30 (0 bit)
access : read-write
MAC Address0 Register (High)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A0 : MAC Address0
bits : 0 - 14 (15 bit)
access : read-write
MO : Must be one
bits : 31 - 30 (0 bit)
access : read-only
MAC Address0 Register (Low)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A0 : MAC Address0
bits : 0 - 30 (31 bit)
access : read-write
MAC Address1 Register -High
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A : MAC Address
bits : 0 - 14 (15 bit)
access : read-write
MBC : Mask Byte Control
bits : 24 - 28 (5 bit)
access : read-write
SA : Source Address
bits : 30 - 29 (0 bit)
access : read-write
AE : Address Enable
bits : 31 - 30 (0 bit)
access : read-write
MAC Address1 Register -Low
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A : MAC Address
bits : 0 - 30 (31 bit)
access : read-write
MAC Address2 Register -High
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address2 Register -Low
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address3 Register -High
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address3 Register -Low
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address4 Register -High
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address4 Register -Low
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address5 Register -High
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address5 Register -Low
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address6 Register -High
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Time Stamp Control Register
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSE : Time Stamp Enable
bits : 0 - -1 (0 bit)
access : read-write
TFCU : Time Stamp Fine or Coarse Update
bits : 1 - 0 (0 bit)
access : read-write
TSI : Time Stamp Initialize
bits : 2 - 1 (0 bit)
access : read-write
TSU : Time Stamp Update
bits : 3 - 2 (0 bit)
access : read-write
TITE : Time Stamp Interrupt Trigger Enable
bits : 4 - 3 (0 bit)
access : read-write
TARU : Addend Register Update
bits : 5 - 4 (0 bit)
access : read-write
TSEA : Enable Time Stamp for All Frames
bits : 8 - 7 (0 bit)
access : read-write
TSDB : Time Stamp Digital or Binary rollover control
bits : 9 - 8 (0 bit)
access : read-write
TSV2E : Enable PTP packet snooping for version 2 format
bits : 10 - 9 (0 bit)
access : read-write
TETSP : Enable Time Stamp Snapshot for PTP over Ethernet frames
bits : 11 - 10 (0 bit)
access : read-write
TSIP6E : Enable Time Stamp Snapshot for IPv6 frames
bits : 12 - 11 (0 bit)
access : read-write
TSIP4E : Enable Time Stamp Snapshot for IPv4 frames
bits : 13 - 12 (0 bit)
access : read-write
TETSEM : Enable Time Stamp Snapshot for Event Messages
bits : 14 - 13 (0 bit)
access : read-write
TSMRM : Enable Snapshot for Messages Relevant to Master
bits : 15 - 14 (0 bit)
access : read-write
TSPS : SelectPTP packets for taking snapshots
bits : 16 - 16 (1 bit)
access : read-write
TSENMF : Enable MAC address for PTP frame filtering
bits : 18 - 17 (0 bit)
access : read-write
ATSFC : Auxiliary Snapshot FIFO Clear
bits : 24 - 23 (0 bit)
access : read-write
Sub-Second Increment Register
address_offset : 0x704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSINC : Sub-Second Increment Value
bits : 0 - 6 (7 bit)
access : read-write
System Time - Seconds Register
address_offset : 0x708 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TSS : Time Stamp Second
bits : 0 - 30 (31 bit)
access : read-only
System Time - Nanoseconds Register
address_offset : 0x70C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TSSS : Time Stamp Sub-Seconds
bits : 0 - 29 (30 bit)
access : read-only
System Time - Seconds Update Register
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSS : Time Stamp Second
bits : 0 - 30 (31 bit)
access : read-write
System Time - Nanoseconds Update Register
address_offset : 0x714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSSS : Time Stamp Sub-Seconds
bits : 0 - 29 (30 bit)
access : read-write
ADDSUB : Add or Subtract Time
bits : 31 - 30 (0 bit)
access : read-write
Time Stamp Addend Register
address_offset : 0x718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSAR : Time Stamp Addend Register
bits : 0 - 30 (31 bit)
access : read-write
Target Time Seconds Register
address_offset : 0x71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTR : Target Time Stamp Seconds Register
bits : 0 - 30 (31 bit)
access : read-write
Target Time Nanoseconds Register
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTR : Target Time Stamp Nanoseconds Register
bits : 0 - 29 (30 bit)
access : read-write
System Time - Higher Word Seconds Register
address_offset : 0x724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSHWR : Time Stamp Higher Word Register
bits : 0 - 14 (15 bit)
access : read-write
Time Stamp Status Register
address_offset : 0x728 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TSSOVF : Time Stamp Seconds Overflow
bits : 0 - -1 (0 bit)
access : read-only
TSTART : Time Stamp Target Time Reached
bits : 1 - 0 (0 bit)
access : read-only
ATSTS : Auxiliary Time Stamp Trigger Snapshot
bits : 2 - 1 (0 bit)
access : read-only
TRGTER : Timestamp Target Time Error
bits : 3 - 2 (0 bit)
access : read-only
ATSSTM : Auxiliary Time Stamp Snapshot Trigger Missed
bits : 24 - 23 (0 bit)
access : read-only
ATSNS : Auxiliary Time Stamp Number of Snapshots
bits : 25 - 26 (2 bit)
access : read-only
PPS Control Register
address_offset : 0x72C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPSCTRL : Controls the frequency of the PPS output
bits : 0 - 2 (3 bit)
access : read-only
Auxiliary Time Stamp - Nanoseconds Register
address_offset : 0x730 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ATN : ATN
bits : 0 - 29 (30 bit)
access : read-only
Auxiliary Time Stamp - Seconds Register
address_offset : 0x734 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ATS : ATS
bits : 0 - 30 (31 bit)
access : read-only
MAC Address6 Register -Low
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address7 Register -High
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address7 Register -Low
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Hash Table Register (High)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTH : the upper 32 bits of the hash table in the HTH
bits : 0 - 30 (31 bit)
access : read-write
MAC Address8 Register -High
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address16 Register -High
address_offset : 0x800 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address16 Register -Low
address_offset : 0x804 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address17 Register -High
address_offset : 0x808 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address17 Register -Low
address_offset : 0x80C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address18 Register -High
address_offset : 0x810 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address18 Register -Low
address_offset : 0x814 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address19 Register -High
address_offset : 0x818 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address19 Register -Low
address_offset : 0x81C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address20 Register -High
address_offset : 0x820 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address20 Register -Low
address_offset : 0x824 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address21 Register -High
address_offset : 0x828 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address21 Register -Low
address_offset : 0x82C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address22 Register -High
address_offset : 0x830 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address22 Register -Low
address_offset : 0x834 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address23 Register -High
address_offset : 0x838 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address23 Register -Low
address_offset : 0x83C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address8 Register -Low
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address24 Register -High
address_offset : 0x840 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address24 Register -Low
address_offset : 0x844 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address25 Register -High
address_offset : 0x848 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address25 Register -Low
address_offset : 0x84C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address26 Register -High
address_offset : 0x850 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address26 Register -Low
address_offset : 0x854 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address27 Register -High
address_offset : 0x858 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address27 Register -Low
address_offset : 0x85C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address28 Register -High
address_offset : 0x860 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address28 Register -Low
address_offset : 0x864 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address29 Register -High
address_offset : 0x868 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address29 Register -Low
address_offset : 0x86C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address30 Register -High
address_offset : 0x870 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address30 Register -Low
address_offset : 0x874 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address31 Register -High
address_offset : 0x878 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address31 Register -Low
address_offset : 0x87C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address9 Register -High
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address9 Register -Low
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address10 Register -High
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address10 Register -Low
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address11 Register -High
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address11 Register -Low
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address12 Register -High
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address12 Register -Low
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address13 Register -High
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address13 Register -Low
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address14 Register -High
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address14 Register -Low
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address15 Register -High
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Address15 Register -Low
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAC Hash Table Register (Low)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTL : the lower 32 bits of the hash table in the HTL
bits : 0 - 30 (31 bit)
access : read-write
RGMII Status Register)
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LM : Link Mode
bits : 0 - -1 (0 bit)
access : read-only
LSP : Link Speed
bits : 1 - 1 (1 bit)
access : read-only
LS : Link Status
bits : 3 - 2 (0 bit)
access : read-only
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