\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
Receive FIFO Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Words received from the serial bus are written to the receive FIFO
bits : 0 - 30 (31 bit)
access : read-only
Channel Control Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S0CH00 : This controls the enable/disable state of the channel 0 in subframe 0
bits : 0 - -1 (0 bit)
access : read-write
S0CH01 : This controls the enable/disable state of the channel 1 in subframe 0
bits : 1 - 0 (0 bit)
access : read-write
S0CH02 : This controls the enable/disable state of the channel 2 in subframe 0
bits : 2 - 1 (0 bit)
access : read-write
S0CH03 : This controls the enable/disable state of the channel 3 in subframe 0
bits : 3 - 2 (0 bit)
access : read-write
S0CH04 : This controls the enable/disable state of the channel 4 in subframe 0
bits : 4 - 3 (0 bit)
access : read-write
S0CH05 : This controls the enable/disable state of the channel 5 in subframe 0
bits : 5 - 4 (0 bit)
access : read-write
S0CH06 : This controls the enable/disable state of the channel 6 in subframe 0
bits : 6 - 5 (0 bit)
access : read-write
S0CH07 : This controls the enable/disable state of the channel 7 in subframe 0
bits : 7 - 6 (0 bit)
access : read-write
S0CH08 : This controls the enable/disable state of the channel 8 in subframe 0
bits : 8 - 7 (0 bit)
access : read-write
S0CH09 : This controls the enable/disable state of the channel 9 in subframe 0
bits : 9 - 8 (0 bit)
access : read-write
S0CH10 : This controls the enable/disable state of the channel 10 in subframe 0
bits : 10 - 9 (0 bit)
access : read-write
S0CH11 : This controls the enable/disable state of the channel 11 in subframe 0
bits : 11 - 10 (0 bit)
access : read-write
S0CH12 : This controls the enable/disable state of the channel 12 in subframe 0
bits : 12 - 11 (0 bit)
access : read-write
S0CH13 : This controls the enable/disable state of the channel 13 in subframe 0
bits : 13 - 12 (0 bit)
access : read-write
S0CH14 : This controls the enable/disable state of the channel 14 in subframe 0
bits : 14 - 13 (0 bit)
access : read-write
S0CH15 : This controls the enable/disable state of the channel 15 in subframe 0
bits : 15 - 14 (0 bit)
access : read-write
S0CH16 : This controls the enable/disable state of the channel 16 in subframe 0
bits : 16 - 15 (0 bit)
access : read-write
S0CH17 : This controls the enable/disable state of the channel 17 in subframe 0
bits : 17 - 16 (0 bit)
access : read-write
S0CH18 : This controls the enable/disable state of the channel 18 in subframe 0
bits : 18 - 17 (0 bit)
access : read-write
S0CH19 : This controls the enable/disable state of the channel 19 in subframe 0
bits : 19 - 18 (0 bit)
access : read-write
S0CH20 : This controls the enable/disable state of the channel 20 in subframe 0
bits : 20 - 19 (0 bit)
access : read-write
S0CH21 : This controls the enable/disable state of the channel 21 in subframe 0
bits : 21 - 20 (0 bit)
access : read-write
S0CH22 : This controls the enable/disable state of the channel 22 in subframe 0
bits : 22 - 21 (0 bit)
access : read-write
S0CH23 : This controls the enable/disable state of the channel 23 in subframe 0
bits : 23 - 22 (0 bit)
access : read-write
S0CH24 : This controls the enable/disable state of the channel 24 in subframe 0
bits : 24 - 23 (0 bit)
access : read-write
S0CH25 : This controls the enable/disable state of the channel 25 in subframe 0
bits : 25 - 24 (0 bit)
access : read-write
S0CH26 : This controls the enable/disable state of the channel 26 in subframe 0
bits : 26 - 25 (0 bit)
access : read-write
S0CH27 : This controls the enable/disable state of the channel 27 in subframe 0
bits : 27 - 26 (0 bit)
access : read-write
S0CH28 : This controls the enable/disable state of the channel 28 in subframe 0
bits : 28 - 27 (0 bit)
access : read-write
S0CH29 : This controls the enable/disable state of the channel 29 in subframe 0
bits : 29 - 28 (0 bit)
access : read-write
S0CH30 : This controls the enable/disable state of the channel 30 in subframe 0
bits : 30 - 29 (0 bit)
access : read-write
S0CH31 : This controls the enable/disable state of the channel 31 in subframe 0
bits : 31 - 30 (0 bit)
access : read-write
Channel Control Register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S1CH00 : This controls the enable/disable state of the channel 0 in subframe 1
bits : 0 - -1 (0 bit)
access : read-write
S1CH01 : This controls the enable/disable state of the channel 1 in subframe 1
bits : 1 - 0 (0 bit)
access : read-write
S1CH02 : This controls the enable/disable state of the channel 2 in subframe 1
bits : 2 - 1 (0 bit)
access : read-write
S1CH03 : This controls the enable/disable state of the channel 3 in subframe 1
bits : 3 - 2 (0 bit)
access : read-write
S1CH04 : This controls the enable/disable state of the channel 4 in subframe 1
bits : 4 - 3 (0 bit)
access : read-write
S1CH05 : This controls the enable/disable state of the channel 5 in subframe 1
bits : 5 - 4 (0 bit)
access : read-write
S1CH06 : This controls the enable/disable state of the channel 6 in subframe 1
bits : 6 - 5 (0 bit)
access : read-write
S1CH07 : This controls the enable/disable state of the channel 7 in subframe 1
bits : 7 - 6 (0 bit)
access : read-write
S1CH08 : This controls the enable/disable state of the channel 8 in subframe 1
bits : 8 - 7 (0 bit)
access : read-write
S1CH09 : This controls the enable/disable state of the channel 9 in subframe 1
bits : 9 - 8 (0 bit)
access : read-write
S1CH10 : This controls the enable/disable state of the channel 10 in subframe 1
bits : 10 - 9 (0 bit)
access : read-write
S1CH11 : This controls the enable/disable state of the channel 11 in subframe 1
bits : 11 - 10 (0 bit)
access : read-write
S1CH12 : This controls the enable/disable state of the channel 12 in subframe 1
bits : 12 - 11 (0 bit)
access : read-write
S1CH13 : This controls the enable/disable state of the channel 13 in subframe 1
bits : 13 - 12 (0 bit)
access : read-write
S1CH14 : This controls the enable/disable state of the channel 14 in subframe 1
bits : 14 - 13 (0 bit)
access : read-write
S1CH15 : This controls the enable/disable state of the channel 15 in subframe 1
bits : 15 - 14 (0 bit)
access : read-write
S1CH16 : This controls the enable/disable state of the channel 16 in subframe 1
bits : 16 - 15 (0 bit)
access : read-write
S1CH17 : This controls the enable/disable state of the channel 17 in subframe 1
bits : 17 - 16 (0 bit)
access : read-write
S1CH18 : This controls the enable/disable state of the channel 18 in subframe 1
bits : 18 - 17 (0 bit)
access : read-write
S1CH19 : This controls the enable/disable state of the channel 19 in subframe 1
bits : 19 - 18 (0 bit)
access : read-write
S1CH20 : This controls the enable/disable state of the channel 20 in subframe 1
bits : 20 - 19 (0 bit)
access : read-write
S1CH21 : This controls the enable/disable state of the channel 21 in subframe 1
bits : 21 - 20 (0 bit)
access : read-write
S1CH22 : This controls the enable/disable state of the channel 22 in subframe 1
bits : 22 - 21 (0 bit)
access : read-write
S1CH23 : This controls the enable/disable state of the channel 23 in subframe 1
bits : 23 - 22 (0 bit)
access : read-write
S1CH24 : This controls the enable/disable state of the channel 24 in subframe 1
bits : 24 - 23 (0 bit)
access : read-write
S1CH25 : This controls the enable/disable state of the channel 25 in subframe 1
bits : 25 - 24 (0 bit)
access : read-write
S1CH26 : This controls the enable/disable state of the channel 26 in subframe 1
bits : 26 - 25 (0 bit)
access : read-write
S1CH27 : This controls the enable/disable state of the channel 27 in subframe 1
bits : 27 - 26 (0 bit)
access : read-write
S1CH28 : This controls the enable/disable state of the channel 28 in subframe 1
bits : 28 - 27 (0 bit)
access : read-write
S1CH29 : This controls the enable/disable state of the channel 29 in subframe 1
bits : 29 - 28 (0 bit)
access : read-write
S1CH30 : This controls the enable/disable state of the channel 30 in subframe 1
bits : 30 - 29 (0 bit)
access : read-write
S1CH31 : This controls the enable/disable state of the channel 31 in subframe 1
bits : 31 - 30 (0 bit)
access : read-write
Operation Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : This enables or disables the I2S interface
bits : 0 - -1 (0 bit)
access : read-write
TXENB : This sets the enabled/disabled state of the transmit operation
bits : 16 - 15 (0 bit)
access : read-write
RXENB : This sets the enabled/disabled state of the receive operation
bits : 24 - 23 (0 bit)
access : read-write
Soft Reset Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRST : Soft reset bit
bits : 0 - -1 (0 bit)
access : read-write
Interrupt Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFTH : This bit sets the receive FIFO threshold value
bits : 0 - 2 (3 bit)
access : read-write
RPTMR : This is the bit for setting the packet receive completion timer
bits : 4 - 4 (1 bit)
access : read-write
TFTH : This bit sets the transmit FIFO threshold value
bits : 8 - 10 (3 bit)
access : read-write
RXFIM : This bit masks the receive FIFO interrupt
bits : 16 - 15 (0 bit)
access : read-write
RXFDM : This bit masks the receive DMA request
bits : 17 - 16 (0 bit)
access : read-write
EOPM : This bit masks the interrupts by EOPI of the STATUS register
bits : 18 - 17 (0 bit)
access : read-write
RXOVM : This bit masks the receive FIFO overflow interrupt
bits : 19 - 18 (0 bit)
access : read-write
RXUDM : This bit masks the receive FIFO underflow interrupt
bits : 20 - 19 (0 bit)
access : read-write
RBERM : This bit masks the receive channel block size error interrupt
bits : 21 - 20 (0 bit)
access : read-write
TXFIM : This bit masks the transmit FIFO interrupt
bits : 24 - 23 (0 bit)
access : read-write
TXFDM : This bit masks the transmit DMA request
bits : 25 - 24 (0 bit)
access : read-write
TXOVM : This bit masks the transmit FIFO overflow interrupt
bits : 26 - 25 (0 bit)
access : read-write
TXUD0M : This bit masks the transmit FIFO underflow interrupt
bits : 27 - 26 (0 bit)
access : read-write
FERRM : This bit masks the frame error interrupt mask
bits : 28 - 27 (0 bit)
access : read-write
TBERM : This bit masks the transmit channel block size error interrupt
bits : 29 - 28 (0 bit)
access : read-write
TXUD1M : This bit masks the transmit FIFO underflow interrupt
bits : 30 - 29 (0 bit)
access : read-write
Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNUM : This indicates the data count in the receive FIFO
bits : 0 - 6 (7 bit)
access : read-only
TXNUM : This indicates the data count in the transmit FIFO
bits : 8 - 14 (7 bit)
access : read-only
RXFI : This is set to 1 when the receive FIFO data count meets or exceeds the threshold value
bits : 16 - 15 (0 bit)
access : read-only
TXFI : This is set to 1 when the transmit FIFO empty slot meets or exceeds the threshold value
bits : 17 - 16 (0 bit)
access : read-only
BSY : This indicates the status of the serial transmit control unit
bits : 18 - 17 (0 bit)
access : read-only
EOPI : This is the interrupt flag based on the receive timer
bits : 19 - 18 (0 bit)
access : read-write
RXOVR : This is set to 1 when the receive FIFO overflows
bits : 24 - 23 (0 bit)
access : read-write
RXUDR : This is set to 1 when the receive FIFO underflows
bits : 25 - 24 (0 bit)
access : read-write
TXOVR : This is set to 1 when the transmit FIFO overflows
bits : 26 - 25 (0 bit)
access : read-write
TXUDR0 : This is set to 1 when the transmit FIFO underflows during frame transmission
bits : 27 - 26 (0 bit)
access : read-write
TXUDR1 : This is set to 1 when the transmit FIFO underflows at the frame start
bits : 28 - 27 (0 bit)
access : read-write
FERR : This indicates that a frame error has occurred
bits : 29 - 28 (0 bit)
access : read-write
RBERR : If the block size of the DMA receive channel is set to a value larger than the receive FIFO threshold value, this bit is set to 1.
bits : 30 - 29 (0 bit)
access : read-only
TBERR : If the block size of the DMA transmit channel is set to a value larger than the transmit FIFO threshold value, this bit is set to 1.
bits : 31 - 30 (0 bit)
access : read-only
DMA Startup Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDMACT : This bit is enabled when the same register RL1E0=0
bits : 0 - -1 (0 bit)
access : read-write
RL1E0 : This sets the operation mode of RXDREQ
bits : 8 - 7 (0 bit)
access : read-write
TDMACT : This bit is enabled when the same register TL1E0=0
bits : 16 - 15 (0 bit)
access : read-write
TL1E0 : This sets the operation mode of TXDREQ
bits : 24 - 23 (0 bit)
access : read-write
Test Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBMD : This sets the loopback mode
bits : 0 - -1 (0 bit)
access : read-write
Transmit FIFO Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDATA : As long as the transmit FIFO is not full, the words to be transmitted can be written.
bits : 0 - 30 (31 bit)
access : write-only
Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSPL : This sets the polarity of the I2SWS pin
bits : 0 - -1 (0 bit)
access : read-write
FSLN : This specifies the pulse width of I2SWS
bits : 1 - 0 (0 bit)
access : read-write
FSPH : This specifies the phase for I2SWS frame data
bits : 2 - 1 (0 bit)
access : read-write
CPOL : This specifies the I2SCK polarity where drive sampling of the serial data is performed
bits : 3 - 2 (0 bit)
access : read-write
SMPL : This specifies the point where data is sampled
bits : 4 - 3 (0 bit)
access : read-write
RXDIS : This enables or disables the receive function
bits : 5 - 4 (0 bit)
access : read-write
TXDIS : This enables or disables the transmit function
bits : 6 - 5 (0 bit)
access : read-write
MLSB : This sets word bit shift order
bits : 7 - 6 (0 bit)
access : read-write
FRUN : This sets the output mode of the frame sync signal
bits : 8 - 7 (0 bit)
access : read-write
BEXT : When the receive word length is smaller than the FIFO word length, this sets the upper bit extension mode.
bits : 9 - 8 (0 bit)
access : read-write
ECKM : In master mode, this selects the base clock divider.
bits : 10 - 9 (0 bit)
access : read-write
RHLL : This sets the FIFO word configuration to one or two words
bits : 11 - 10 (0 bit)
access : read-write
SBFN : This specifies the subframe configuration (number of subframes) of the frame
bits : 12 - 11 (0 bit)
access : read-write
MSMD : This sets master or slave mode.
bits : 13 - 12 (0 bit)
access : read-write
MSKB : This sets the serial output data of the invalid transmit frames
bits : 14 - 13 (0 bit)
access : read-write
OVHD : Following the valid data of the frame, it can insert OVERHEAD bits to enable adjustment of the frame rate.
bits : 16 - 24 (9 bit)
access : read-write
CKRT : When operating in master mode, this sets the clock division ratio for output.
bits : 26 - 30 (5 bit)
access : read-write
Channel Control Register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S0WDL : This sets the word length of the channels that make up subframe 1
bits : 0 - 3 (4 bit)
access : read-write
S0CHL : This sets the channel length of the channels that make up subframe 1
bits : 5 - 8 (4 bit)
access : read-write
S0CHN : This sets the number of channels for subframe 0
bits : 10 - 13 (4 bit)
access : read-write
S1WDL : This sets the word length of the channels that make up subframe 1
bits : 16 - 19 (4 bit)
access : read-write
S1CHL : This sets the channel length of the channels that make up subframe 1
bits : 21 - 24 (4 bit)
access : read-write
S1CHN : This sets the number of channels for subframe 1
bits : 26 - 29 (4 bit)
access : read-write
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