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HSSPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x34 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3E Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x35 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x39 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3A Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3B Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x90 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xD0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xD4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xD8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xDC Bytes (0x0)
size : 0x32 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xFC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x400 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x404 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MCTRL

PCC3

TXF

TXE

TXC

RXF

RXE

RXC

FAULTF

FAULTC

DMCFG

DMDMAEN

DMSTART

DMSTOP

DMPSEL

DMTRP

DMBCC

DMBCS

PCC0

DMSTATUS

QDCLKR

DBCNT

FIFOCFG

TXFIFO0

TXFIFO1

TXFIFO2

TXFIFO3

TXFIFO4

TXFIFO5

TXFIFO6

TXFIFO7

TXFIFO8

TXFIFO9

TXFIFO10

TXFIFO11

PCC1

TXFIFO12

TXFIFO13

TXFIFO14

TXFIFO15

RXFIFO0

RXFIFO1

RXFIFO2

RXFIFO3

RXFIFO4

RXFIFO5

RXFIFO6

RXFIFO7

RXFIFO8

RXFIFO9

RXFIFO10

RXFIFO11

PCC2

RXFIFO12

RXFIFO13

RXFIFO14

RXFIFO15

CSCFG

CSITIME

CSAEXT

RDCSDC0

RDCSDC1

RDCSDC2

RDCSDC3

RDCSDC4

RDCSDC5

RDCSDC6

RDCSDC7

WRCSDC0

WRCSDC1

WRCSDC2

WRCSDC3

WRCSDC4

WRCSDC5

WRCSDC6

WRCSDC7

MID


MCTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTRL MCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEN CSEN MES SYNCON

MEN : Module enable bit
bits : 0 - -1 (0 bit)
access : read-write

CSEN : Command sequencer mode enable bit
bits : 1 - 0 (0 bit)
access : read-write

MES : Module enable status bit
bits : 4 - 3 (0 bit)
access : read-only

SYNCON : Synchronizer circuit operation bit
bits : 5 - 4 (0 bit)
access : read-write


PCC3

Peripheral Communication Setting Registers 3
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC3 PCC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXF

Transmission Interrupt Factor Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXF TXF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFFS TFES TFOS TFUS TFLETS TFMTS TSSRS

TFFS : TX-FIFO full detection bit
bits : 0 - -1 (0 bit)
access : read-only

TFES : TX-FIFO and shift register empty detection bit
bits : 1 - 0 (0 bit)
access : read-only

TFOS : TX-FIFO overrun detection bit
bits : 2 - 1 (0 bit)
access : read-only

TFUS : TX-FIFO underrun detection bit
bits : 3 - 2 (0 bit)
access : read-only

TFLETS : TX-FIFO-less-than-or-equal-to-threshold detection bit
bits : 4 - 3 (0 bit)
access : read-only

TFMTS : TX-FIFO-exceeded-threshold detection bit
bits : 5 - 4 (0 bit)
access : read-only

TSSRS : Slave select released detection bit
bits : 6 - 5 (0 bit)
access : read-only


TXE

Transmission Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXE TXE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFFE TFEE TFOE TFUE TFLETE TFMTE TSSRE

TFFE : TX-FIFO full detection interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write

TFEE : TX-FIFO and shift register empty detection interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write

TFOE : TX-FIFO overrun detection interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write

TFUE : TX-FIFO underrun detection interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write

TFLETE : TX-FIFO-less-than-or-equal-to-threshold detection interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write

TFMTE : TX-FIFO-exceeded-threshold detection interrupt enable bit
bits : 5 - 4 (0 bit)
access : read-write

TSSRE : Slave select released detection interrupt enable bit
bits : 6 - 5 (0 bit)
access : read-write


TXC

Transmission Interrupt Clear Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXC TXC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFFC TFEC TFOC TFUC TFLETC TFMTC TSSRC

TFFC : TX-FIFO full detection clear bit
bits : 0 - -1 (0 bit)
access : write-only

TFEC : TX-FIFO and shift register empty detection clear bit
bits : 1 - 0 (0 bit)
access : write-only

TFOC : TX-FIFO overrun detection clear bit
bits : 2 - 1 (0 bit)
access : write-only

TFUC : TX-FIFO underrun detection clear bit
bits : 3 - 2 (0 bit)
access : write-only

TFLETC : TX-FIFO-less-than-or-equal-to-threshold detection clear bit
bits : 4 - 3 (0 bit)
access : write-only

TFMTC : TX-FIFO-exceeded-threshold detection clear bit
bits : 5 - 4 (0 bit)
access : write-only

TSSRC : Slave select released detection clear bit
bits : 6 - 5 (0 bit)
access : write-only


RXF

Reception Interrupt Factor Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXF RXF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFFS RFES RFOS RFUS RFLETS RFMTS RSSRS

RFFS : RX-FIFO full detection bit
bits : 0 - -1 (0 bit)
access : read-only

RFES : RX-FIFO empty detection bit
bits : 1 - 0 (0 bit)
access : read-only

RFOS : RX-FIFO overrun detection bit
bits : 2 - 1 (0 bit)
access : read-only

RFUS : RX-FIFO underrun detection bit
bits : 3 - 2 (0 bit)
access : read-only

RFLETS : RX-FIFO-less-than-or-equal-to-threshold detection bit
bits : 4 - 3 (0 bit)
access : read-only

RFMTS : RX-FIFO-exceeded-threshold detection bit
bits : 5 - 4 (0 bit)
access : read-only

RSSRS : Slave select released detection bit
bits : 6 - 5 (0 bit)
access : read-only


RXE

Reception Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXE RXE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFFE RFEE RFOE RFUE RFLETE RFMTE RSSRE

RFFE : RX-FIFO full detection interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write

RFEE : RX-FIFO and shift register empty-state detection interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write

RFOE : RX-FIFO overrun detection interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write

RFUE : RX-FIFO underrun detection interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write

RFLETE : RX-FIFO-less-than-or-equal-to-threshold detection interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write

RFMTE : RX-FIFO-exceeded-threshold detection interrupt enable bit
bits : 5 - 4 (0 bit)
access : read-write

RSSRE : Slave select released detection interrupt enable bit
bits : 6 - 5 (0 bit)
access : read-write


RXC

Interrupt Clear Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RXC RXC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFFC RFEC RFOC RFUC RFLETC RFMTC RSSRC

RFFC : RX-FIFO full detection clear bit
bits : 0 - -1 (0 bit)
access : write-only

RFEC : RX-FIFO and shift register empty-state detection clear bit
bits : 1 - 0 (0 bit)
access : write-only

RFOC : RX-FIFO overrun detection clear bit
bits : 2 - 1 (0 bit)
access : write-only

RFUC : RX-FIFO underrun detection clear bit
bits : 3 - 2 (0 bit)
access : write-only

RFLETC : RX-FIFO-less-than-or-equal-to-threshold detection clear bit
bits : 4 - 3 (0 bit)
access : write-only

RFMTC : RX-FIFO-exceeded-threshold detection clear bit
bits : 5 - 4 (0 bit)
access : write-only

RSSRC : Slave select released detection clear bit
bits : 6 - 5 (0 bit)
access : write-only


FAULTF

Fault Interrupt Factor Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FAULTF FAULTF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UMAFS WAFS PVFS DWCBSFS DRCBSFS

UMAFS : Unmapped memory access fault detection bit
bits : 0 - -1 (0 bit)
access : read-only

WAFS : Write access fault detection bit
bits : 1 - 0 (0 bit)
access : read-only

PVFS : Protection violation fault detection bit
bits : 2 - 1 (0 bit)
access : read-only

DWCBSFS : DWCBSFS
bits : 3 - 2 (0 bit)
access : read-only

DRCBSFS : DRCBSFS
bits : 4 - 3 (0 bit)
access : read-only


FAULTC

Fault Interrupt Clear Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FAULTC FAULTC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UMAFC WAFC PVFC DWCBSFC DRCBSFC

UMAFC : Unmapped memory access fault detection clear bit
bits : 0 - -1 (0 bit)
access : write-only

WAFC : Write access fault detection clear bit
bits : 1 - 0 (0 bit)
access : write-only

PVFC : Protection violation fault detection clear bit
bits : 2 - 1 (0 bit)
access : write-only

DWCBSFC : DWCBSFC
bits : 3 - 2 (0 bit)
access : write-only

DRCBSFC : DRCBSFC
bits : 4 - 3 (0 bit)
access : write-only


DMCFG

Direct Mode Setting Register
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMCFG DMCFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SSDC

SSDC : Slave select deassertion setting bit
bits : 1 - 0 (0 bit)
access : read-write


DMDMAEN

DMDMAEN
address_offset : 0x35 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMDMAEN DMDMAEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RXDMAEN TXDMAEN

RXDMAEN : RXDMAEN
bits : 0 - -1 (0 bit)
access : read-write

TXDMAEN : TXDMAEN
bits : 1 - 0 (0 bit)
access : read-write


DMSTART

Direct Mode Transfer Start Control Register
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMSTART DMSTART read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 START

START : Transfer start bit
bits : 0 - -1 (0 bit)
access : read-write


DMSTOP

Direct Mode Transfer Stop Control Register
address_offset : 0x39 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMSTOP DMSTOP read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STOP

STOP : Transfer stop bit
bits : 0 - -1 (0 bit)
access : read-write


DMPSEL

Direct Mode Slave Select Register
address_offset : 0x3A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMPSEL DMPSEL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PSEL

PSEL : Peripheral select bits
bits : 0 - 0 (1 bit)
access : read-write


DMTRP

Direct Mode Transfer Protocol Setting Register
address_offset : 0x3B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMTRP DMTRP read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRP

TRP : Transfer protocol setting bits
bits : 0 - 2 (3 bit)
access : read-write


DMBCC

Direct Mode Transfer Byte Count Setting Register
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMBCC DMBCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCC

BCC : Transferred byte count setting value
bits : 0 - 14 (15 bit)
access : read-write


DMBCS

Direct Mode Transfer Remaining Count Register
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMBCS DMBCS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCS

BCS : Number of remaining bytes to transfer
bits : 0 - 14 (15 bit)
access : read-only


PCC0

Peripheral Communication Setting Register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC0 PCC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPHA CPOL ACES RTM SSPOL SS2CD SDIR SENDIAN CDRS SAFESYNC WRDSEL RDDSEL

CPHA : Clock phase setting bit
bits : 0 - -1 (0 bit)
access : read-write

CPOL : Serial clock polarity setting bit
bits : 1 - 0 (0 bit)
access : read-write

ACES : Serial data transmission/reception timing setting bit
bits : 2 - 1 (0 bit)
access : read-write

RTM : Timing compensation setting bit
bits : 3 - 2 (0 bit)
access : read-write

SSPOL : Slave select polarity setting bit
bits : 4 - 3 (0 bit)
access : read-write

SS2CD : Slave-select-to-clock-start delay time setting bit
bits : 5 - 5 (1 bit)
access : read-write

SDIR : Shift direction setting bit
bits : 7 - 6 (0 bit)
access : read-write

SENDIAN : Endian setting bit
bits : 8 - 7 (0 bit)
access : read-write

CDRS : Clock division ratio setting bits
bits : 9 - 14 (6 bit)
access : read-write

SAFESYNC : Safe synchronization bit
bits : 16 - 15 (0 bit)
access : read-write

WRDSEL : Write or different command deselect time setting bits
bits : 17 - 19 (3 bit)
access : read-write

RDDSEL : Read deselect time setting bits
bits : 21 - 21 (1 bit)
access : read-write


DMSTATUS

Direct Mode Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMSTATUS DMSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXACTIVE TXACTIVE RXFLEVEL TXFLEVEL

RXACTIVE : Reception status bit
bits : 0 - -1 (0 bit)
access : read-only

TXACTIVE : Transmission status bit
bits : 1 - 0 (0 bit)
access : read-only

RXFLEVEL : Remaining RX-FIFO data indication bits
bits : 8 - 11 (4 bit)
access : read-only

TXFLEVEL : Remaining TX-FIFO data indication bits
bits : 16 - 19 (4 bit)
access : read-only


QDCLKR

QDCLKR
address_offset : 0x400 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QDCLKR QDCLKR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 QHDIV

QHDIV : QHDIV
bits : 0 - 2 (3 bit)
access : read-write


DBCNT

DBCNT
address_offset : 0x404 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBCNT DBCNT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RXDBEN TXDBEN

RXDBEN : RXDBEN
bits : 0 - -1 (0 bit)
access : read-write

TXDBEN : TXDBEN
bits : 1 - 0 (0 bit)
access : read-write


FIFOCFG

FIFO Setting Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFOCFG FIFOCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFTH TXFTH FWIDTH TXCTRL RXFLSH TXFLSH

RXFTH : RX-FIFO threshold
bits : 0 - 2 (3 bit)
access : read-write

TXFTH : TX-FIFO threshold
bits : 4 - 6 (3 bit)
access : read-write

FWIDTH : FIFO bit width setting value
bits : 8 - 8 (1 bit)
access : read-write

TXCTRL : TX-FIFO transmission data control bit
bits : 10 - 9 (0 bit)
access : read-write

RXFLSH : RX-FIFO clear bit
bits : 11 - 10 (0 bit)
access : write-only

TXFLSH : TX-FIFO clear bit
bits : 12 - 11 (0 bit)
access : write-only


TXFIFO0

TX-FIFO0 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXFIFO0 TXFIFO0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : TX-FIFO0 write data
bits : 0 - 30 (31 bit)
access : write-only


TXFIFO1

TX-FIFO1 Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO1 TXFIFO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFIFO2

TX-FIFO2 Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO2 TXFIFO2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFIFO3

TX-FIFO3 Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO3 TXFIFO3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFIFO4

TX-FIFO4 Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO4 TXFIFO4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFIFO5

TX-FIFO5 Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO5 TXFIFO5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFIFO6

TX-FIFO6 Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO6 TXFIFO6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFIFO7

TX-FIFO7 Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO7 TXFIFO7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFIFO8

TX-FIFO8 Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO8 TXFIFO8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFIFO9

TX-FIFO9 Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO9 TXFIFO9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFIFO10

TX-FIFO10 Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO10 TXFIFO10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFIFO11

TX-FIFO11 Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO11 TXFIFO11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCC1

Peripheral Communication Setting Registers 1
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC1 PCC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFIFO12

TX-FIFO12 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO12 TXFIFO12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFIFO13

TX-FIFO13 Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO13 TXFIFO13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFIFO14

TX-FIFO14 Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO14 TXFIFO14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFIFO15

TX-FIFO15 Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFO15 TXFIFO15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO0

RX-FIFO0 Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXFIFO0 RXFIFO0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : RX-FIFO0 read data
bits : 0 - 30 (31 bit)
access : read-only


RXFIFO1

RX-FIFO1 read data
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO1 RXFIFO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO2

RX-FIFO2 read data
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO2 RXFIFO2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO3

RX-FIFO3 read data
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO3 RXFIFO3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO4

RX-FIFO4 read data
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO4 RXFIFO4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO5

RX-FIFO5 read data
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO5 RXFIFO5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO6

RX-FIFO6 read data
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO6 RXFIFO6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO7

RX-FIFO7 read data
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO7 RXFIFO7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO8

RX-FIFO8 read data
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO8 RXFIFO8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO9

RX-FIFO9 read data
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO9 RXFIFO9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO10

RX-FIFO10 read data
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO10 RXFIFO10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO11

RX-FIFO11 read data
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO11 RXFIFO11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCC2

Peripheral Communication Setting Registers 2
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC2 PCC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO12

RX-FIFO12 read data
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO12 RXFIFO12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO13

RX-FIFO13 read data
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO13 RXFIFO13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO14

RX-FIFO14 read data
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO14 RXFIFO14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFO15

RX-FIFO15 read data
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO15 RXFIFO15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CSCFG

32
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSCFG CSCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRAM MBM SSEL0EN SSEL1EN SSEL2EN SSEL3EN MSEL

SRAM : Readable/Writable or Read only selection bit
bits : 0 - -1 (0 bit)
access : read-write

MBM : SPI data width setting bits
bits : 1 - 1 (1 bit)
access : read-write

SSEL0EN : Slave select 0 enable bit
bits : 8 - 7 (0 bit)
access : read-write

SSEL1EN : Slave select 1 enable bit
bits : 9 - 8 (0 bit)
access : read-write

SSEL2EN : Slave select 2 enable bit
bits : 10 - 9 (0 bit)
access : read-write

SSEL3EN : Slave select 3 enable bit
bits : 11 - 10 (0 bit)
access : read-write

MSEL : Memory device selection bits
bits : 16 - 18 (3 bit)
access : read-write


CSITIME

Command Sequencer Idle Timer Setting Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSITIME CSITIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITIME

ITIME : Idle timer setting value
bits : 0 - 14 (15 bit)
access : read-write


CSAEXT

Command Sequencer Address Extension Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSAEXT CSAEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AEXT

AEXT : Address extension bits
bits : 13 - 30 (18 bit)
access : read-write


RDCSDC0

Read Command Sequence Data/Control Register 0
address_offset : 0xDC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDCSDC0 RDCSDC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEC TRP CONT RDCSDATA

DEC : Decode control bit
bits : 0 - -1 (0 bit)
access : read-write

TRP : Serial interface width control bits
bits : 1 - 1 (1 bit)
access : read-write

CONT : Continuous instruction setting bit
bits : 3 - 2 (0 bit)
access : read-write

RDCSDATA : Read command sequencer data/control setting values
bits : 8 - 14 (7 bit)
access : read-write


RDCSDC1

Read Command Sequence Data/Control Register 1
address_offset : 0xDE Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDCSDC1 RDCSDC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDCSDC2

Read Command Sequence Data/Control Register 2
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDCSDC2 RDCSDC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDCSDC3

Read Command Sequence Data/Control Register 3
address_offset : 0xE2 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDCSDC3 RDCSDC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDCSDC4

Read Command Sequence Data/Control Register 4
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDCSDC4 RDCSDC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDCSDC5

Read Command Sequence Data/Control Register 5
address_offset : 0xE6 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDCSDC5 RDCSDC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDCSDC6

Read Command Sequence Data/Control Register 6
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDCSDC6 RDCSDC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDCSDC7

Read Command Sequence Data/Control Register 7
address_offset : 0xEA Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDCSDC7 RDCSDC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WRCSDC0

Write Command Sequence Data/Control Register 0
address_offset : 0xEC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRCSDC0 WRCSDC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEC TRP CONT WRCSDATA

DEC : Decode control bit
bits : 0 - -1 (0 bit)
access : read-write

TRP : Serial interface width control bits
bits : 1 - 1 (1 bit)
access : read-write

CONT : Continuous instruction setting bit
bits : 3 - 2 (0 bit)
access : read-write

WRCSDATA : Write command sequencer data/control setting values
bits : 8 - 14 (7 bit)
access : read-write


WRCSDC1

Write Command Sequence Data/Control Register 1
address_offset : 0xEE Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRCSDC1 WRCSDC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WRCSDC2

Write Command Sequence Data/Control Register 2
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRCSDC2 WRCSDC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WRCSDC3

Write Command Sequence Data/Control Register 3
address_offset : 0xF2 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRCSDC3 WRCSDC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WRCSDC4

Write Command Sequence Data/Control Register 4
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRCSDC4 WRCSDC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WRCSDC5

Write Command Sequence Data/Control Register 5
address_offset : 0xF6 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRCSDC5 WRCSDC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WRCSDC6

Write Command Sequence Data/Control Register 6
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRCSDC6 WRCSDC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WRCSDC7

Write Command Sequence Data/Control Register 7
address_offset : 0xFA Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRCSDC7 WRCSDC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MID

Module Identification Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MID MID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MID

MID : Module identification information bits
bits : 0 - 30 (31 bit)
access : read-only



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