\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x38 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3E Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x35 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x39 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3A Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3B Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x90 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xDC Bytes (0x0)
size : 0x32 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xFC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x400 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x404 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEN : Module enable bit
bits : 0 - -1 (0 bit)
access : read-write
CSEN : Command sequencer mode enable bit
bits : 1 - 0 (0 bit)
access : read-write
MES : Module enable status bit
bits : 4 - 3 (0 bit)
access : read-only
SYNCON : Synchronizer circuit operation bit
bits : 5 - 4 (0 bit)
access : read-write
Peripheral Communication Setting Registers 3
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Transmission Interrupt Factor Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TFFS : TX-FIFO full detection bit
bits : 0 - -1 (0 bit)
access : read-only
TFES : TX-FIFO and shift register empty detection bit
bits : 1 - 0 (0 bit)
access : read-only
TFOS : TX-FIFO overrun detection bit
bits : 2 - 1 (0 bit)
access : read-only
TFUS : TX-FIFO underrun detection bit
bits : 3 - 2 (0 bit)
access : read-only
TFLETS : TX-FIFO-less-than-or-equal-to-threshold detection bit
bits : 4 - 3 (0 bit)
access : read-only
TFMTS : TX-FIFO-exceeded-threshold detection bit
bits : 5 - 4 (0 bit)
access : read-only
TSSRS : Slave select released detection bit
bits : 6 - 5 (0 bit)
access : read-only
Transmission Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFFE : TX-FIFO full detection interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write
TFEE : TX-FIFO and shift register empty detection interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write
TFOE : TX-FIFO overrun detection interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write
TFUE : TX-FIFO underrun detection interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write
TFLETE : TX-FIFO-less-than-or-equal-to-threshold detection interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write
TFMTE : TX-FIFO-exceeded-threshold detection interrupt enable bit
bits : 5 - 4 (0 bit)
access : read-write
TSSRE : Slave select released detection interrupt enable bit
bits : 6 - 5 (0 bit)
access : read-write
Transmission Interrupt Clear Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TFFC : TX-FIFO full detection clear bit
bits : 0 - -1 (0 bit)
access : write-only
TFEC : TX-FIFO and shift register empty detection clear bit
bits : 1 - 0 (0 bit)
access : write-only
TFOC : TX-FIFO overrun detection clear bit
bits : 2 - 1 (0 bit)
access : write-only
TFUC : TX-FIFO underrun detection clear bit
bits : 3 - 2 (0 bit)
access : write-only
TFLETC : TX-FIFO-less-than-or-equal-to-threshold detection clear bit
bits : 4 - 3 (0 bit)
access : write-only
TFMTC : TX-FIFO-exceeded-threshold detection clear bit
bits : 5 - 4 (0 bit)
access : write-only
TSSRC : Slave select released detection clear bit
bits : 6 - 5 (0 bit)
access : write-only
Reception Interrupt Factor Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFFS : RX-FIFO full detection bit
bits : 0 - -1 (0 bit)
access : read-only
RFES : RX-FIFO empty detection bit
bits : 1 - 0 (0 bit)
access : read-only
RFOS : RX-FIFO overrun detection bit
bits : 2 - 1 (0 bit)
access : read-only
RFUS : RX-FIFO underrun detection bit
bits : 3 - 2 (0 bit)
access : read-only
RFLETS : RX-FIFO-less-than-or-equal-to-threshold detection bit
bits : 4 - 3 (0 bit)
access : read-only
RFMTS : RX-FIFO-exceeded-threshold detection bit
bits : 5 - 4 (0 bit)
access : read-only
RSSRS : Slave select released detection bit
bits : 6 - 5 (0 bit)
access : read-only
Reception Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFFE : RX-FIFO full detection interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write
RFEE : RX-FIFO and shift register empty-state detection interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write
RFOE : RX-FIFO overrun detection interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write
RFUE : RX-FIFO underrun detection interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write
RFLETE : RX-FIFO-less-than-or-equal-to-threshold detection interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write
RFMTE : RX-FIFO-exceeded-threshold detection interrupt enable bit
bits : 5 - 4 (0 bit)
access : read-write
RSSRE : Slave select released detection interrupt enable bit
bits : 6 - 5 (0 bit)
access : read-write
Interrupt Clear Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RFFC : RX-FIFO full detection clear bit
bits : 0 - -1 (0 bit)
access : write-only
RFEC : RX-FIFO and shift register empty-state detection clear bit
bits : 1 - 0 (0 bit)
access : write-only
RFOC : RX-FIFO overrun detection clear bit
bits : 2 - 1 (0 bit)
access : write-only
RFUC : RX-FIFO underrun detection clear bit
bits : 3 - 2 (0 bit)
access : write-only
RFLETC : RX-FIFO-less-than-or-equal-to-threshold detection clear bit
bits : 4 - 3 (0 bit)
access : write-only
RFMTC : RX-FIFO-exceeded-threshold detection clear bit
bits : 5 - 4 (0 bit)
access : write-only
RSSRC : Slave select released detection clear bit
bits : 6 - 5 (0 bit)
access : write-only
Fault Interrupt Factor Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UMAFS : Unmapped memory access fault detection bit
bits : 0 - -1 (0 bit)
access : read-only
WAFS : Write access fault detection bit
bits : 1 - 0 (0 bit)
access : read-only
PVFS : Protection violation fault detection bit
bits : 2 - 1 (0 bit)
access : read-only
DWCBSFS : DWCBSFS
bits : 3 - 2 (0 bit)
access : read-only
DRCBSFS : DRCBSFS
bits : 4 - 3 (0 bit)
access : read-only
Fault Interrupt Clear Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UMAFC : Unmapped memory access fault detection clear bit
bits : 0 - -1 (0 bit)
access : write-only
WAFC : Write access fault detection clear bit
bits : 1 - 0 (0 bit)
access : write-only
PVFC : Protection violation fault detection clear bit
bits : 2 - 1 (0 bit)
access : write-only
DWCBSFC : DWCBSFC
bits : 3 - 2 (0 bit)
access : write-only
DRCBSFC : DRCBSFC
bits : 4 - 3 (0 bit)
access : write-only
Direct Mode Setting Register
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSDC : Slave select deassertion setting bit
bits : 1 - 0 (0 bit)
access : read-write
DMDMAEN
address_offset : 0x35 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDMAEN : RXDMAEN
bits : 0 - -1 (0 bit)
access : read-write
TXDMAEN : TXDMAEN
bits : 1 - 0 (0 bit)
access : read-write
Direct Mode Transfer Start Control Register
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Transfer start bit
bits : 0 - -1 (0 bit)
access : read-write
Direct Mode Transfer Stop Control Register
address_offset : 0x39 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOP : Transfer stop bit
bits : 0 - -1 (0 bit)
access : read-write
Direct Mode Slave Select Register
address_offset : 0x3A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSEL : Peripheral select bits
bits : 0 - 0 (1 bit)
access : read-write
Direct Mode Transfer Protocol Setting Register
address_offset : 0x3B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRP : Transfer protocol setting bits
bits : 0 - 2 (3 bit)
access : read-write
Direct Mode Transfer Byte Count Setting Register
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCC : Transferred byte count setting value
bits : 0 - 14 (15 bit)
access : read-write
Direct Mode Transfer Remaining Count Register
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BCS : Number of remaining bytes to transfer
bits : 0 - 14 (15 bit)
access : read-only
Peripheral Communication Setting Register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPHA : Clock phase setting bit
bits : 0 - -1 (0 bit)
access : read-write
CPOL : Serial clock polarity setting bit
bits : 1 - 0 (0 bit)
access : read-write
ACES : Serial data transmission/reception timing setting bit
bits : 2 - 1 (0 bit)
access : read-write
RTM : Timing compensation setting bit
bits : 3 - 2 (0 bit)
access : read-write
SSPOL : Slave select polarity setting bit
bits : 4 - 3 (0 bit)
access : read-write
SS2CD : Slave-select-to-clock-start delay time setting bit
bits : 5 - 5 (1 bit)
access : read-write
SDIR : Shift direction setting bit
bits : 7 - 6 (0 bit)
access : read-write
SENDIAN : Endian setting bit
bits : 8 - 7 (0 bit)
access : read-write
CDRS : Clock division ratio setting bits
bits : 9 - 14 (6 bit)
access : read-write
SAFESYNC : Safe synchronization bit
bits : 16 - 15 (0 bit)
access : read-write
WRDSEL : Write or different command deselect time setting bits
bits : 17 - 19 (3 bit)
access : read-write
RDDSEL : Read deselect time setting bits
bits : 21 - 21 (1 bit)
access : read-write
Direct Mode Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXACTIVE : Reception status bit
bits : 0 - -1 (0 bit)
access : read-only
TXACTIVE : Transmission status bit
bits : 1 - 0 (0 bit)
access : read-only
RXFLEVEL : Remaining RX-FIFO data indication bits
bits : 8 - 11 (4 bit)
access : read-only
TXFLEVEL : Remaining TX-FIFO data indication bits
bits : 16 - 19 (4 bit)
access : read-only
QDCLKR
address_offset : 0x400 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QHDIV : QHDIV
bits : 0 - 2 (3 bit)
access : read-write
DBCNT
address_offset : 0x404 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDBEN : RXDBEN
bits : 0 - -1 (0 bit)
access : read-write
TXDBEN : TXDBEN
bits : 1 - 0 (0 bit)
access : read-write
FIFO Setting Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFTH : RX-FIFO threshold
bits : 0 - 2 (3 bit)
access : read-write
TXFTH : TX-FIFO threshold
bits : 4 - 6 (3 bit)
access : read-write
FWIDTH : FIFO bit width setting value
bits : 8 - 8 (1 bit)
access : read-write
TXCTRL : TX-FIFO transmission data control bit
bits : 10 - 9 (0 bit)
access : read-write
RXFLSH : RX-FIFO clear bit
bits : 11 - 10 (0 bit)
access : write-only
TXFLSH : TX-FIFO clear bit
bits : 12 - 11 (0 bit)
access : write-only
TX-FIFO0 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX-FIFO0 write data
bits : 0 - 30 (31 bit)
access : write-only
TX-FIFO1 Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX-FIFO2 Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX-FIFO3 Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX-FIFO4 Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX-FIFO5 Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX-FIFO6 Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX-FIFO7 Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX-FIFO8 Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX-FIFO9 Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX-FIFO10 Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX-FIFO11 Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Peripheral Communication Setting Registers 1
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX-FIFO12 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX-FIFO13 Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX-FIFO14 Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX-FIFO15 Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO0 Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX-FIFO0 read data
bits : 0 - 30 (31 bit)
access : read-only
RX-FIFO1 read data
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO2 read data
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO3 read data
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO4 read data
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO5 read data
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO6 read data
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO7 read data
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO8 read data
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO9 read data
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO10 read data
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO11 read data
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Peripheral Communication Setting Registers 2
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO12 read data
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO13 read data
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO14 read data
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX-FIFO15 read data
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
32
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM : Readable/Writable or Read only selection bit
bits : 0 - -1 (0 bit)
access : read-write
MBM : SPI data width setting bits
bits : 1 - 1 (1 bit)
access : read-write
SSEL0EN : Slave select 0 enable bit
bits : 8 - 7 (0 bit)
access : read-write
SSEL1EN : Slave select 1 enable bit
bits : 9 - 8 (0 bit)
access : read-write
SSEL2EN : Slave select 2 enable bit
bits : 10 - 9 (0 bit)
access : read-write
SSEL3EN : Slave select 3 enable bit
bits : 11 - 10 (0 bit)
access : read-write
MSEL : Memory device selection bits
bits : 16 - 18 (3 bit)
access : read-write
Command Sequencer Idle Timer Setting Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITIME : Idle timer setting value
bits : 0 - 14 (15 bit)
access : read-write
Command Sequencer Address Extension Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AEXT : Address extension bits
bits : 13 - 30 (18 bit)
access : read-write
Read Command Sequence Data/Control Register 0
address_offset : 0xDC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEC : Decode control bit
bits : 0 - -1 (0 bit)
access : read-write
TRP : Serial interface width control bits
bits : 1 - 1 (1 bit)
access : read-write
CONT : Continuous instruction setting bit
bits : 3 - 2 (0 bit)
access : read-write
RDCSDATA : Read command sequencer data,ontrol setting values
bits : 8 - 14 (7 bit)
access : read-write
Read Command Sequence Data/Control Register 1
address_offset : 0xDE Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read Command Sequence Data/Control Register 2
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read Command Sequence Data/Control Register 3
address_offset : 0xE2 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read Command Sequence Data/Control Register 4
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read Command Sequence Data/Control Register 5
address_offset : 0xE6 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read Command Sequence Data/Control Register 6
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Read Command Sequence Data/Control Register 7
address_offset : 0xEA Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Write Command Sequence Data/Control Register 0
address_offset : 0xEC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEC : Decode control bit
bits : 0 - -1 (0 bit)
access : read-write
TRP : Serial interface width control bits
bits : 1 - 1 (1 bit)
access : read-write
CONT : Continuous instruction setting bit
bits : 3 - 2 (0 bit)
access : read-write
WRCSDATA : Write command sequencer data,ontrol setting values
bits : 8 - 14 (7 bit)
access : read-write
Write Command Sequence Data/Control Register 1
address_offset : 0xEE Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Write Command Sequence Data/Control Register 2
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Write Command Sequence Data/Control Register 3
address_offset : 0xF2 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Write Command Sequence Data/Control Register 4
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Write Command Sequence Data/Control Register 5
address_offset : 0xF6 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Write Command Sequence Data/Control Register 6
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Write Command Sequence Data/Control Register 7
address_offset : 0xFA Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Module Identification Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MID : Module identification information bits
bits : 0 - 30 (31 bit)
access : read-only
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