\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x88 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x13C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x148 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x44 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x48 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x58 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x5C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x78 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x7C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x84 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x104 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x108 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x140 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
Lock Protection Setting register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LockUnlock : Protection key of this address block setting bits
bits : 0 - 30 (31 bit)
access : write-only
VRAM ECC error interrupt enable/disable register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VramInterruptEnableSec0 : Interrupt control of VRAM ECC error for VRAM port0
bits : 0 - -1 (0 bit)
access : read-write
VramInterruptEnableSec1 : Interrupt control of VRAM ECC error for VRAM port1
bits : 1 - 0 (0 bit)
access : read-write
VRAM LockUnlock Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
vram_LockUnlock : $
bits : 0 - 30 (31 bit)
access : read-write
$
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
vram_LockStatus : Current status of lock protection
bits : 0 - -1 (0 bit)
access : read-only
vram_PrivilegeStatus : Current status of previlege protection
bits : 4 - 3 (0 bit)
access : read-only
vram_FreezeStatus : Current status of freeze status
bits : 8 - 7 (0 bit)
access : read-only
Size of the ECC protected memory region selection register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
vram_sram_select : Selects the size of the ECC protected region
bits : 0 - 10 (11 bit)
access : read-write
GDC bus address of the read access at S0 interface which had a single-bit ECC error
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
vram_aberraddr_s0 : Indicates address which had an ECC single bit error
bits : 0 - 30 (31 bit)
access : read-only
GDC bus address of the read access at S1 interface which had a single-bit ECC error
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
vram_aberraddr_s1 : Indicates address which had an ECC single bit error
bits : 0 - 30 (31 bit)
access : read-only
Register assigns fixed arbitration priorities to each GDC bus slave interface
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
vram_priority_s0_write : set priority of S0 interface for write
bits : 0 - 0 (1 bit)
access : read-write
vram_priority_s0_read : set priority of S0 interface for read
bits : 2 - 2 (1 bit)
access : read-write
vram_priority_s1_read : set priority of S1 interface for read
bits : 4 - 4 (1 bit)
access : read-write
vram_priority_s2_read : for internal device test purpose
bits : 6 - 6 (1 bit)
access : read-write
VRAM ECC error interrupt clear register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
VramInterruptClearSec0 : Clear interrupt of VRAM ECC error for VRAM port0
bits : 0 - -1 (0 bit)
access : write-only
VramInterruptClearSec1 : Clear interrupt of VRAM ECC error for VRAM port1
bits : 1 - 0 (0 bit)
access : write-only
VRAM ECC error interrupt status register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VramInterruptStatusSec0 : Indicator of VRAM Interrupt status for VRAM port0
bits : 0 - -1 (0 bit)
access : read-only
VramInterruptStatusSec1 : Indicator of VRAM Interrupt status for VRAM port1
bits : 1 - 0 (0 bit)
access : read-only
External Flash Device Selection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ExtFlashDevSelect : External memory device selection bit
bits : 0 - -1 (0 bit)
access : read-write
VRAM Remap Mode Disable register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VramRemapDisable : VRAM address remap or non-remap selection bit
bits : 0 - -1 (0 bit)
access : read-write
Panic display mode switch register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PanicSwitch : Panic display mode or Normal display mode selection bit
bits : 0 - -1 (0 bit)
access : read-write
GDC Clock Generation Control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GDCClockSelect : GDC clock generation control bits
bits : 8 - 22 (15 bit)
access : read-write
CPU wake-up trigger Mask register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WtrigMaskGe : Wake up trigger mask for GDC Core
bits : 0 - 17 (18 bit)
access : read-write
WtrigMaskQspi : Wake up trigger mask for QSPI interface
bits : 24 - 23 (0 bit)
access : read-write
WtrigMaskSdram : Wake up trigger mask for SDRAM interface
bits : 25 - 24 (0 bit)
access : read-write
WtrigMaskRpc : Wake up trigger mask for HyperBus interface
bits : 26 - 25 (0 bit)
access : read-write
Clock Domain Status Indication register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DspClockDomainReady : Clock Status of Display clock domain
bits : 0 - -1 (0 bit)
access : read-write
SdramClockDomainReady : Clcok Status of SDRAM interface clock domain
bits : 1 - 0 (0 bit)
access : read-write
RpcClockDomainReady : Clock Status of HyperBus interface clock domain
bits : 2 - 1 (0 bit)
access : read-write
HsspiClockDomainReady : Clock Status of QSPI interface clock domain
bits : 3 - 2 (0 bit)
access : read-write
Lock Protection Status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LockStatus : Current status of lock protection
bits : 0 - -1 (0 bit)
access : read-only
PrivilegeStatus : Current status of privilege protection
bits : 4 - 3 (0 bit)
access : read-only
FreezStatus : Current status of freeze status
bits : 8 - 7 (0 bit)
access : read-only
Display LockUnlock register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
dsp_LockUnlock : Protection key of this address block setting bits
bits : 0 - 30 (31 bit)
access : write-only
Display Lock Status indication register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
dsp_LockStatus : 0
bits : 0 - -1 (0 bit)
access : read-only
dsp_PrivilegeStatus : Current status of provilege protection
bits : 4 - 3 (0 bit)
access : read-only
dsp_FreezeStatus : Current status of freeze status
bits : 8 - 7 (0 bit)
access : read-only
Display Clock Divider Ration Setting Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dsp0_ClockDivider : Division ration from the Reference clock for peripherals
bits : 8 - 22 (15 bit)
access : read-write
Display clock domain control register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dsp0_ClockEnable : Display clock output control
bits : 0 - -1 (0 bit)
access : read-write
dsp0_SoftwareReset : Display clock domain software reset
bits : 16 - 15 (0 bit)
access : read-write
Register for display clock shift
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
dsp0_ClockInvert : Display clock polarity setting bit
bits : 0 - -1 (0 bit)
access : read-write
dsp0_ClockOffset : Display clock phase setting bits
bits : 16 - 22 (7 bit)
access : read-write
Register for display Power Enable Signal Control
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Power_Enable : Power control of external TFT panel setting bit
bits : 0 - -1 (0 bit)
access : read-write
Display Clock Gate Mode Protection Control register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LockUnlock : Protection of this address block setting bits
bits : 0 - 30 (31 bit)
access : read-write
Display Clock Gate Control register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ClockGate_Enable : Dot clock for external TFT panel control bit
bits : 0 - -1 (0 bit)
access : read-write
Division Ratio of SDRAM interface setting register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDRAMC_ClockDivider : Division ratio from the Reference clock for peripherals
bits : 8 - 22 (15 bit)
access : read-write
SDRAM interface clock domain setting register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDRAMC_ClockEnable : SDRAM interface clock output control
bits : 0 - -1 (0 bit)
access : read-write
SDRAMC_SoftwareReset : Software reset for SDRAM interface clock domain
bits : 16 - 15 (0 bit)
access : read-write
Division Ratio of QSPI interface setting register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSSPIC_ClockDivider : Division Ratio from the Reference clock for peripherals
bits : 8 - 22 (15 bit)
access : read-write
QSPI interface clock domain setting register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSSPIC_ClockEnable : QSPI interface clock output control
bits : 0 - -1 (0 bit)
access : read-write
HSSPIC_SoftwareReset : Software reset for QSPI interface clock domain
bits : 16 - 15 (0 bit)
access : read-write
Division Ratio of HyperBus interface setting register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPCC_ClockDivider : Division Ratio from the Reference clock for peripherals
bits : 0 - 1 (2 bit)
access : read-write
HyperBus interface clock domain setting register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPCC_ClockEnable : HyperBus interface clock output control
bits : 0 - -1 (0 bit)
access : read-write
CONFIG Clock control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ConfigClockSelect : CONFIG Clock division ratio setting bits
bits : 0 - 1 (2 bit)
access : read-write
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