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USB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EP0R

EP4R

EP5R

EP6R

EP7R

EP1R

CNTR

ISTR

FNR

DADDR

BTABLE

LPMCSR

BCDR

EP2R

EP3R


EP0R

endpoint register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP0R EP0R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EPTYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : EA
bits : 0 - 3 (4 bit)

STAT_TX : STAT_TX
bits : 4 - 5 (2 bit)

DTOG_TX : DTOG_TX
bits : 6 - 6 (1 bit)

CTR_TX : CTR_TX
bits : 7 - 7 (1 bit)

EP_KIND : EP_KIND
bits : 8 - 8 (1 bit)

EPTYPE : EPTYPE
bits : 9 - 10 (2 bit)

SETUP : SETUP
bits : 11 - 11 (1 bit)

STAT_RX : STAT_RX
bits : 12 - 13 (2 bit)

DTOG_RX : DTOG_RX
bits : 14 - 14 (1 bit)

CTR_RX : CTR_RX
bits : 15 - 15 (1 bit)


EP4R

endpoint register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP4R EP4R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EPTYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : EA
bits : 0 - 3 (4 bit)

STAT_TX : STAT_TX
bits : 4 - 5 (2 bit)

DTOG_TX : DTOG_TX
bits : 6 - 6 (1 bit)

CTR_TX : CTR_TX
bits : 7 - 7 (1 bit)

EP_KIND : EP_KIND
bits : 8 - 8 (1 bit)

EPTYPE : EPTYPE
bits : 9 - 10 (2 bit)

SETUP : SETUP
bits : 11 - 11 (1 bit)

STAT_RX : STAT_RX
bits : 12 - 13 (2 bit)

DTOG_RX : DTOG_RX
bits : 14 - 14 (1 bit)

CTR_RX : CTR_RX
bits : 15 - 15 (1 bit)


EP5R

endpoint register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP5R EP5R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EPTYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : EA
bits : 0 - 3 (4 bit)

STAT_TX : STAT_TX
bits : 4 - 5 (2 bit)

DTOG_TX : DTOG_TX
bits : 6 - 6 (1 bit)

CTR_TX : CTR_TX
bits : 7 - 7 (1 bit)

EP_KIND : EP_KIND
bits : 8 - 8 (1 bit)

EPTYPE : EPTYPE
bits : 9 - 10 (2 bit)

SETUP : SETUP
bits : 11 - 11 (1 bit)

STAT_RX : STAT_RX
bits : 12 - 13 (2 bit)

DTOG_RX : DTOG_RX
bits : 14 - 14 (1 bit)

CTR_RX : CTR_RX
bits : 15 - 15 (1 bit)


EP6R

endpoint register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP6R EP6R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EPTYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : EA
bits : 0 - 3 (4 bit)

STAT_TX : STAT_TX
bits : 4 - 5 (2 bit)

DTOG_TX : DTOG_TX
bits : 6 - 6 (1 bit)

CTR_TX : CTR_TX
bits : 7 - 7 (1 bit)

EP_KIND : EP_KIND
bits : 8 - 8 (1 bit)

EPTYPE : EPTYPE
bits : 9 - 10 (2 bit)

SETUP : SETUP
bits : 11 - 11 (1 bit)

STAT_RX : STAT_RX
bits : 12 - 13 (2 bit)

DTOG_RX : DTOG_RX
bits : 14 - 14 (1 bit)

CTR_RX : CTR_RX
bits : 15 - 15 (1 bit)


EP7R

endpoint register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP7R EP7R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EPTYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : EA
bits : 0 - 3 (4 bit)

STAT_TX : STAT_TX
bits : 4 - 5 (2 bit)

DTOG_TX : DTOG_TX
bits : 6 - 6 (1 bit)

CTR_TX : CTR_TX
bits : 7 - 7 (1 bit)

EP_KIND : EP_KIND
bits : 8 - 8 (1 bit)

EPTYPE : EPTYPE
bits : 9 - 10 (2 bit)

SETUP : SETUP
bits : 11 - 11 (1 bit)

STAT_RX : STAT_RX
bits : 12 - 13 (2 bit)

DTOG_RX : DTOG_RX
bits : 14 - 14 (1 bit)

CTR_RX : CTR_RX
bits : 15 - 15 (1 bit)


EP1R

endpoint register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP1R EP1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EPTYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : EA
bits : 0 - 3 (4 bit)

STAT_TX : STAT_TX
bits : 4 - 5 (2 bit)

DTOG_TX : DTOG_TX
bits : 6 - 6 (1 bit)

CTR_TX : CTR_TX
bits : 7 - 7 (1 bit)

EP_KIND : EP_KIND
bits : 8 - 8 (1 bit)

EPTYPE : EPTYPE
bits : 9 - 10 (2 bit)

SETUP : SETUP
bits : 11 - 11 (1 bit)

STAT_RX : STAT_RX
bits : 12 - 13 (2 bit)

DTOG_RX : DTOG_RX
bits : 14 - 14 (1 bit)

CTR_RX : CTR_RX
bits : 15 - 15 (1 bit)


CNTR

control register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR CNTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRES PDWN LPMODE FSUSP RESUME L1RESUME L1REQM ESOFM SOFM RESETM SUSPM WKUPM ERRM PMAOVRM CTRM

FRES : FRES
bits : 0 - 0 (1 bit)

PDWN : PDWN
bits : 1 - 1 (1 bit)

LPMODE : LPMODE
bits : 2 - 2 (1 bit)

FSUSP : FSUSP
bits : 3 - 3 (1 bit)

RESUME : RESUME
bits : 4 - 4 (1 bit)

L1RESUME : L1RESUME
bits : 5 - 5 (1 bit)

L1REQM : L1REQM
bits : 7 - 7 (1 bit)

ESOFM : ESOFM
bits : 8 - 8 (1 bit)

SOFM : SOFM
bits : 9 - 9 (1 bit)

RESETM : RESETM
bits : 10 - 10 (1 bit)

SUSPM : SUSPM
bits : 11 - 11 (1 bit)

WKUPM : WKUPM
bits : 12 - 12 (1 bit)

ERRM : ERRM
bits : 13 - 13 (1 bit)

PMAOVRM : PMAOVRM
bits : 14 - 14 (1 bit)

CTRM : CTRM
bits : 15 - 15 (1 bit)


ISTR

interrupt status register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISTR ISTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP_ID DIR L1REQ ESOF SOF RESET SUSP WKUP ERR PMAOVR CTR

EP_ID : EP_ID
bits : 0 - 3 (4 bit)

DIR : DIR
bits : 4 - 4 (1 bit)

L1REQ : L1REQ
bits : 7 - 7 (1 bit)

ESOF : ESOF
bits : 8 - 8 (1 bit)

SOF : SOF
bits : 9 - 9 (1 bit)

RESET : RESET
bits : 10 - 10 (1 bit)

SUSP : SUSP
bits : 11 - 11 (1 bit)

WKUP : WKUP
bits : 12 - 12 (1 bit)

ERR : ERR
bits : 13 - 13 (1 bit)

PMAOVR : PMAOVR
bits : 14 - 14 (1 bit)

CTR : CTR
bits : 15 - 15 (1 bit)


FNR

frame number register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FNR FNR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FN LSOF LCK RXDM RXDP

FN : FN
bits : 0 - 10 (11 bit)

LSOF : LSOF
bits : 11 - 12 (2 bit)

LCK : LCK
bits : 13 - 13 (1 bit)

RXDM : RXDM
bits : 14 - 14 (1 bit)

RXDP : RXDP
bits : 15 - 15 (1 bit)


DADDR

device address
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DADDR DADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD EF

ADD : ADD
bits : 0 - 6 (7 bit)

EF : EF
bits : 7 - 7 (1 bit)


BTABLE

Buffer table address
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTABLE BTABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTABLE

BTABLE : BTABLE
bits : 3 - 15 (13 bit)


LPMCSR

LPM control and status register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPMCSR LPMCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPMEN LPMACK REMWAKE BESL

LPMEN : LPMEN
bits : 0 - 0 (1 bit)
access : read-write

LPMACK : LPMACK
bits : 1 - 1 (1 bit)
access : read-write

REMWAKE : REMWAKE
bits : 3 - 3 (1 bit)
access : read-only

BESL : BESL
bits : 4 - 7 (4 bit)
access : read-only


BCDR

Battery charging detector
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCDR BCDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCDEN DCDEN PDEN SDEN DCDET PDET SDET PS2DET DPPU

BCDEN : BCDEN
bits : 0 - 0 (1 bit)
access : read-write

DCDEN : DCDEN
bits : 1 - 1 (1 bit)
access : read-write

PDEN : PDEN
bits : 2 - 2 (1 bit)
access : read-write

SDEN : SDEN
bits : 3 - 3 (1 bit)
access : read-write

DCDET : DCDET
bits : 4 - 4 (1 bit)
access : read-only

PDET : PDET
bits : 5 - 5 (1 bit)
access : read-only

SDET : SDET
bits : 6 - 6 (1 bit)
access : read-only

PS2DET : PS2DET
bits : 7 - 7 (1 bit)
access : read-only

DPPU : DPPU
bits : 15 - 15 (1 bit)
access : read-write


EP2R

endpoint register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP2R EP2R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EPTYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : EA
bits : 0 - 3 (4 bit)

STAT_TX : STAT_TX
bits : 4 - 5 (2 bit)

DTOG_TX : DTOG_TX
bits : 6 - 6 (1 bit)

CTR_TX : CTR_TX
bits : 7 - 7 (1 bit)

EP_KIND : EP_KIND
bits : 8 - 8 (1 bit)

EPTYPE : EPTYPE
bits : 9 - 10 (2 bit)

SETUP : SETUP
bits : 11 - 11 (1 bit)

STAT_RX : STAT_RX
bits : 12 - 13 (2 bit)

DTOG_RX : DTOG_RX
bits : 14 - 14 (1 bit)

CTR_RX : CTR_RX
bits : 15 - 15 (1 bit)


EP3R

endpoint register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP3R EP3R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EA STAT_TX DTOG_TX CTR_TX EP_KIND EPTYPE SETUP STAT_RX DTOG_RX CTR_RX

EA : EA
bits : 0 - 3 (4 bit)

STAT_TX : STAT_TX
bits : 4 - 5 (2 bit)

DTOG_TX : DTOG_TX
bits : 6 - 6 (1 bit)

CTR_TX : CTR_TX
bits : 7 - 7 (1 bit)

EP_KIND : EP_KIND
bits : 8 - 8 (1 bit)

EPTYPE : EPTYPE
bits : 9 - 10 (2 bit)

SETUP : SETUP
bits : 11 - 11 (1 bit)

STAT_RX : STAT_RX
bits : 12 - 13 (2 bit)

DTOG_RX : DTOG_RX
bits : 14 - 14 (1 bit)

CTR_RX : CTR_RX
bits : 15 - 15 (1 bit)



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