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RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

CIER

CIFR

CICR

IOPRSTR

AHBRSTR

APB2RSTR

APB1RSTR

IOPENR

AHBENR

APB2ENR

APB1ENR

IOPSMEN

ICSCR

AHBSMENR

APB2SMENR

APB1SMENR

CCIPR

CSR

CRRCR

CFGR


CR

Clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSI16ON HSI16KERON HSI16RDYF HSI16DIVEN HSI16DIVF HSI16OUTEN MSION MSIRDY HSEON HSERDY HSEBYP CSSLSEON RTCPRE PLLON PLLRDY

HSI16ON : 16 MHz high-speed internal clock enable
bits : 0 - 0 (1 bit)
access : read-write

HSI16KERON : High-speed internal clock enable bit for some IP kernels
bits : 1 - 1 (1 bit)
access : read-only

HSI16RDYF : Internal high-speed clock ready flag
bits : 2 - 2 (1 bit)
access : read-write

HSI16DIVEN : HSI16DIVEN
bits : 3 - 3 (1 bit)
access : read-write

HSI16DIVF : HSI16DIVF
bits : 4 - 4 (1 bit)
access : read-only

HSI16OUTEN : 16 MHz high-speed internal clock output enable
bits : 5 - 5 (1 bit)
access : read-write

MSION : MSI clock enable bit
bits : 8 - 8 (1 bit)
access : read-write

MSIRDY : MSI clock ready flag
bits : 9 - 9 (1 bit)
access : read-only

HSEON : HSE clock enable bit
bits : 16 - 16 (1 bit)
access : read-write

HSERDY : HSE clock ready flag
bits : 17 - 17 (1 bit)
access : read-only

HSEBYP : HSE clock bypass bit
bits : 18 - 18 (1 bit)
access : read-write

CSSLSEON : Clock security system on HSE enable bit
bits : 19 - 19 (1 bit)
access : read-write

RTCPRE : TC/LCD prescaler
bits : 20 - 21 (2 bit)
access : read-write

PLLON : PLL enable bit
bits : 24 - 24 (1 bit)
access : read-write

PLLRDY : PLL clock ready flag
bits : 25 - 25 (1 bit)
access : read-only


CIER

Clock interrupt enable register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIER CIER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYIE LSERDYIE HSI16RDYIE HSERDYIE PLLRDYIE MSIRDYIE HSI48RDYIE CSSLSE

LSIRDYIE : LSI ready interrupt flag
bits : 0 - 0 (1 bit)

LSERDYIE : LSE ready interrupt flag
bits : 1 - 1 (1 bit)

HSI16RDYIE : HSI16 ready interrupt flag
bits : 2 - 2 (1 bit)

HSERDYIE : HSE ready interrupt flag
bits : 3 - 3 (1 bit)

PLLRDYIE : PLL ready interrupt flag
bits : 4 - 4 (1 bit)

MSIRDYIE : MSI ready interrupt flag
bits : 5 - 5 (1 bit)

HSI48RDYIE : HSI48 ready interrupt flag
bits : 6 - 6 (1 bit)

CSSLSE : LSE CSS interrupt flag
bits : 7 - 7 (1 bit)


CIFR

Clock interrupt flag register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIFR CIFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYF LSERDYF HSI16RDYF HSERDYF PLLRDYF MSIRDYF HSI48RDYF CSSLSEF CSSHSEF

LSIRDYF : LSI ready interrupt flag
bits : 0 - 0 (1 bit)

LSERDYF : LSE ready interrupt flag
bits : 1 - 1 (1 bit)

HSI16RDYF : HSI16 ready interrupt flag
bits : 2 - 2 (1 bit)

HSERDYF : HSE ready interrupt flag
bits : 3 - 3 (1 bit)

PLLRDYF : PLL ready interrupt flag
bits : 4 - 4 (1 bit)

MSIRDYF : MSI ready interrupt flag
bits : 5 - 5 (1 bit)

HSI48RDYF : HSI48 ready interrupt flag
bits : 6 - 6 (1 bit)

CSSLSEF : LSE Clock Security System Interrupt flag
bits : 7 - 7 (1 bit)

CSSHSEF : Clock Security System Interrupt flag
bits : 8 - 8 (1 bit)


CICR

Clock interrupt clear register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CICR CICR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYC LSERDYC HSI16RDYC HSERDYC PLLRDYC MSIRDYC HSI48RDYC CSSLSEC CSSHSEC

LSIRDYC : LSI ready Interrupt clear
bits : 0 - 0 (1 bit)

LSERDYC : LSE ready Interrupt clear
bits : 1 - 1 (1 bit)

HSI16RDYC : HSI16 ready Interrupt clear
bits : 2 - 2 (1 bit)

HSERDYC : HSE ready Interrupt clear
bits : 3 - 3 (1 bit)

PLLRDYC : PLL ready Interrupt clear
bits : 4 - 4 (1 bit)

MSIRDYC : MSI ready Interrupt clear
bits : 5 - 5 (1 bit)

HSI48RDYC : HSI48 ready Interrupt clear
bits : 6 - 6 (1 bit)

CSSLSEC : LSE Clock Security System Interrupt clear
bits : 7 - 7 (1 bit)

CSSHSEC : Clock Security System Interrupt clear
bits : 8 - 8 (1 bit)


IOPRSTR

GPIO reset register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOPRSTR IOPRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOPARST IOPBRST IOPCRST IOPDRST IOPERST IOPHRST

IOPARST : I/O port A reset
bits : 0 - 0 (1 bit)

IOPBRST : I/O port B reset
bits : 1 - 1 (1 bit)

IOPCRST : I/O port A reset
bits : 2 - 2 (1 bit)

IOPDRST : I/O port D reset
bits : 3 - 3 (1 bit)

IOPERST : I/O port E reset
bits : 4 - 4 (1 bit)

IOPHRST : I/O port H reset
bits : 7 - 7 (1 bit)


AHBRSTR

AHB peripheral reset register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBRSTR AHBRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMARST MIFRST CRCRST TOUCHRST RNGRST CRYPRST

DMARST : DMA reset
bits : 0 - 0 (1 bit)

MIFRST : Memory interface reset
bits : 8 - 8 (1 bit)

CRCRST : Test integration module reset
bits : 12 - 12 (1 bit)

TOUCHRST : Touch Sensing reset
bits : 16 - 16 (1 bit)

RNGRST : Random Number Generator module reset
bits : 20 - 20 (1 bit)

CRYPRST : Crypto module reset
bits : 24 - 24 (1 bit)


APB2RSTR

APB2 peripheral reset register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2RSTR APB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGRST TIM21RST TM12RST ADCRST SPI1RST USART1RST DBGRST

SYSCFGRST : System configuration controller reset
bits : 0 - 0 (1 bit)

TIM21RST : TIM21 timer reset
bits : 2 - 2 (1 bit)

TM12RST : TIM22 timer reset
bits : 5 - 5 (1 bit)

ADCRST : ADC interface reset
bits : 9 - 9 (1 bit)

SPI1RST : SPI 1 reset
bits : 12 - 12 (1 bit)

USART1RST : USART1 reset
bits : 14 - 14 (1 bit)

DBGRST : DBG reset
bits : 22 - 22 (1 bit)


APB1RSTR

APB1 peripheral reset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RSTR APB1RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2RST TIM3RST TIM6RST TIM7RST WWDRST SPI2RST LPUART12RST LPUART1RST USART4RST USART5RST I2C1RST I2C2RST USBRST CRSRST PWRRST DACRST I2C3RST LPTIM1RST

TIM2RST : Timer2 reset
bits : 0 - 0 (1 bit)

TIM3RST : Timer3 reset
bits : 1 - 1 (1 bit)

TIM6RST : Timer 6 reset
bits : 4 - 4 (1 bit)

TIM7RST : Timer 7 reset
bits : 5 - 5 (1 bit)

WWDRST : Window watchdog reset
bits : 11 - 11 (1 bit)

SPI2RST : SPI2 reset
bits : 14 - 14 (1 bit)

LPUART12RST : UART2 reset
bits : 17 - 17 (1 bit)

LPUART1RST : LPUART1 reset
bits : 18 - 18 (1 bit)

USART4RST : USART4 reset
bits : 19 - 19 (1 bit)

USART5RST : USART5 reset
bits : 20 - 20 (1 bit)

I2C1RST : I2C1 reset
bits : 21 - 21 (1 bit)

I2C2RST : I2C2 reset
bits : 22 - 22 (1 bit)

USBRST : USB reset
bits : 23 - 23 (1 bit)

CRSRST : Clock recovery system reset
bits : 27 - 27 (1 bit)

PWRRST : Power interface reset
bits : 28 - 28 (1 bit)

DACRST : DAC interface reset
bits : 29 - 29 (1 bit)

I2C3RST : I2C3 reset
bits : 30 - 30 (1 bit)

LPTIM1RST : Low power timer reset
bits : 31 - 31 (1 bit)


IOPENR

GPIO clock enable register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOPENR IOPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOPAEN IOPBEN IOPCEN IOPDEN IOPEEN IOPHEN

IOPAEN : IO port A clock enable bit
bits : 0 - 0 (1 bit)

IOPBEN : IO port B clock enable bit
bits : 1 - 1 (1 bit)

IOPCEN : IO port A clock enable bit
bits : 2 - 2 (1 bit)

IOPDEN : I/O port D clock enable bit
bits : 3 - 3 (1 bit)

IOPEEN : I/O port E clock enable bit
bits : 4 - 4 (1 bit)

IOPHEN : I/O port H clock enable bit
bits : 7 - 7 (1 bit)


AHBENR

AHB peripheral clock enable register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBENR AHBENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN MIFEN CRCEN TOUCHEN RNGEN CRYPEN

DMAEN : DMA clock enable bit
bits : 0 - 0 (1 bit)

MIFEN : NVM interface clock enable bit
bits : 8 - 8 (1 bit)

CRCEN : CRC clock enable bit
bits : 12 - 12 (1 bit)

TOUCHEN : Touch Sensing clock enable bit
bits : 16 - 16 (1 bit)

RNGEN : Random Number Generator clock enable bit
bits : 20 - 20 (1 bit)

CRYPEN : Crypto clock enable bit
bits : 24 - 24 (1 bit)


APB2ENR

APB2 peripheral clock enable register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2ENR APB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGEN TIM21EN TIM22EN MIFIEN ADCEN SPI1EN USART1EN DBGEN

SYSCFGEN : System configuration controller clock enable bit
bits : 0 - 0 (1 bit)

TIM21EN : TIM21 timer clock enable bit
bits : 2 - 2 (1 bit)

TIM22EN : TIM22 timer clock enable bit
bits : 5 - 5 (1 bit)

MIFIEN : MiFaRe Firewall clock enable bit
bits : 7 - 7 (1 bit)

ADCEN : ADC clock enable bit
bits : 9 - 9 (1 bit)

SPI1EN : SPI1 clock enable bit
bits : 12 - 12 (1 bit)

USART1EN : USART1 clock enable bit
bits : 14 - 14 (1 bit)

DBGEN : DBG clock enable bit
bits : 22 - 22 (1 bit)


APB1ENR

APB1 peripheral clock enable register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1ENR APB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2EN TIM3EN TIM6EN TIM7EN WWDGEN SPI2EN USART2EN LPUART1EN USART4EN USART5EN I2C1EN I2C2EN USBEN CRSEN PWREN DACEN I2C3EN LPTIM1EN

TIM2EN : Timer2 clock enable bit
bits : 0 - 0 (1 bit)

TIM3EN : Timer3 clock enable bit
bits : 1 - 1 (1 bit)

TIM6EN : Timer 6 clock enable bit
bits : 4 - 4 (1 bit)

TIM7EN : Timer 7 clock enable bit
bits : 5 - 5 (1 bit)

WWDGEN : Window watchdog clock enable bit
bits : 11 - 11 (1 bit)

SPI2EN : SPI2 clock enable bit
bits : 14 - 14 (1 bit)

USART2EN : UART2 clock enable bit
bits : 17 - 17 (1 bit)

LPUART1EN : LPUART1 clock enable bit
bits : 18 - 18 (1 bit)

USART4EN : USART4 clock enable bit
bits : 19 - 19 (1 bit)

USART5EN : USART5 clock enable bit
bits : 20 - 20 (1 bit)

I2C1EN : I2C1 clock enable bit
bits : 21 - 21 (1 bit)

I2C2EN : I2C2 clock enable bit
bits : 22 - 22 (1 bit)

USBEN : USB clock enable bit
bits : 23 - 23 (1 bit)

CRSEN : Clock recovery system clock enable bit
bits : 27 - 27 (1 bit)

PWREN : Power interface clock enable bit
bits : 28 - 28 (1 bit)

DACEN : DAC interface clock enable bit
bits : 29 - 29 (1 bit)

I2C3EN : I2C3 clock enable bit
bits : 30 - 30 (1 bit)

LPTIM1EN : Low power timer clock enable bit
bits : 31 - 31 (1 bit)


IOPSMEN

GPIO clock enable in sleep mode register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOPSMEN IOPSMEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOPASMEN IOPBSMEN IOPCSMEN IOPDSMEN IOPESMEN IOPHSMEN

IOPASMEN : IOPASMEN
bits : 0 - 0 (1 bit)

IOPBSMEN : IOPBSMEN
bits : 1 - 1 (1 bit)

IOPCSMEN : IOPCSMEN
bits : 2 - 2 (1 bit)

IOPDSMEN : IOPDSMEN
bits : 3 - 3 (1 bit)

IOPESMEN : Port E clock enable during Sleep mode bit
bits : 4 - 4 (1 bit)

IOPHSMEN : IOPHSMEN
bits : 7 - 7 (1 bit)


ICSCR

Internal clock sources calibration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICSCR ICSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSI16CAL HSI16TRIM MSIRANGE MSICAL MSITRIM

HSI16CAL : nternal high speed clock calibration
bits : 0 - 7 (8 bit)
access : read-only

HSI16TRIM : High speed internal clock trimming
bits : 8 - 12 (5 bit)
access : read-write

MSIRANGE : MSI clock ranges
bits : 13 - 15 (3 bit)
access : read-write

MSICAL : MSI clock calibration
bits : 16 - 23 (8 bit)
access : read-only

MSITRIM : MSI clock trimming
bits : 24 - 31 (8 bit)
access : read-write


AHBSMENR

AHB peripheral clock enable in sleep mode register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBSMENR AHBSMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMASMEN MIFSMEN SRAMSMEN CRCSMEN TOUCHSMEN RNGSMEN CRYPSMEN

DMASMEN : DMA clock enable during sleep mode bit
bits : 0 - 0 (1 bit)

MIFSMEN : NVM interface clock enable during sleep mode bit
bits : 8 - 8 (1 bit)

SRAMSMEN : SRAM interface clock enable during sleep mode bit
bits : 9 - 9 (1 bit)

CRCSMEN : CRC clock enable during sleep mode bit
bits : 12 - 12 (1 bit)

TOUCHSMEN : Touch Sensing clock enable during sleep mode bit
bits : 16 - 16 (1 bit)

RNGSMEN : Random Number Generator clock enable during sleep mode bit
bits : 20 - 20 (1 bit)

CRYPSMEN : Crypto clock enable during sleep mode bit
bits : 24 - 24 (1 bit)


APB2SMENR

APB2 peripheral clock enable in sleep mode register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2SMENR APB2SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGSMEN TIM21SMEN TIM22SMEN ADCSMEN SPI1SMEN USART1SMEN DBGSMEN

SYSCFGSMEN : System configuration controller clock enable during sleep mode bit
bits : 0 - 0 (1 bit)

TIM21SMEN : TIM21 timer clock enable during sleep mode bit
bits : 2 - 2 (1 bit)

TIM22SMEN : TIM22 timer clock enable during sleep mode bit
bits : 5 - 5 (1 bit)

ADCSMEN : ADC clock enable during sleep mode bit
bits : 9 - 9 (1 bit)

SPI1SMEN : SPI1 clock enable during sleep mode bit
bits : 12 - 12 (1 bit)

USART1SMEN : USART1 clock enable during sleep mode bit
bits : 14 - 14 (1 bit)

DBGSMEN : DBG clock enable during sleep mode bit
bits : 22 - 22 (1 bit)


APB1SMENR

APB1 peripheral clock enable in sleep mode register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1SMENR APB1SMENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2SMEN TIM3SMEN TIM6SMEN TIM7SMEN WWDGSMEN SPI2SMEN USART2SMEN LPUART1SMEN USART4SMEN USART5SMEN I2C1SMEN I2C2SMEN USBSMEN CRSSMEN PWRSMEN DACSMEN I2C3SMEN LPTIM1SMEN

TIM2SMEN : Timer2 clock enable during sleep mode bit
bits : 0 - 0 (1 bit)

TIM3SMEN : Timer3 clock enable during Sleep mode bit
bits : 1 - 1 (1 bit)

TIM6SMEN : Timer 6 clock enable during sleep mode bit
bits : 4 - 4 (1 bit)

TIM7SMEN : Timer 7 clock enable during Sleep mode bit
bits : 5 - 5 (1 bit)

WWDGSMEN : Window watchdog clock enable during sleep mode bit
bits : 11 - 11 (1 bit)

SPI2SMEN : SPI2 clock enable during sleep mode bit
bits : 14 - 14 (1 bit)

USART2SMEN : UART2 clock enable during sleep mode bit
bits : 17 - 17 (1 bit)

LPUART1SMEN : LPUART1 clock enable during sleep mode bit
bits : 18 - 18 (1 bit)

USART4SMEN : USART4 clock enable during Sleep mode bit
bits : 19 - 19 (1 bit)

USART5SMEN : USART5 clock enable during Sleep mode bit
bits : 20 - 20 (1 bit)

I2C1SMEN : I2C1 clock enable during sleep mode bit
bits : 21 - 21 (1 bit)

I2C2SMEN : I2C2 clock enable during sleep mode bit
bits : 22 - 22 (1 bit)

USBSMEN : USB clock enable during sleep mode bit
bits : 23 - 23 (1 bit)

CRSSMEN : Clock recovery system clock enable during sleep mode bit
bits : 27 - 27 (1 bit)

PWRSMEN : Power interface clock enable during sleep mode bit
bits : 28 - 28 (1 bit)

DACSMEN : DAC interface clock enable during sleep mode bit
bits : 29 - 29 (1 bit)

I2C3SMEN : 2C3 clock enable during Sleep mode bit
bits : 30 - 30 (1 bit)

LPTIM1SMEN : Low power timer clock enable during sleep mode bit
bits : 31 - 31 (1 bit)


CCIPR

Clock configuration register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCIPR CCIPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART1SEL0 USART1SEL1 USART2SEL0 USART2SEL1 LPUART1SEL0 LPUART1SEL1 I2C1SEL0 I2C1SEL1 I2C3SEL LPTIM1SEL0 LPTIM1SEL1 HSI48MSEL

USART1SEL0 : USART1SEL0
bits : 0 - 0 (1 bit)

USART1SEL1 : USART1 clock source selection bits
bits : 1 - 1 (1 bit)

USART2SEL0 : USART2SEL0
bits : 2 - 2 (1 bit)

USART2SEL1 : USART2 clock source selection bits
bits : 3 - 3 (1 bit)

LPUART1SEL0 : LPUART1SEL0
bits : 10 - 10 (1 bit)

LPUART1SEL1 : LPUART1 clock source selection bits
bits : 11 - 11 (1 bit)

I2C1SEL0 : I2C1SEL0
bits : 12 - 12 (1 bit)

I2C1SEL1 : I2C1 clock source selection bits
bits : 13 - 13 (1 bit)

I2C3SEL : I2C3 clock source selection bits
bits : 16 - 17 (2 bit)

LPTIM1SEL0 : LPTIM1SEL0
bits : 18 - 18 (1 bit)

LPTIM1SEL1 : Low Power Timer clock source selection bits
bits : 19 - 19 (1 bit)

HSI48MSEL : 48 MHz HSI48 clock source selection bit
bits : 26 - 26 (1 bit)


CSR

Control and status register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSION LSIRDY LSEON LSERDY LSEBYP LSEDRV CSSLSEON CSSLSED RTCSEL RTCEN RTCRST RMVF OBLRSTF PINRSTF PORRSTF SFTRSTF IWDGRSTF WWDGRSTF LPWRSTF

LSION : Internal low-speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSIRDY : Internal low-speed oscillator ready bit
bits : 1 - 1 (1 bit)
access : read-write

LSEON : External low-speed oscillator enable bit
bits : 8 - 8 (1 bit)
access : read-write

LSERDY : External low-speed oscillator ready bit
bits : 9 - 9 (1 bit)
access : read-only

LSEBYP : External low-speed oscillator bypass bit
bits : 10 - 10 (1 bit)
access : read-write

LSEDRV : LSEDRV
bits : 11 - 12 (2 bit)
access : read-write

CSSLSEON : CSSLSEON
bits : 13 - 13 (1 bit)
access : read-write

CSSLSED : CSS on LSE failure detection flag
bits : 14 - 14 (1 bit)
access : read-write

RTCSEL : RTC and LCD clock source selection bits
bits : 16 - 17 (2 bit)
access : read-write

RTCEN : RTC clock enable bit
bits : 18 - 18 (1 bit)
access : read-write

RTCRST : RTC software reset bit
bits : 19 - 19 (1 bit)
access : read-write

RMVF : Remove reset flag
bits : 24 - 24 (1 bit)
access : read-write

OBLRSTF : OBLRSTF
bits : 25 - 25 (1 bit)
access : read-write

PINRSTF : PIN reset flag
bits : 26 - 26 (1 bit)
access : read-write

PORRSTF : POR/PDR reset flag
bits : 27 - 27 (1 bit)
access : read-write

SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-write

IWDGRSTF : Independent watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-write

WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-write

LPWRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-write


CRRCR

Clock recovery RC register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRRCR CRRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSI48ON HSI48RDY HSI48DIV6EN HSI48CAL

HSI48ON : 48MHz HSI clock enable bit
bits : 0 - 0 (1 bit)
access : read-write

HSI48RDY : 48MHz HSI clock ready flag
bits : 1 - 1 (1 bit)
access : read-only

HSI48DIV6EN : 48 MHz HSI clock divided by 6 output enable
bits : 2 - 2 (1 bit)
access : read-write

HSI48CAL : 48 MHz HSI clock calibration
bits : 8 - 15 (8 bit)
access : read-only


CFGR

Clock configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SWS HPRE PPRE1 PPRE2 STOPWUCK PLLSRC PLLMUL PLLDIV MCOSEL MCOPRE

SW : System clock switch
bits : 0 - 1 (2 bit)
access : read-write

SWS : System clock switch status
bits : 2 - 3 (2 bit)
access : read-only

HPRE : AHB prescaler
bits : 4 - 7 (4 bit)
access : read-write

PPRE1 : APB low-speed prescaler (APB1)
bits : 8 - 10 (3 bit)
access : read-write

PPRE2 : APB high-speed prescaler (APB2)
bits : 11 - 13 (3 bit)
access : read-write

STOPWUCK : Wake-up from stop clock selection
bits : 15 - 15 (1 bit)
access : read-write

PLLSRC : PLL entry clock source
bits : 16 - 16 (1 bit)
access : read-write

PLLMUL : PLL multiplication factor
bits : 18 - 21 (4 bit)
access : read-write

PLLDIV : PLL output division
bits : 22 - 23 (2 bit)
access : read-write

MCOSEL : Microcontroller clock output selection
bits : 24 - 27 (4 bit)
access : read-write

MCOPRE : Microcontroller clock output prescaler
bits : 28 - 30 (3 bit)
access : read-write



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