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FLASH_IF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x110 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

FASZR

FSYNDN

CRTRMM

FGPDM1

FGPDM2

FGPDM3

FGPDM4

FBFCR

FICR

FISR

FICLR

FRWTR

FSTR


FASZR

Flash Access Size Register [BHW]
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FASZR FASZR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASZ

ASZ : Access Size
bits : 0 - 0 (1 bit)
access : read-write


FSYNDN

Flash Sync Down Register [BHW]
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSYNDN FSYNDN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SD

SD : Sync Down
bits : 0 - 1 (2 bit)
access : read-write


CRTRMM

CR Trimming Data Mirror Register [BHW]
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CRTRMM CRTRMM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRMM TTRMM

TRMM : CR Trimming Data Mirror
bits : 0 - 8 (9 bit)
access : read-only

TTRMM : Temperature CR Trimming Data Mirror
bits : 16 - 19 (4 bit)
access : read-only


FGPDM1

Flash General Purpose Data Mirror Register1 [BHW]
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FGPDM1 FGPDM1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPD1

GPD1 : General Purpose Data1
bits : 0 - 30 (31 bit)
access : read-only


FGPDM2

Flash General Purpose Data Mirror Register2 [BHW]
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FGPDM2 FGPDM2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPD2

GPD2 : General Purpose Data2
bits : 0 - 30 (31 bit)
access : read-only


FGPDM3

Flash General Purpose Data Mirror Register3 [BHW]
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FGPDM3 FGPDM3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPD3

GPD3 : General Purpose Data3
bits : 0 - 30 (31 bit)
access : read-only


FGPDM4

Flash General Purpose Data Mirror Register4 [BHW]
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FGPDM4 FGPDM4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPD4

GPD4 : General Purpose Data4
bits : 0 - 30 (31 bit)
access : read-only


FBFCR

Flash Buffer Control Register [BHW]
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FBFCR FBFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BE BS

BE : Buffer Enable
bits : 0 - -1 (0 bit)
access : read-write

BS : Buffer Status
bits : 1 - 0 (0 bit)
access : read-only


FICR

Flash Interrupt Control Register [BHW]
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FICR FICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDYIE HNGIE ERRIE

RDYIE : Flash RDY Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

HNGIE : Flash HANG Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

ERRIE : Flash ECC Error Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write


FISR

Flash Interrupt Status Register [BHW]
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FISR FISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDYIF HNGIF ERRIF

RDYIF : Flash RDY Interrupt Flag
bits : 0 - -1 (0 bit)
access : read-only

HNGIF : Flash HANG Interrupt Flag
bits : 1 - 0 (0 bit)
access : read-only

ERRIF : Flash ECC Error Interrupt Flag
bits : 2 - 1 (0 bit)
access : read-only


FICLR

Flash Interrupt Clear Register [BHW]
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FICLR FICLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDYIC HNGIC ERRIC

RDYIC : Flash RDY Interrupt Clear
bits : 0 - -1 (0 bit)
access : read-write

HNGIC : Flash HANG Interrupt Clear
bits : 1 - 0 (0 bit)
access : read-write

ERRIC : Flash ECC Error Interrupt Clear
bits : 2 - 1 (0 bit)
access : read-write


FRWTR

Flash Read Wait Register [BHW]
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRWTR FRWTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWT

RWT : Read Wait Cycle
bits : 0 - 0 (1 bit)
access : read-write


FSTR

Flash Status Register [BHW]
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSTR FSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDY HNG ERR

RDY : Flash Rdy
bits : 0 - -1 (0 bit)
access : read-only

HNG : Flash Hang
bits : 1 - 0 (0 bit)
access : read-only

ERR : Flash ECC Error
bits : 2 - 1 (0 bit)
access : read-write



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