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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x34 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x44 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x14 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x38 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x48 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC Bytes (0x0)
size : 0x6 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x26 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ADSR

ADCR

SCIS23

SCIS01

PFNS

PCCR

PCFD

PCFD_FDAS1

PCIS

CMPCR

CMPD

ADSS23

ADSS01

ADST01

ADCT

PRTSL

SCTSL

ADCEN

CALSR

WCMRCOT

WCMRCIF

WCMPCR

WCMPSR

WCMPDL

WCMPDH

SFNS

SCCR

SCFD

SCFD_FDAS1


ADSR

A/D Status Register [BHW]
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADSR ADSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SCS PCS PCNS FDAS ADSTP

SCS : Scan conversion status flag
bits : 0 - -1 (0 bit)
access : read-only

PCS : Priority conversion status flag
bits : 1 - 0 (0 bit)
access : read-only

PCNS : Priority conversion pending flag
bits : 2 - 1 (0 bit)
access : read-only

FDAS : FIFO data placement selection bit
bits : 6 - 5 (0 bit)
access : read-write

ADSTP : A/D conversion forced stop bit
bits : 7 - 6 (0 bit)
access : read-write


ADCR

A/D Control Register [BHW]
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCR ADCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVRIE CMPIE PCIE SCIE CMPIF PCIF SCIF

OVRIE : FIFO overrun interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write

CMPIE : Conversion result comparison interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write

PCIE : Priority conversion interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write

SCIE : Scan conversion interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write

CMPIF : Conversion result comparison interrupt request bit
bits : 5 - 4 (0 bit)
access : read-write

PCIF : Priority conversion interrupt request bit
bits : 6 - 5 (0 bit)
access : read-write

SCIF : Scan conversion interrupt request bit
bits : 7 - 6 (0 bit)
access : read-write


SCIS23

Scan Conversion Input Selection Register 2 and 3 [BHW]
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCIS23 SCIS23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31

AN16 : Bit0 of SCIS23
bits : 0 - -1 (0 bit)
access : read-write

AN17 : Bit1 of SCIS23
bits : 1 - 0 (0 bit)
access : read-write

AN18 : Bit2 of SCIS23
bits : 2 - 1 (0 bit)
access : read-write

AN19 : Bit3 of SCIS23
bits : 3 - 2 (0 bit)
access : read-write

AN20 : Bit4 of SCIS23
bits : 4 - 3 (0 bit)
access : read-write

AN21 : Bit5 of SCIS23
bits : 5 - 4 (0 bit)
access : read-write

AN22 : Bit6 of SCIS23
bits : 6 - 5 (0 bit)
access : read-write

AN23 : Bit7 of SCIS23
bits : 7 - 6 (0 bit)
access : read-write

AN24 : Bit8 of SCIS23
bits : 8 - 7 (0 bit)
access : read-write

AN25 : Bit9 of SCIS23
bits : 9 - 8 (0 bit)
access : read-write

AN26 : Bit10 of SCIS23
bits : 10 - 9 (0 bit)
access : read-write

AN27 : Bit11 of SCIS23
bits : 11 - 10 (0 bit)
access : read-write

AN28 : Bit12 of SCIS23
bits : 12 - 11 (0 bit)
access : read-write

AN29 : Bit13 of SCIS23
bits : 13 - 12 (0 bit)
access : read-write

AN30 : Bit14 of SCIS23
bits : 14 - 13 (0 bit)
access : read-write

AN31 : Bit15 of SCIS23
bits : 15 - 14 (0 bit)
access : read-write


SCIS01

Scan Conversion Input Selection Register 1 [BHW]
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCIS01 SCIS01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15

AN0 : Bit0 of SCIS01
bits : 0 - -1 (0 bit)
access : read-write

AN1 : Bit1 of SCIS01
bits : 1 - 0 (0 bit)
access : read-write

AN2 : Bit2 of SCIS01
bits : 2 - 1 (0 bit)
access : read-write

AN3 : Bit3 of SCIS01
bits : 3 - 2 (0 bit)
access : read-write

AN4 : Bit4 of SCIS01
bits : 4 - 3 (0 bit)
access : read-write

AN5 : Bit5 of SCIS01
bits : 5 - 4 (0 bit)
access : read-write

AN6 : Bit6 of SCIS01
bits : 6 - 5 (0 bit)
access : read-write

AN7 : Bit7 of SCIS01
bits : 7 - 6 (0 bit)
access : read-write

AN8 : Bit8 of SCIS01
bits : 8 - 7 (0 bit)
access : read-write

AN9 : Bit9 of SCIS01
bits : 9 - 8 (0 bit)
access : read-write

AN10 : Bit10 of SCIS01
bits : 10 - 9 (0 bit)
access : read-write

AN11 : Bit11 of SCIS01
bits : 11 - 10 (0 bit)
access : read-write

AN12 : Bit12 of SCIS01
bits : 12 - 11 (0 bit)
access : read-write

AN13 : Bit13 of SCIS01
bits : 13 - 12 (0 bit)
access : read-write

AN14 : Bit14 of SCIS01
bits : 14 - 13 (0 bit)
access : read-write

AN15 : Bit15 of SCIS01
bits : 15 - 14 (0 bit)
access : read-write


PFNS

Priority Conversion FIFO Stage Count Setup Register [BHW]
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFNS PFNS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PFS TEST

PFS : Priority conversion FIFO stage count setting bits
bits : 0 - 0 (1 bit)
access : read-write

TEST : Test bits
bits : 4 - 4 (1 bit)
access : read-only


PCCR

Priority Conversion Control Register [BHW]
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCCR PCCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PSTR PHEN PEEN ESCE PFCLR POVR PFUL PEMP

PSTR : Priority conversion start bit
bits : 0 - -1 (0 bit)
access : read-write

PHEN : Priority conversion timer start enable bit
bits : 1 - 0 (0 bit)
access : read-write

PEEN : Priority conversion external start enable bit
bits : 2 - 1 (0 bit)
access : read-write

ESCE : External trigger analog input selection bit
bits : 3 - 2 (0 bit)
access : read-write

PFCLR : Priority conversion FIFO clear bit
bits : 4 - 3 (0 bit)
access : read-write

POVR : Priority conversion overrun flag
bits : 5 - 4 (0 bit)
access : read-write

PFUL : Priority conversion FIFO full bit
bits : 6 - 5 (0 bit)
access : read-only

PEMP : Priority conversion FIFO empty bit
bits : 7 - 6 (0 bit)
access : read-only


PCFD

Priority Conversion FIFO Data Register for ADSR.FDAS=0 [BHW]
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : PCFD_FDAS1
reset_Mask : 0x0

PCFD PCFD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC RS INVL PD

PC : Conversion input channel bits
bits : 0 - 3 (4 bit)
access : read-only

RS : Scan conversion start factor
bits : 8 - 9 (2 bit)
access : read-only

INVL : A/D conversion result disable bit
bits : 12 - 11 (0 bit)
access : read-only

PD : Priority conversion result
bits : 20 - 30 (11 bit)
access : read-only


PCFD_FDAS1

Priority Conversion FIFO Data Register for ADSR.FDAS=1 [BHW]
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : PCFD
reset_Mask : 0x0

PCFD_FDAS1 PCFD_FDAS1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC RS INVL PD

PC : Conversion input channel bits
bits : 0 - 3 (4 bit)
access : read-only

RS : Scan conversion start factor
bits : 8 - 9 (2 bit)
access : read-only

INVL : A/D conversion result disable bit
bits : 12 - 11 (0 bit)
access : read-only

PD : Priority conversion result
bits : 16 - 26 (11 bit)
access : read-only


PCIS

Priority Conversion Input Selection Register [BHW]
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCIS PCIS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 P1A P2A

P1A : Priority level 1 analog input selection
bits : 0 - 1 (2 bit)
access : read-write

P2A : Priority level 2 analog input selection
bits : 3 - 6 (4 bit)
access : read-write


CMPCR

A/D Comparison Control Register [BHW]
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPCR CMPCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CCH CMD0 CMD1 CMPEN

CCH : Comparison target analog input channel
bits : 0 - 3 (4 bit)
access : read-write

CMD0 : Comparison mode 0
bits : 5 - 4 (0 bit)
access : read-write

CMD1 : Comparison mode 1
bits : 6 - 5 (0 bit)
access : read-write

CMPEN : Conversion result comparison function operation enable bit
bits : 7 - 6 (0 bit)
access : read-write


CMPD

A/D Comparison Value Setup Register [BHW]
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPD CMPD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAD

CMAD : A/D conversion result value setting bits
bits : 6 - 14 (9 bit)
access : read-write


ADSS23

Sampling Time Selection Register 2 and 3 [BHW]
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADSS23 ADSS23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS16 TS17 TS18 TS19 TS20 TS21 TS22 TS23 TS24 TS25 TS26 TS27 TS28 TS29 TS30 TS31

TS16 : Bit0 of ADSS23
bits : 0 - -1 (0 bit)
access : read-write

TS17 : Bit1 of ADSS23
bits : 1 - 0 (0 bit)
access : read-write

TS18 : Bit2 of ADSS23
bits : 2 - 1 (0 bit)
access : read-write

TS19 : Bit3 of ADSS23
bits : 3 - 2 (0 bit)
access : read-write

TS20 : Bit4 of ADSS23
bits : 4 - 3 (0 bit)
access : read-write

TS21 : Bit5 of ADSS23
bits : 5 - 4 (0 bit)
access : read-write

TS22 : Bit6 of ADSS23
bits : 6 - 5 (0 bit)
access : read-write

TS23 : Bit7 of ADSS23
bits : 7 - 6 (0 bit)
access : read-write

TS24 : Bit8 of ADSS23
bits : 8 - 7 (0 bit)
access : read-write

TS25 : Bit9 of ADSS23
bits : 9 - 8 (0 bit)
access : read-write

TS26 : Bit10 of ADSS23
bits : 10 - 9 (0 bit)
access : read-write

TS27 : Bit11 of ADSS23
bits : 11 - 10 (0 bit)
access : read-write

TS28 : Bit12 of ADSS23
bits : 12 - 11 (0 bit)
access : read-write

TS29 : Bit13 of ADSS23
bits : 13 - 12 (0 bit)
access : read-write

TS30 : Bit14 of ADSS23
bits : 14 - 13 (0 bit)
access : read-write

TS31 : Bit15 of ADSS23
bits : 15 - 14 (0 bit)
access : read-write


ADSS01

Sampling Time Selection Register 0 and 1 [BHW]
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADSS01 ADSS01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15

TS0 : Bit0 of ADSS01
bits : 0 - -1 (0 bit)
access : read-write

TS1 : Bit1 of ADSS01
bits : 1 - 0 (0 bit)
access : read-write

TS2 : Bit2 of ADSS01
bits : 2 - 1 (0 bit)
access : read-write

TS3 : Bit3 of ADSS01
bits : 3 - 2 (0 bit)
access : read-write

TS4 : Bit4 of ADSS01
bits : 4 - 3 (0 bit)
access : read-write

TS5 : Bit5 of ADSS01
bits : 5 - 4 (0 bit)
access : read-write

TS6 : Bit6 of ADSS01
bits : 6 - 5 (0 bit)
access : read-write

TS7 : Bit7 of ADSS01
bits : 7 - 6 (0 bit)
access : read-write

TS8 : Bit8 of ADSS01
bits : 8 - 7 (0 bit)
access : read-write

TS9 : Bit9 of ADSS01
bits : 9 - 8 (0 bit)
access : read-write

TS10 : Bit10 of ADSS01
bits : 10 - 9 (0 bit)
access : read-write

TS11 : Bit11 of ADSS01
bits : 11 - 10 (0 bit)
access : read-write

TS12 : Bit12 of ADSS01
bits : 12 - 11 (0 bit)
access : read-write

TS13 : Bit13 of ADSS01
bits : 13 - 12 (0 bit)
access : read-write

TS14 : Bit14 of ADSS01
bits : 14 - 13 (0 bit)
access : read-write

TS15 : Bit15 of ADSS01
bits : 15 - 14 (0 bit)
access : read-write


ADST01

Sampling Time Setup Register [BHW]
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADST01 ADST01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST1 STX1 ST0 STX0

ST1 : Sampling time setting bits
bits : 0 - 3 (4 bit)
access : read-write

STX1 : Sampling time N times setting bits
bits : 5 - 6 (2 bit)
access : read-write

ST0 : Sampling time setting bits
bits : 8 - 11 (4 bit)
access : read-write

STX0 : Sampling time N times setting bits
bits : 13 - 14 (2 bit)
access : read-write


ADCT

Frequency Division Ratio Setup Register [BHW]
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCT ADCT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CT

CT : Frequency division ratio setting bits
bits : 0 - 6 (7 bit)
access : read-write


PRTSL

Priority Conversion Timer Trigger Selection Register [BHW]
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRTSL PRTSL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRTSL

PRTSL : Priority conversion timer trigger selection bit
bits : 0 - 2 (3 bit)
access : read-write


SCTSL

Scan Conversion Timer Trigger Selection Register [BHW]
address_offset : 0x39 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTSL SCTSL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SCTSL

SCTSL : Scan conversion timer trigger selection bit
bits : 0 - 2 (3 bit)
access : read-write


ADCEN

A/D Operation Enable Setup Register [BHW]
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCEN ADCEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBL READY ENBLTIME

ENBL : A/D operation enable bit
bits : 0 - -1 (0 bit)
access : read-write

READY : A/D operation enable state bit
bits : 1 - 0 (0 bit)
access : read-only

ENBLTIME : Operation enable state transition cycle selection bits
bits : 8 - 14 (7 bit)
access : read-write


CALSR

Calibration Setting Register [BHW]
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALSR CALSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFST CLBEN

OFST : Offset calibration value setting bits
bits : 0 - 6 (7 bit)
access : read-write

CLBEN : Calibration permission bit
bits : 8 - 7 (0 bit)
access : read-write


WCMRCOT

Range Comparison Threshold Excess Flag Register [BHW]
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCMRCOT WCMRCOT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCOOF

RCOOF : Threshold excess flag bit
bits : 0 - -1 (0 bit)
access : read-write


WCMRCIF

Range Comparison Flag Register [BHW]
address_offset : 0x48 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCMRCIF WCMRCIF read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCINT

RCINT : Range comparison interrupt factor flag
bits : 0 - -1 (0 bit)
access : read-write


WCMPCR

Range Comparison Control Register [BHW]
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCMPCR WCMPCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RCOE RCOIE RCOIRS RCOCD

RCOE : Range comparison execution enable bit
bits : 2 - 1 (0 bit)
access : read-write

RCOIE : Range comparison interrupt request enable bit
bits : 3 - 2 (0 bit)
access : read-write

RCOIRS : Selection bit of within-range and out-of- range confirmation
bits : 4 - 3 (0 bit)
access : read-write

RCOCD : Continuous detection specification count/state indication bits
bits : 5 - 6 (2 bit)
access : read-write


WCMPSR

Range Comparison Channel Select Register [BHW]
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCMPSR WCMPSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WCCH WCMD

WCCH : Comparison target analog input channel
bits : 0 - 3 (4 bit)
access : read-write

WCMD : Comparison mode select bit
bits : 5 - 4 (0 bit)
access : read-write


WCMPDL

Lower Limit Threshold Setup Register [BHW]
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCMPDL WCMPDL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMLD

CMLD : Lower limit threshold bits
bits : 6 - 14 (9 bit)
access : read-write


WCMPDH

Upper Limit Setup Register [BHW]
address_offset : 0x52 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WCMPDH WCMPDH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMHD

CMHD : Upper limit threshold bits
bits : 6 - 14 (9 bit)
access : read-write


SFNS

Scan Conversion FIFO Stage Count Setup Register [BHW]
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFNS SFNS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SFS

SFS : Scan conversion FIFO stage count setting bit
bits : 0 - 2 (3 bit)
access : read-write


SCCR

Scan Conversion Control Register [BHW]
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCCR SCCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SSTR SHEN RPT SFCLR SOVR SFUL SEMP

SSTR : Scan conversion start bit
bits : 0 - -1 (0 bit)
access : read-write

SHEN : Scan conversion timer start enable bit
bits : 1 - 0 (0 bit)
access : read-write

RPT : Scan conversion repeat bit
bits : 2 - 1 (0 bit)
access : read-write

SFCLR : Scan conversion FIFO clear bit
bits : 4 - 3 (0 bit)
access : read-write

SOVR : Scan conversion overrun flag
bits : 5 - 4 (0 bit)
access : read-write

SFUL : Scan conversion FIFO full bit
bits : 6 - 5 (0 bit)
access : read-only

SEMP : Scan conversion FIFO empty bit
bits : 7 - 6 (0 bit)
access : read-only


SCFD

Scan Conversion FIFO Data Register for ADSR.FDAS=0 [BHW]
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SCFD_FDAS1
reset_Mask : 0x0

SCFD SCFD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC RS INVL SD

SC : Conversion input channel bits
bits : 0 - 3 (4 bit)
access : read-only

RS : Scan conversion start factor
bits : 8 - 8 (1 bit)
access : read-only

INVL : A/D conversion result disable bit
bits : 12 - 11 (0 bit)
access : read-only

SD : Scan conversion result
bits : 20 - 30 (11 bit)
access : read-only


SCFD_FDAS1

Scan Conversion FIFO Data Register for ADSR.FDAS=1 [BHW]
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SCFD
reset_Mask : 0x0

SCFD_FDAS1 SCFD_FDAS1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC RS INVL SD

SC : Conversion input channel bits
bits : 0 - 3 (4 bit)
access : read-only

RS : Scan conversion start factor
bits : 8 - 8 (1 bit)
access : read-only

INVL : A/D conversion result disable bit
bits : 12 - 11 (0 bit)
access : read-only

SD : Scan conversion result
bits : 16 - 26 (11 bit)
access : read-only



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