\n
address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
USB/Ethernet-PLL Clock Control Register [BHW]
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UCEN0 : USB0 clock output enable bit
bits : 0 - -1 (0 bit)
access : read-write
UCSEL : USB1/0 clock selection bit
bits : 1 - 1 (1 bit)
access : read-write
UCEN1 : USB1 clock output enable bit
bits : 3 - 2 (0 bit)
access : read-write
ECEN : Ethernet clock output enable bit
bits : 4 - 3 (0 bit)
access : read-write
ECSEL : Ethernet clock selection bit
bits : 5 - 5 (1 bit)
access : read-write
USB/Ethernet-PLL Control Register 4 [BHW]
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPLLN : Frequency division ratio (N) setting bit of the USB/Ethernet-PLL clock
bits : 0 - 5 (6 bit)
access : read-write
USB/Ethernet-PLL Status Register [BHW]
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UPRDY : USB/Ethernet-PLL oscillation stabilization bit
bits : 0 - -1 (0 bit)
access : read-only
USB/Ethernet-PLL Interrupt Source Enable Register [BHW]
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPCSE : USB/Ethernet-PLL oscillation stabilization wait complete interrupt enable bit
bits : 0 - -1 (0 bit)
access : read-write
USB/Ethernet-PLL Interrupt Source Clear Register [BHW]
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UPCSC : USB/Ethernet-PLL oscillation stabilization interrupt source clear bit
bits : 0 - -1 (0 bit)
access : write-only
USB/Ethernet-PLL Interrupt Source Status Register [BHW]
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UPCSI : USB/Ethernet-PLL interrupt source status bit
bits : 0 - -1 (0 bit)
access : read-only
USB/Ethernet-PLL Control Register 5 [BHW]
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPLLM : Frequency division ratio (M) setting bit of the USB/Ethernet-PLL clock
bits : 0 - 2 (3 bit)
access : read-write
USB/Ethernet-PLL Setting Register 6 [BHW]
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBSR : CLKPLL division ratio setting bit
bits : 0 - 2 (3 bit)
access : read-write
USB/Ethernet-PLL Setting Register 7 [BHW]
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPLLEN : USB/Ethernet-PLL control bit in Timer mode
bits : 0 - -1 (0 bit)
access : read-write
USB0 Enable Register [BHW]
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBEN0 : USB0 enable bit
bits : 0 - -1 (0 bit)
access : read-write
USB1 Enable Register [BHW]
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBEN1 : USB1 enable bit
bits : 0 - -1 (0 bit)
access : read-write
USB/Ethernet-PLL Control Register 1 [BHW]
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPLLEN : USB/Ethernet-PLL oscillation enable bit
bits : 0 - -1 (0 bit)
access : read-write
UPINC : USB/Ethernet-PLL input clock selection bit
bits : 1 - 0 (0 bit)
access : read-write
USB/Ethernet-PLL Control Register 2 [BHW]
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPOWT : USB/Ethernet-PLL oscillation stabilization wait time setting bit
bits : 0 - 1 (2 bit)
access : read-write
USB/Ethernet-PLL Control Register 3 [BHW]
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPLLK : Frequency division ratio (K) setting bit of the USB/Ethernet-PLL clock
bits : 0 - 3 (4 bit)
access : read-write
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