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MFS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection : not protected

Registers

UART_SMR

CSIO_SMR

LIN_SMR

I2C_SMR

I2S_SMR

UART_SCR

CSIO_SCR

LIN_SCR

I2C_IBCR

I2S_SCR

I2C_ISBA

I2C_ISMK

UART_FCR

CSIO_FCR

LIN_FCR

I2C_FCR

I2S_FCR

UART_FBYTE1

CSIO_FBYTE1

LIN_FBYTE1

I2C_FBYTE1

I2S_FBYTE1

UART_FBYTE2

CSIO_FBYTE2

LIN_FBYTE2

I2C_FBYTE2

I2S_FBYTE2

CSIO_SCSTR0

I2C_NFCR

CSIO_SCSTR1

I2C_EIBCR

CSIO_SCSTR32

CSIO_SACSR

CSIO_STMR

CSIO_STMCR

CSIO_SCSCR

CSIO_SCSFR0

CSIO_SCSFR1

CSIO_SCSFR2

CSIO_TBYTE0

CSIO_TBYTE1

UART_ESCR

CSIO_ESCR

LIN_ESCR

I2C_IBSR

I2S_ESCR

CSIO_TBYTE2

CSIO_TBYTE3

UART_SSR

CSIO_SSR

LIN_SSR

I2C_SSR

I2S_SSR

UART_RDR

UART_TDR

CSIO_RDR

CSIO_TDR

LIN_RDR

LIN_TDR

I2C_RDR

I2C_TDR

I2S_RDR

I2S_TDR

UART_BGR

CSIO_BGR

LIN_BGR

I2C_BGR


UART_SMR

Serial Mode Register [BHW]
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : UART
reset_Mask : 0x0

UART_SMR UART_SMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOE BDS SBL MD

SOE : Serial data output enable bit
bits : 0 - -1 (0 bit)
access : read-write

BDS : Transfer direction select bit
bits : 2 - 1 (0 bit)
access : read-write

SBL : Stop bit length select bit
bits : 3 - 2 (0 bit)
access : read-write

MD : Operation mode set bit
bits : 5 - 6 (2 bit)
access : read-write


CSIO_SMR

Serial Mode Register [BHW]
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_SMR CSIO_SMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOE SCKE BDS SCINV MD

SOE : Serial data output enable bit
bits : 0 - -1 (0 bit)
access : read-write

SCKE : Master mode serial clock output enable bit
bits : 1 - 0 (0 bit)
access : read-write

BDS : Transfer direction select bit
bits : 2 - 1 (0 bit)
access : read-write

SCINV : Serial clock invert bit
bits : 3 - 2 (0 bit)
access : read-write

MD : Operation mode set bits
bits : 5 - 6 (2 bit)
access : read-write


LIN_SMR

Serial Mode Register [BHW]
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : LIN
reset_Mask : 0x0

LIN_SMR LIN_SMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOE SBL WUCR MD

SOE : Serial data output enable bit
bits : 0 - -1 (0 bit)
access : read-write

SBL : Stop bit length select bit
bits : 3 - 2 (0 bit)
access : read-write

WUCR : Wake-up control bit
bits : 4 - 3 (0 bit)
access : read-write

MD : Operation mode setting bits
bits : 5 - 6 (2 bit)
access : read-write


I2C_SMR

Serial Mode Register [BHW]
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2C
reset_Mask : 0x0

I2C_SMR I2C_SMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TIE RIE MD

TIE : Transmit interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write

RIE : Received interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write

MD : operation mode set bits
bits : 5 - 6 (2 bit)
access : read-write


I2S_SMR

Serial Mode Register [BHW]
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2S
reset_Mask : 0x0

I2S_SMR I2S_SMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOE BDS MD

SOE : Serial data output enable bit
bits : 0 - -1 (0 bit)
access : read-write

BDS : Transfer direction select bit
bits : 2 - 1 (0 bit)
access : read-write

MD : Oeration mode set bits
bits : 5 - 6 (2 bit)
access : read-write


UART_SCR

Serial Control Register [BHW]
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : UART
reset_Mask : 0x0

UART_SCR UART_SCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TXE RXE TBIE TIE RIE UPCL

TXE : Transmission operation enable bit
bits : 0 - -1 (0 bit)
access : read-write

RXE : Received operation enable bit
bits : 1 - 0 (0 bit)
access : read-write

TBIE : Transmit bus idle interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write

TIE : Transmit interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write

RIE : Received interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write

UPCL : Programmable Clear bit
bits : 7 - 6 (0 bit)
access : read-write


CSIO_SCR

Serial Control Register [BHW]
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_SCR CSIO_SCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TXE RXE TBIE TIE RIE SPI MS UPCL

TXE : Data transmission enable bit
bits : 0 - -1 (0 bit)
access : read-write

RXE : Data received enable bit
bits : 1 - 0 (0 bit)
access : read-write

TBIE : Transmit bus idle interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write

TIE : Transmit interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write

RIE : Received interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write

SPI : SPI corresponding bit
bits : 5 - 4 (0 bit)
access : read-write

MS : Master/Slave function select bit
bits : 6 - 5 (0 bit)
access : read-write

UPCL : Programmable clear bit
bits : 7 - 6 (0 bit)
access : read-write


LIN_SCR

Serial Control Register [BHW]
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : LIN
reset_Mask : 0x0

LIN_SCR LIN_SCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TXE RXE TBIE TIE RIE LBR MS UPCL

TXE : Data transmission enable bit
bits : 0 - -1 (0 bit)
access : read-write

RXE : Data reception enable bit
bits : 1 - 0 (0 bit)
access : read-write

TBIE : Transmit bus idle interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write

TIE : Transmit interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write

RIE : Received interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write

LBR : LIN Break Field setting bit (valid in master mode only)
bits : 5 - 4 (0 bit)
access : read-write

MS : Master/Slave function select bit
bits : 6 - 5 (0 bit)
access : read-write

UPCL : Programmable clear bit
bits : 7 - 6 (0 bit)
access : read-write


I2C_IBCR

I2C Bus Control Register [BHW]
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2C
reset_Mask : 0x0

I2C_IBCR I2C_IBCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INT BER INTE CNDE WSEL ACKE ACT_SCC MSS

INT : interrupt flag bit
bits : 0 - -1 (0 bit)
access : read-write

BER : Bus error flag bit
bits : 1 - 0 (0 bit)
access : read-only

INTE : Interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write

CNDE : Condition detection interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write

WSEL : Wait selection bit
bits : 4 - 3 (0 bit)
access : read-write

ACKE : Data byte acknowledge enable bit
bits : 5 - 4 (0 bit)
access : read-write

ACT_SCC : Operation flag/iteration start condition generation bit
bits : 6 - 5 (0 bit)
access : read-write

MSS : Master/slave select bit
bits : 7 - 6 (0 bit)
access : read-write


I2S_SCR

Serial Control Register [BHW]
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2S
reset_Mask : 0x0

I2S_SCR I2S_SCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TXE RXE RIE MS UPCL

TXE : Data transmission enable bit
bits : 0 - -1 (0 bit)
access : read-write

RXE : Data received enable bit
bits : 1 - 0 (0 bit)
access : read-write

RIE : Received interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write

MS : Master/Slave function select bit
bits : 6 - 5 (0 bit)
access : read-write

UPCL : Programmable clear bit
bits : 7 - 6 (0 bit)
access : read-write


I2C_ISBA

7-bit Slave Address Register [BHW]
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2C
reset_Mask : 0x0

I2C_ISBA I2C_ISBA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SA SAEN

SA : 7-bit slave address
bits : 0 - 5 (6 bit)
access : read-write

SAEN : Slave address enable bit
bits : 7 - 6 (0 bit)
access : read-write


I2C_ISMK

7-bit Slave Address Mask Register [BHW]
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2C
reset_Mask : 0x0

I2C_ISMK I2C_ISMK read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SM EN

SM : Slave address mask bits
bits : 0 - 5 (6 bit)
access : read-write

EN : I2C interface operation enable bit
bits : 7 - 6 (0 bit)
access : read-write


UART_FCR

FIFO Control Register [BHW]
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : UART
reset_Mask : 0x0

UART_FCR UART_FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FE1 FE2 FCL1 FCL2 FSET FLD FLST FSEL FTIE FDRQ FRIIE FLSTE

FE1 : FIFO1 operation enable bit
bits : 0 - -1 (0 bit)
access : read-write

FE2 : FIFO2 operation enable bit
bits : 1 - 0 (0 bit)
access : read-write

FCL1 : FIFO1 reset bit
bits : 2 - 1 (0 bit)
access : read-write

FCL2 : FIFO2 reset bit
bits : 3 - 2 (0 bit)
access : read-write

FSET : FIFO pointer save bit
bits : 4 - 3 (0 bit)
access : read-write

FLD : FIFO pointer reload bit
bits : 5 - 4 (0 bit)
access : read-write

FLST : FIFO re-transmit data lost flag bit
bits : 6 - 5 (0 bit)
access : read-only

FSEL : FIFO select bit
bits : 8 - 7 (0 bit)
access : read-write

FTIE : Transmit FIFO interrupt enable bit
bits : 9 - 8 (0 bit)
access : read-write

FDRQ : Transmit FIFO data request bit
bits : 10 - 9 (0 bit)
access : read-write

FRIIE : Received FIFO idle detection enable bit
bits : 11 - 10 (0 bit)
access : read-write

FLSTE : Re-transmission data lost detect enable bit
bits : 12 - 11 (0 bit)
access : read-write


CSIO_FCR

FIFO Control Register [BHW]
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_FCR CSIO_FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FE1 FE2 FCL1 FCL2 FSET FLD FLST FSEL FTIE FDRQ FRIIE FLSTE

FE1 : FIFO1 operation enable bit
bits : 0 - -1 (0 bit)
access : read-write

FE2 : FIFO2 operation enable bit
bits : 1 - 0 (0 bit)
access : read-write

FCL1 : FIFO1 reset bit
bits : 2 - 1 (0 bit)
access : read-write

FCL2 : FIFO2 reset bit
bits : 3 - 2 (0 bit)
access : read-write

FSET : FIFO pointer save bit
bits : 4 - 3 (0 bit)
access : read-write

FLD : FIFO pointer reload bit
bits : 5 - 4 (0 bit)
access : read-write

FLST : FIFO re-transmit data lost flag bit
bits : 6 - 5 (0 bit)
access : read-only

FSEL : FIFO select bit
bits : 8 - 7 (0 bit)
access : read-write

FTIE : Transmit FIFO interrupt enable bit
bits : 9 - 8 (0 bit)
access : read-write

FDRQ : Transmit FIFO data request bit
bits : 10 - 9 (0 bit)
access : read-write

FRIIE : Received FIFO idle detection enable bit
bits : 11 - 10 (0 bit)
access : read-write

FLSTE : Re-transmission data lost detect enable bit
bits : 12 - 11 (0 bit)
access : read-write


LIN_FCR

FIFO Control Register [BHW]
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : LIN
reset_Mask : 0x0

LIN_FCR LIN_FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FE1 FE2 FCL1 FCL2 FSET FLD FLST FSEL FTIE FDRQ FRIIE FLSTE

FE1 : FIFO1 operation enable bit
bits : 0 - -1 (0 bit)
access : read-write

FE2 : FIFO2 operation enable bit
bits : 1 - 0 (0 bit)
access : read-write

FCL1 : FIFO1 reset bit
bits : 2 - 1 (0 bit)
access : read-write

FCL2 : FIFO2 reset bit
bits : 3 - 2 (0 bit)
access : read-write

FSET : FIFO pointer save bit
bits : 4 - 3 (0 bit)
access : read-write

FLD : FIFO pointer reload bit
bits : 5 - 4 (0 bit)
access : read-write

FLST : FIFO re-transmit data lost flag bit
bits : 6 - 5 (0 bit)
access : read-only

FSEL : FIFO select bit
bits : 8 - 7 (0 bit)
access : read-write

FTIE : Transmit FIFO interrupt enable bit
bits : 9 - 8 (0 bit)
access : read-write

FDRQ : Transmit FIFO data request bit
bits : 10 - 9 (0 bit)
access : read-write

FRIIE : Received FIFO idle detection enable bit
bits : 11 - 10 (0 bit)
access : read-write

FLSTE : Re-transmission data lost detect enable bit
bits : 12 - 11 (0 bit)
access : read-write


I2C_FCR

FIFO Control Register [BHW]
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : I2C
reset_Mask : 0x0

I2C_FCR I2C_FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FE1 FE2 FCL1 FCL2 FSET FLD FLST FSEL FTIE FDRQ FRIIE FLSTE

FE1 : FIFO1 operation enable bit
bits : 0 - -1 (0 bit)
access : read-write

FE2 : FIFO2 operation enable bit
bits : 1 - 0 (0 bit)
access : read-write

FCL1 : FIFO1 reset bit
bits : 2 - 1 (0 bit)
access : read-write

FCL2 : FIFO2 reset bit
bits : 3 - 2 (0 bit)
access : read-write

FSET : FIFO pointer save bit
bits : 4 - 3 (0 bit)
access : read-write

FLD : FIFO pointer reload bit
bits : 5 - 4 (0 bit)
access : read-write

FLST : FIFO re-transmit data lost flag bit
bits : 6 - 5 (0 bit)
access : read-only

FSEL : FIFO select bit
bits : 8 - 7 (0 bit)
access : read-write

FTIE : Transmit FIFO interrupt enable bit
bits : 9 - 8 (0 bit)
access : read-write

FDRQ : Transmit FIFO data request bit
bits : 10 - 9 (0 bit)
access : read-write

FRIIE : Received FIFO idle detection enable bit
bits : 11 - 10 (0 bit)
access : read-write

FLSTE : Re-transmission data lost detect enable bit
bits : 12 - 11 (0 bit)
access : read-write


I2S_FCR

FIFO Control Register 0 [BHW]
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : I2S
reset_Mask : 0x0

I2S_FCR I2S_FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FE1 FE2 FCL1 FCL2 FSEL FTIE FDRQ

FE1 : FIFO1 operation enable bit
bits : 0 - -1 (0 bit)
access : read-write

FE2 : FIFO2 operation enable bit
bits : 1 - 0 (0 bit)
access : read-write

FCL1 : FIFO1 reset bit
bits : 2 - 1 (0 bit)
access : read-write

FCL2 : FIFO2 reset bit
bits : 3 - 2 (0 bit)
access : read-write

FSEL : FIFO select bit
bits : 8 - 7 (0 bit)
access : read-write

FTIE : Transmit FIFO interrupt enable bit
bits : 9 - 8 (0 bit)
access : read-write

FDRQ : Transmit FIFO data request bit
bits : 10 - 9 (0 bit)
access : read-write


UART_FBYTE1

FIFO Byte Register 1 [BHW]
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : UART
reset_Mask : 0x0

UART_FBYTE1 UART_FBYTE1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FD

FD : data count in FIFO
bits : 0 - 6 (7 bit)
access : read-write


CSIO_FBYTE1

FIFO Byte Register 1 [BHW]
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_FBYTE1 CSIO_FBYTE1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FD

FD : data count in FIFO
bits : 0 - 6 (7 bit)
access : read-write


LIN_FBYTE1

FIFO Byte Register 1 [BHW]
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : LIN
reset_Mask : 0x0

LIN_FBYTE1 LIN_FBYTE1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FD

FD : data count in FIFO
bits : 0 - 6 (7 bit)
access : read-write


I2C_FBYTE1

FIFO Byte Register 1 [BHW]
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2C
reset_Mask : 0x0

I2C_FBYTE1 I2C_FBYTE1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FD

FD : data count in FIFO
bits : 0 - 6 (7 bit)
access : read-write


I2S_FBYTE1

FIFO Byte Register 1 [BHW]
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2S
reset_Mask : 0x0

I2S_FBYTE1 I2S_FBYTE1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FD

FD : data count in FIFO
bits : 0 - 6 (7 bit)
access : read-write


UART_FBYTE2

FIFO Byte Register 2 [BHW]
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : UART
reset_Mask : 0x0

UART_FBYTE2 UART_FBYTE2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FD

FD : data count in FIFO
bits : 0 - 6 (7 bit)
access : read-write


CSIO_FBYTE2

FIFO Byte Register 2 [BHW]
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_FBYTE2 CSIO_FBYTE2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FD

FD : data count in FIFO
bits : 0 - 6 (7 bit)
access : read-write


LIN_FBYTE2

FIFO Byte Register 2 [BHW]
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : LIN
reset_Mask : 0x0

LIN_FBYTE2 LIN_FBYTE2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FD

FD : data count in FIFO
bits : 0 - 6 (7 bit)
access : read-write


I2C_FBYTE2

FIFO Byte Register 2 [BHW]
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2C
reset_Mask : 0x0

I2C_FBYTE2 I2C_FBYTE2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FD

FD : data count in FIFO
bits : 0 - 6 (7 bit)
access : read-write


I2S_FBYTE2

FIFO Byte Register 2 [BHW]
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2S
reset_Mask : 0x0

I2S_FBYTE2 I2S_FBYTE2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FD

FD : data count in FIFO
bits : 0 - 6 (7 bit)
access : read-write


CSIO_SCSTR0

Serial Chip Select Timing Register 0 [BHW]
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_SCSTR0 CSIO_SCSTR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CSHD

CSHD : Serial Chip Select Hold Delay bits
bits : 0 - 6 (7 bit)
access : read-write


I2C_NFCR

Noise Filter Control Register [BHW]
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2C
reset_Mask : 0x0

I2C_NFCR I2C_NFCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NFT

NFT : Noise Filter Time Select bits
bits : 0 - 3 (4 bit)
access : read-write


CSIO_SCSTR1

Serial Chip Select Timing Register 1 [BHW]
address_offset : 0x1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_SCSTR1 CSIO_SCSTR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CSSU

CSSU : Serial Chip Select Setup Delay bits
bits : 0 - 6 (7 bit)
access : read-write


I2C_EIBCR

Extension I2C Bus Control Register [BHW]
address_offset : 0x1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2C
reset_Mask : 0x0

I2C_EIBCR I2C_EIBCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BEC SOCE SCLC SDAC SCLS SDAS

BEC : Bus error control bit
bits : 0 - -1 (0 bit)
access : read-write

SOCE : Serial output enabled bit
bits : 1 - 0 (0 bit)
access : read-write

SCLC : SCL output control bit
bits : 2 - 1 (0 bit)
access : read-write

SDAC : SDA output control bit
bits : 3 - 2 (0 bit)
access : read-write

SCLS : SCL status bit
bits : 4 - 3 (0 bit)
access : read-only

SDAS : SDA status bit
bits : 5 - 4 (0 bit)
access : read-only


CSIO_SCSTR32

Serial Chip Select Timing Registers 2/3 [BHW]
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_SCSTR32 CSIO_SCSTR32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSDS

CSDS : Serial Chip Deselect bits
bits : 0 - 14 (15 bit)
access : read-write


CSIO_SACSR

Serial Support Control Register [BHW]
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_SACSR CSIO_SACSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRE TDIV TSYNE TINTE TINT CSE CSEIE TBEEN

TMRE : Serial Timer Enable bit
bits : 0 - -1 (0 bit)
access : read-write

TDIV : Timer Operation Clock Division bit
bits : 1 - 3 (3 bit)
access : read-write

TSYNE : Synchronous Transmission Enable bit
bits : 6 - 5 (0 bit)
access : read-write

TINTE : Timer Interrupt Enable bit
bits : 7 - 6 (0 bit)
access : read-write

TINT : Timer Interrupt Flag
bits : 8 - 7 (0 bit)
access : read-write

CSE : Chip Select Error Flag
bits : 11 - 10 (0 bit)
access : read-write

CSEIE : Chip Select Error Interupt Enable bit
bits : 12 - 11 (0 bit)
access : read-write

TBEEN : Transfer Byte Error Enable bit
bits : 13 - 12 (0 bit)
access : read-write


CSIO_STMR

Serial Timer Register [BHW]
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_STMR CSIO_STMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TM

TM : Timer Data bits
bits : 0 - 14 (15 bit)
access : read-only


CSIO_STMCR

Serial Timer Comparison Register [BHW]
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_STMCR CSIO_STMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC

TC : Compare bits
bits : 0 - 14 (15 bit)
access : read-write


CSIO_SCSCR

Serial Chip Select Control Status Register [BHW]
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_SCSCR CSIO_SCSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSOE CSEN0 CSEN1 CSEN2 CSEN3 CSLVL CDIV SCAM SCD SED SST

CSOE : Serial Chip Select Output Enable bit
bits : 0 - -1 (0 bit)
access : read-write

CSEN0 : Serial Chip Select Enable bit with SCS0 pin
bits : 1 - 0 (0 bit)
access : read-write

CSEN1 : Serial Chip Select Enable bit with SCS1 pin
bits : 2 - 1 (0 bit)
access : read-write

CSEN2 : Serial Chip Select Enable bit with SCS2 pin
bits : 3 - 2 (0 bit)
access : read-write

CSEN3 : Serial Chip Select Enable bit with SCS3 pin
bits : 4 - 3 (0 bit)
access : read-write

CSLVL : Serial Chip Select Level Setting bit
bits : 5 - 4 (0 bit)
access : read-write

CDIV : Serial Chip Select Timing Operation Clock Division bit
bits : 6 - 7 (2 bit)
access : read-write

SCAM : Serial Chip Select Active Hold bit
bits : 9 - 8 (0 bit)
access : read-write

SCD : Serial Chip Select Active Display bit
bits : 10 - 10 (1 bit)
access : read-write

SED : Serial Chip Select Active End bit
bits : 12 - 12 (1 bit)
access : read-write

SST : Serial Chip Select Active Start bit
bits : 14 - 14 (1 bit)
access : read-write


CSIO_SCSFR0

Serial Chip Select Format Register 0 [BHW]
address_offset : 0x34 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_SCSFR0 CSIO_SCSFR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CS1L CS1SPI CS1SCINV CS1CSLVL

CS1L : Transfer direction select bit of Serial Chip Select 1
bits : 0 - 3 (4 bit)
access : read-write

CS1SPI : SPI corresponding bit of Serial Chip Select 1
bits : 5 - 4 (0 bit)
access : read-write

CS1SCINV : Serial Clock Invert bit of Serial Chip Select 1
bits : 6 - 5 (0 bit)
access : read-write

CS1CSLVL : Serial Chip Select 1 Level Setting bit
bits : 7 - 6 (0 bit)
access : read-write


CSIO_SCSFR1

Serial Chip Select Format Register 1 [BHW]
address_offset : 0x35 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_SCSFR1 CSIO_SCSFR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CS2L CS2SPI CS2SCINV CS2CSLVL

CS2L : Transfer direction select bit of Serial Chip Select 2
bits : 0 - 3 (4 bit)
access : read-write

CS2SPI : SPI corresponding bit of Serial Chip Select 2
bits : 5 - 4 (0 bit)
access : read-write

CS2SCINV : Serial Clock Invert bit of Serial Chip Select 2
bits : 6 - 5 (0 bit)
access : read-write

CS2CSLVL : Serial Chip Select 2 Level Setting bit
bits : 7 - 6 (0 bit)
access : read-write


CSIO_SCSFR2

Serial Chip Select Format Register 2 [BHW]
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_SCSFR2 CSIO_SCSFR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CS3L CS3SPI CS3SCINV CS3CSLVL

CS3L : Transfer direction select bit of Serial Chip Select 3
bits : 0 - 3 (4 bit)
access : read-write

CS3SPI : SPI corresponding bit of Serial Chip Select 3
bits : 5 - 4 (0 bit)
access : read-write

CS3SCINV : Serial Clock Invert bit of Serial Chip Select 3
bits : 6 - 5 (0 bit)
access : read-write

CS3CSLVL : Serial Chip Select 3 Level Setting bit
bits : 7 - 6 (0 bit)
access : read-write


CSIO_TBYTE0

Transfer Byte Register 0 [BHW]
address_offset : 0x3C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_TBYTE0 CSIO_TBYTE0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CSIO_TBYTE1

Transfer Byte Register 1 [BHW]
address_offset : 0x3D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_TBYTE1 CSIO_TBYTE1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

UART_ESCR

Extended Communication Control Register [BHW]
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : UART
reset_Mask : 0x0

UART_ESCR UART_ESCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 L P PEN INV ESBL FLWEN

L : Data length select bit
bits : 0 - 1 (2 bit)
access : read-write

P : Parity select bit (only functions in operation mode 0)
bits : 3 - 2 (0 bit)
access : read-write

PEN : Parity enable bit (only functions in operation mode 0)
bits : 4 - 3 (0 bit)
access : read-write

INV : Inverted serial data format bit
bits : 5 - 4 (0 bit)
access : read-write

ESBL : Extension stop bit length select bit
bits : 6 - 5 (0 bit)
access : read-write

FLWEN : Flow control enable bit
bits : 7 - 6 (0 bit)
access : read-write


CSIO_ESCR

Extended Communication Control Register [BHW]
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_ESCR CSIO_ESCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 L WT CSFE L3 SOP

L : Data length select bits
bits : 0 - 1 (2 bit)
access : read-write

WT : Data transmit/received wait select bits
bits : 3 - 3 (1 bit)
access : read-write

CSFE : Serial Chip Select Format enable bit
bits : 5 - 4 (0 bit)
access : read-write

L3 : Bit3 of Data length select bits
bits : 6 - 5 (0 bit)
access : read-write

SOP : Serial output pin set bit
bits : 7 - 6 (0 bit)
access : read-write


LIN_ESCR

Extended Communication Control Register [BHW]
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : LIN
reset_Mask : 0x0

LIN_ESCR LIN_ESCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DEL LBL LBIE ESBL

DEL : LIN Break delimiter length select bits (valid in master mode only)
bits : 0 - 0 (1 bit)
access : read-write

LBL : LIN Break field length select bits (valid in master mode only)
bits : 2 - 2 (1 bit)
access : read-write

LBIE : LIN Break field detect interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write

ESBL : Extended stop bit length select bit
bits : 6 - 5 (0 bit)
access : read-write


I2C_IBSR

I2C Bus Status Register [BHW]
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2C
reset_Mask : 0x0

I2C_IBSR I2C_IBSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BB SPC RSC AL TRX RSA RACK FBT

BB : Bus state bit
bits : 0 - -1 (0 bit)
access : read-only

SPC : Stop condition check bit
bits : 1 - 0 (0 bit)
access : read-write

RSC : Iteration start condition check bit
bits : 2 - 1 (0 bit)
access : read-write

AL : Arbitration lost bit
bits : 3 - 2 (0 bit)
access : read-only

TRX : Data direction bit
bits : 4 - 3 (0 bit)
access : read-only

RSA : Reserved address detection bit
bits : 5 - 4 (0 bit)
access : read-only

RACK : Acknowledge flag bit
bits : 6 - 5 (0 bit)
access : read-only

FBT : First byte bit
bits : 7 - 6 (0 bit)
access : read-only


I2S_ESCR

Extended Communication Control Register [BHW]
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2S
reset_Mask : 0x0

I2S_ESCR I2S_ESCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 L L3 SOP

L : Data length select bits
bits : 0 - 1 (2 bit)
access : read-write

L3 : Data length select bit 3
bits : 6 - 5 (0 bit)
access : read-write

SOP : Serial output pin set bit
bits : 7 - 6 (0 bit)
access : read-write


CSIO_TBYTE2

Transfer Byte Register 2 [BHW]
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_TBYTE2 CSIO_TBYTE2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CSIO_TBYTE3

Transfer Byte Register 3 [BHW]
address_offset : 0x41 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_TBYTE3 CSIO_TBYTE3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

UART_SSR

Serial Status Register [BHW]
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : UART
reset_Mask : 0x0

UART_SSR UART_SSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TBI TDRE RDRF ORE FRE PE REC

TBI : Transmit bus idle flag
bits : 0 - -1 (0 bit)
access : read-only

TDRE : Transmit data empty flag bit
bits : 1 - 0 (0 bit)
access : read-only

RDRF : Received data full flag bit
bits : 2 - 1 (0 bit)
access : read-only

ORE : Overrun error flag bit
bits : 3 - 2 (0 bit)
access : read-only

FRE : Framing error flag bit
bits : 4 - 3 (0 bit)
access : read-only

PE : Parity error flag bit (only functions in operation mode 0)
bits : 5 - 4 (0 bit)
access : read-only

REC : Received error flag clear bit
bits : 7 - 6 (0 bit)
access : read-write


CSIO_SSR

Serial Status Register [BHW]
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_SSR CSIO_SSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TBI TDRE RDRF ORE AWC REC

TBI : Transmit bus idle flag bit
bits : 0 - -1 (0 bit)
access : read-only

TDRE : Transmit data empty flag bit
bits : 1 - 0 (0 bit)
access : read-only

RDRF : Received data full flag bit
bits : 2 - 1 (0 bit)
access : read-only

ORE : Overrun error flag bit
bits : 3 - 2 (0 bit)
access : read-only

AWC : Access Width Control bit
bits : 4 - 3 (0 bit)
access : read-write

REC : Received error flag clear bit
bits : 7 - 6 (0 bit)
access : read-write


LIN_SSR

Serial Status Register [BHW]
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : LIN
reset_Mask : 0x0

LIN_SSR LIN_SSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TBI TDRE RDRF ORE FRE LBD REC

TBI : Transmit bus idle flag bit
bits : 0 - -1 (0 bit)
access : read-only

TDRE : Transmit data empty flag bit
bits : 1 - 0 (0 bit)
access : read-only

RDRF : Received data full flag bit
bits : 2 - 1 (0 bit)
access : read-only

ORE : Overrun error flag bit
bits : 3 - 2 (0 bit)
access : read-only

FRE : Framing error flag bit
bits : 4 - 3 (0 bit)
access : read-only

LBD : LIN Break field detection flag bit
bits : 5 - 4 (0 bit)
access : read-write

REC : Received Error flag clear bit
bits : 7 - 6 (0 bit)
access : read-write


I2C_SSR

Serial Status Register [BHW]
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2C
reset_Mask : 0x0

I2C_SSR I2C_SSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TBI TDRE RDRF ORE TBIE DMA TSET REC

TBI : Transmit bus idle flag bit (Effective only when DMA mode is enabled)
bits : 0 - -1 (0 bit)
access : read-only

TDRE : Transmit data empty flag bit
bits : 1 - 0 (0 bit)
access : read-only

RDRF : Received data full flag bit
bits : 2 - 1 (0 bit)
access : read-only

ORE : Overrun error flag bit
bits : 3 - 2 (0 bit)
access : read-only

TBIE : Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled)
bits : 4 - 3 (0 bit)
access : read-write

DMA : DMA mode enable bit
bits : 5 - 4 (0 bit)
access : read-write

TSET : Transmit empty flag set bit
bits : 6 - 5 (0 bit)
access : read-write

REC : Received error flag clear bit
bits : 7 - 6 (0 bit)
access : read-write


I2S_SSR

Serial Status Register [BHW]
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : I2S
reset_Mask : 0x0

I2S_SSR I2S_SSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TDRE RDRF ORE AWC REC

TDRE : Transmit data empty flag bit
bits : 1 - 0 (0 bit)
access : read-only

RDRF : Received data full flag bit
bits : 2 - 1 (0 bit)
access : read-only

ORE : Overrun error flag bit
bits : 3 - 2 (0 bit)
access : read-only

AWC : FIFO access width set
bits : 4 - 3 (0 bit)
access : read-write

REC : Received error flag clear bit
bits : 7 - 6 (0 bit)
access : read-write


UART_RDR

Received Data Register [HW]
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : UART
reset_Mask : 0x0

UART_RDR UART_RDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D

D : Data
bits : 0 - 7 (8 bit)
access : read-only


UART_TDR

Transmit Data Register [HW]
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
alternate_register : UART
reset_Mask : 0x0

UART_TDR UART_TDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D

D : Data
bits : 0 - 7 (8 bit)
access : write-only


CSIO_RDR

Received Data Register [HW]
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_RDR CSIO_RDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D

D : Data
bits : 0 - 14 (15 bit)
access : read-only


CSIO_TDR

Transmit Data Register [HW]
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_TDR CSIO_TDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D

D : Data
bits : 0 - 14 (15 bit)
access : write-only


LIN_RDR

Received Data Register [HW]
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : LIN
reset_Mask : 0x0

LIN_RDR LIN_RDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D

D : Data
bits : 0 - 6 (7 bit)
access : read-only


LIN_TDR

Transmit Data Register [HW]
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
alternate_register : LIN
reset_Mask : 0x0

LIN_TDR LIN_TDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D

D : Data
bits : 0 - 6 (7 bit)
access : write-only


I2C_RDR

Received Data Register [HW]
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : I2C
reset_Mask : 0x0

I2C_RDR I2C_RDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D

D : Data
bits : 0 - 6 (7 bit)
access : read-only


I2C_TDR

Transmit Data Register [HW]
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
alternate_register : I2C
reset_Mask : 0x0

I2C_TDR I2C_TDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D

D : Data
bits : 0 - 6 (7 bit)
access : write-only


I2S_RDR

Received Data Register [HW]
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : I2S
reset_Mask : 0x0

I2S_RDR I2S_RDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

I2S_TDR

Transmit Data Register [HW]
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : I2S
reset_Mask : 0x0

I2S_TDR I2S_TDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

UART_BGR

Baud Rate Generator Registers [BHW]
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : UART
reset_Mask : 0x0

UART_BGR UART_BGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BGR EXT

BGR : Baud Rate Generator Register
bits : 0 - 13 (14 bit)
access : read-write

EXT : External clock select bit
bits : 15 - 14 (0 bit)
access : read-write


CSIO_BGR

Baud Rate Generator Registers [BHW]
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : CSIO
reset_Mask : 0x0

CSIO_BGR CSIO_BGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BGR

BGR : Baud Rate Generator Register
bits : 0 - 13 (14 bit)
access : read-write


LIN_BGR

Baud Rate Generator Registers [BHW]
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : LIN
reset_Mask : 0x0

LIN_BGR LIN_BGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BGR EXT

BGR : Baud Rate Generator Register
bits : 0 - 13 (14 bit)
access : read-write

EXT : External clock select bit
bits : 15 - 14 (0 bit)
access : read-write


I2C_BGR

Baud Rate Generator Registers [BHW]
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : I2C
reset_Mask : 0x0

I2C_BGR I2C_BGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BGR

BGR : Baud Rate Generator Register
bits : 0 - 13 (14 bit)
access : read-write



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