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RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x13 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2C Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x15 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x19 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x3 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WTCR1

WTDW

WTMOR

WTYR

ALMIR

ALHR

ALDR

ALMOR

ALYR

WTTR

WTCLKS

WTCLKM

WTCAL

WTCALEN

WTDIV

WTDIVEN

WTCALPRD

WTCOSEL

WTCR2

WTBR

WTSR

WTMIR

WTHR

WTDR


WTCR1

Control Register 1 [BHW]
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR1 WTCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST RUN SRST SCST SCRST BUSY MIEN HEN DEN MOEN YEN INTSSI INTSI INTMI INTHI INTTMI INTALI INTERI INTCRI INTSSIE INTSIE INTMIE INTHIE INTTMIE INTALIE INTERIE INTCRIE

ST : Start bit
bits : 0 - -1 (0 bit)
access : read-write

RUN : RTC count block operation bit
bits : 2 - 1 (0 bit)
access : read-only

SRST : RTC reset bit
bits : 3 - 2 (0 bit)
access : read-write

SCST : 1-second clock output stop bit
bits : 4 - 3 (0 bit)
access : read-write

SCRST : Sub second generation/1-second generation counter reset bit
bits : 5 - 4 (0 bit)
access : read-write

BUSY : Busy bit
bits : 6 - 5 (0 bit)
access : read-only

MIEN : Alarm minute register enable bit
bits : 8 - 7 (0 bit)
access : read-write

HEN : Alarm hour register enable bit
bits : 9 - 8 (0 bit)
access : read-write

DEN : Alarm date register enable bit
bits : 10 - 9 (0 bit)
access : read-write

MOEN : Alarm month register enable bit
bits : 11 - 10 (0 bit)
access : read-write

YEN : Alarm year register enable bit
bits : 12 - 11 (0 bit)
access : read-write

INTSSI : 0.5-second interrupt flag bit
bits : 16 - 15 (0 bit)
access : read-write

INTSI : 1-second interrupt flag bit
bits : 17 - 16 (0 bit)
access : read-write

INTMI : 1-minute interrupt flag bit
bits : 18 - 17 (0 bit)
access : read-write

INTHI : 1-hour interrupt flag bit
bits : 19 - 18 (0 bit)
access : read-write

INTTMI : Timer interrupt flag bit
bits : 20 - 19 (0 bit)
access : read-write

INTALI : Alarm interrupt flag bit
bits : 21 - 20 (0 bit)
access : read-write

INTERI : Time rewrite error interrupt flag bit
bits : 22 - 21 (0 bit)
access : read-write

INTCRI : Year/month/date/hour/minute/second/day of the week counter value read completion interrupt flag bit
bits : 23 - 22 (0 bit)
access : read-write

INTSSIE : 0.5-second interrupt enable bit
bits : 24 - 23 (0 bit)
access : read-write

INTSIE : 1-second interrupt enable bit
bits : 25 - 24 (0 bit)
access : read-write

INTMIE : 1-minute interrupt enable bit
bits : 26 - 25 (0 bit)
access : read-write

INTHIE : 1-hour interrupt enable bit
bits : 27 - 26 (0 bit)
access : read-write

INTTMIE : Timer interrupt enable bit
bits : 28 - 27 (0 bit)
access : read-write

INTALIE : Alarm interrupt enable bit
bits : 29 - 28 (0 bit)
access : read-write

INTERIE : Time rewrite error interrupt enable bit
bits : 30 - 29 (0 bit)
access : read-write

INTCRIE : Year/month/date/hour/minute/second/day of the week counter value read completion interrupt enable bit
bits : 31 - 30 (0 bit)
access : read-write


WTDW

Day of the Week Register [BHW]
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTDW WTDW read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DW

DW : Day of the week
bits : 0 - 1 (2 bit)
access : read-write


WTMOR

Month Register [BHW]
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTMOR WTMOR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MO TMO0

MO : The first digit of the month
bits : 0 - 2 (3 bit)
access : read-write

TMO0 : The second digit in the month
bits : 4 - 3 (0 bit)
access : read-write


WTYR

Year Register [BHW]
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTYR WTYR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 Y TY

Y : The first digit of the year
bits : 0 - 2 (3 bit)
access : read-write

TY : The second digit of the year
bits : 4 - 6 (3 bit)
access : read-write


ALMIR

Alarm Minute Register [BHW]
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALMIR ALMIR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMI TAMI

AMI : The first digit of the alarm-set minute
bits : 0 - 2 (3 bit)
access : read-write

TAMI : The second digit of the alarm-set minute
bits : 4 - 5 (2 bit)
access : read-write


ALHR

Alarm Hour Register [BHW]
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALHR ALHR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AH TAH

AH : The first digit of the alarm-set hour
bits : 0 - 2 (3 bit)
access : read-write

TAH : The second digit of the alarm-set hour
bits : 4 - 4 (1 bit)
access : read-write


ALDR

Alarm Date Register [BHW]
address_offset : 0x17 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALDR ALDR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AD TAD

AD : The first digit of the alarm-set date
bits : 0 - 2 (3 bit)
access : read-write

TAD : The second digit of the alarm-set date
bits : 4 - 4 (1 bit)
access : read-write


ALMOR

Alarm Month Register [BHW]
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALMOR ALMOR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMO TAMO0

AMO : The first digit of the alarm-set month
bits : 0 - 2 (3 bit)
access : read-write

TAMO0 : The second digit of the alarm-set month
bits : 4 - 3 (0 bit)
access : read-write


ALYR

Alarm Years Register [BHW]
address_offset : 0x1A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALYR ALYR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AY TAY

AY : The first digit of the alarm-set year
bits : 0 - 2 (3 bit)
access : read-write

TAY : The second digit of the alarm-set year
bits : 4 - 6 (3 bit)
access : read-write


WTTR

Timer Setting Register [BHW]
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTTR WTTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TM

TM : Timer setting register
bits : 0 - 16 (17 bit)
access : read-write


WTCLKS

Clock Selection Register [BHW]
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCLKS WTCLKS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCLKS

WTCLKS : Input clock selection bit
bits : 0 - -1 (0 bit)
access : read-write


WTCLKM

Selection Clock Status Register [BHW]
address_offset : 0x21 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WTCLKM WTCLKM read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCLKM

WTCLKM : Clock selection status bits
bits : 0 - 0 (1 bit)
access : read-only


WTCAL

Frequency Correction Value Setting Register [BHW]
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCAL WTCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WTCAL

WTCAL : Frequency correction value setting bits
bits : 0 - 8 (9 bit)
access : read-write


WTCALEN

Frequency Correction Enable Register [BHW]
address_offset : 0x26 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCALEN WTCALEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCALEN

WTCALEN : Frequency correction enable bit
bits : 0 - -1 (0 bit)
access : read-write


WTDIV

Divider Ratio Setting Register [BHW]
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTDIV WTDIV read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTDIV

WTDIV : Divider ratio setting bits
bits : 0 - 2 (3 bit)
access : read-write


WTDIVEN

Divider Output Enable Register [BHW]
address_offset : 0x29 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTDIVEN WTDIVEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTDIVEN WTDIVRDY

WTDIVEN : Divider enable bit
bits : 0 - -1 (0 bit)
access : read-write

WTDIVRDY : Divider status bit
bits : 1 - 0 (0 bit)
access : read-only


WTCALPRD

Frequency Correction Cycle Setting Register [BHW]
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCALPRD WTCALPRD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCALPRD

WTCALPRD : frequency correction value
bits : 0 - 4 (5 bit)
access : read-write


WTCOSEL

RTCCO Output Selection Register [BHW]
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCOSEL WTCOSEL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WTCOSEL

WTCOSEL : RTCCO output selection bit
bits : 0 - -1 (0 bit)
access : read-write


WTCR2

Control Register 2 [BHW]
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR2 WTCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CREAD TMST TMEN TMRUN

CREAD : Year/month/date/hour/minute/second/day of the week counter value read control bit
bits : 0 - -1 (0 bit)
access : read-write

TMST : Timer counter start bit
bits : 8 - 7 (0 bit)
access : read-write

TMEN : Timer counter control bit
bits : 9 - 8 (0 bit)
access : read-write

TMRUN : Timer counter operation bit
bits : 10 - 9 (0 bit)
access : read-only


WTBR

Counter Cycle Setting Register [BHW]
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTBR WTBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BR

BR : Counter Cycle Setting bits
bits : 0 - 22 (23 bit)
access : read-write


WTSR

Second Register [BHW]
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTSR WTSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 S TS

S : The first digit of the second
bits : 0 - 2 (3 bit)
access : read-write

TS : The second digit of the second
bits : 4 - 5 (2 bit)
access : read-write


WTMIR

Minute Register [BHW]
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTMIR WTMIR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MI TMI

MI : The first digit of the minute
bits : 0 - 2 (3 bit)
access : read-write

TMI : The second digit of the minute
bits : 4 - 5 (2 bit)
access : read-write


WTHR

Hour register [BHW]
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTHR WTHR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 H TH

H : The first digit of the hour
bits : 0 - 2 (3 bit)
access : read-write

TH : The second digit of the hour
bits : 4 - 4 (1 bit)
access : read-write


WTDR

Date Register [BHW]
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTDR WTDR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 D TD

D : The first digit of the date
bits : 0 - 2 (3 bit)
access : read-write

TD : The second digit of the date
bits : 4 - 4 (1 bit)
access : read-write



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