\n
address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x38 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected
Global Control Register 1 [HW]
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARITY : Odd/Even parity select bit
bits : 0 - -1 (0 bit)
access : read-write
FRM0 : Clock generation mode select bit
bits : 1 - 0 (0 bit)
access : read-write
FRM1 : Data frame coding style select bit
bits : 2 - 1 (0 bit)
access : read-write
MODE8N1 : Clock generation mode select bit
bits : 3 - 2 (0 bit)
access : read-write
MASKRXFUL : Receive data register full interrupt enable bit
bits : 4 - 3 (0 bit)
access : read-write
MASKTXEMP : Transmit data register empty interrupt enable bit
bits : 5 - 4 (0 bit)
access : read-write
MASKSTI : Start bit detect interrupt enable bit
bits : 6 - 5 (0 bit)
access : read-write
MASKCAEVENT : Card event detect interrupt enable bit
bits : 7 - 6 (0 bit)
access : read-write
MASKITEXP : Idle timer expired interrupt enable bit
bits : 8 - 7 (0 bit)
access : read-write
IOMOD : Data generation mode select bit
bits : 9 - 8 (0 bit)
access : read-write
CKMOD : Clock generation mode select bit
bits : 10 - 9 (0 bit)
access : read-write
RESND : Transmiter and receiver resend function enable bit
bits : 11 - 10 (0 bit)
access : read-write
GUAEN : Guard timer enable bit
bits : 12 - 11 (0 bit)
access : read-write
STIDT : Start idle timer bit
bits : 13 - 12 (0 bit)
access : read-write
IDTSC : Idle timer clock select bit
bits : 14 - 13 (0 bit)
access : read-write
Card Clock Frequency Register [HW]
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIVIDER : Card clock frequency divider
bits : 0 - 14 (15 bit)
access : read-write
Baud Rate Register [HW]
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRREG : Baud rate register bits
bits : 0 - 13 (14 bit)
access : read-write
LITTLESTEP : Little step bit for baud rate
bits : 15 - 14 (0 bit)
access : read-write
Guard Timer Register [HW]
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTREG : Guard time in ETUs
bits : 0 - 6 (7 bit)
access : read-write
Idle Timer Register [HW]
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDTREG : Reload value for idle timer
bits : 0 - 14 (15 bit)
access : read-write
Global Control Register 2 [HW]
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RX8N1 : Serial data output enable bit
bits : 0 - -1 (0 bit)
access : read-write
INVDATAOUT : Output inversion enable bit
bits : 1 - 0 (0 bit)
access : read-write
ICCDISABLE : ICC disable/enable bit
bits : 3 - 2 (0 bit)
access : read-write
FIFO Access Register [HW]
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Transmit/Received data
bits : 0 - 7 (8 bit)
access : read-write
Read FIFO Level Register [HW]
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIFORDLEVEL : Read FIFO level
bits : 0 - 14 (15 bit)
access : read-only
Write FIFO Level Register [HW]
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIFOWRLEVEL : Read FIFO level
bits : 0 - 14 (15 bit)
access : read-only
FIFO Mode Register [HW]
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOEN : FIFO enable bit
bits : 0 - -1 (0 bit)
access : read-write
RDFIFOOVRIRQEN : Read FIFO overflow interrupt enable bit
bits : 1 - 0 (0 bit)
access : read-write
WRFIFOIRQEN : Write FIFO empty interrupt enable bit
bits : 2 - 1 (0 bit)
access : read-write
RDFIFOIRQEN : Read FIFO full interrupt enable bit
bits : 3 - 2 (0 bit)
access : read-write
WRFIFOLEVEL : Write FIFO level
bits : 8 - 10 (3 bit)
access : read-write
RDFIFOLEVEL : Read FIFO level
bits : 12 - 14 (3 bit)
access : read-write
Write FIFO Clear Register [HW]
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRWRFIFO : Write FIFO clear bit
bits : 0 - -1 (0 bit)
access : read-write
Read FIFO Clear Register [HW]
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRRDFIFO : Read FIFO clear bit
bits : 0 - -1 (0 bit)
access : read-write
Status Register [HW]
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXEMP : Transmit data register status flag
bits : 0 - -1 (0 bit)
access : read-only
RXFUL : Received data register status flag
bits : 1 - 0 (0 bit)
access : read-only
RXACT : Receiver status flag
bits : 2 - 1 (0 bit)
access : read-only
TXACT : Transmitter status flag
bits : 3 - 2 (0 bit)
access : read-only
CARDDETECT : Level on ICx_CIN input pin
bits : 4 - 3 (0 bit)
access : read-only
CARDEVENT : Card event flag
bits : 5 - 4 (0 bit)
access : read-only
RECOFL : Received data register overflow flag
bits : 6 - 5 (0 bit)
access : read-only
IDTRUN : Idle timer running flag
bits : 7 - 6 (0 bit)
access : read-only
RDFIFOOVR : Read FIFO overflow flag
bits : 8 - 7 (0 bit)
access : read-only
RDFIFOFUL : Read FIFO full flag bit
bits : 9 - 8 (0 bit)
access : read-only
WRFIFOEMP : Write FIFO empty flag bit
bits : 10 - 9 (0 bit)
access : read-only
RXSTARTERR : Received start bit error flag bit
bits : 11 - 10 (0 bit)
access : read-only
TXRESEND : Transmitter resend flag bit
bits : 12 - 11 (0 bit)
access : read-only
RXRESEND : Receiver resend flag bit
bits : 13 - 12 (0 bit)
access : read-only
Interrupt Status Register [HW]
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDFIFOOVRIRQ : Read FIFO overflow interrupt flag bit
bits : 0 - -1 (0 bit)
access : read-only
WRFIFOIRQ : Write FIFO empty interrupt flag bit
bits : 1 - 0 (0 bit)
access : read-only
RDFIFOIRQ : Read FIFO full interrupt flag bit
bits : 2 - 1 (0 bit)
access : read-only
IDTEXPIRQ : Idle timer expired interrupt flag bit
bits : 3 - 2 (0 bit)
access : read-only
CARDEVENTIRQ : Card event interrupt flag bit
bits : 4 - 3 (0 bit)
access : read-only
RXSTBIIRQ : Received start bit interrupt flag bit
bits : 5 - 4 (0 bit)
access : read-only
TXEMPIRQ : Transmit data register empty interrupt flag bit
bits : 6 - 5 (0 bit)
access : read-only
RXFULIRQ : Received data register full interrupt flag bit
bits : 7 - 6 (0 bit)
access : read-only
Port Control Register [HW]
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIMOD : ICx_DATA output enable generation mode select bit
bits : 0 - -1 (0 bit)
access : read-write
IO1 : Level on ICx_DATA pin
bits : 2 - 1 (0 bit)
access : read-write
IO1EN : ICx_DATA output enable control bit
bits : 4 - 3 (0 bit)
access : read-write
CLKPT : ICx_CLK output value
bits : 6 - 5 (0 bit)
access : read-write
RST : ICx_RST output value
bits : 7 - 6 (0 bit)
access : read-write
VCCEN : ICx_VCC output value
bits : 8 - 7 (0 bit)
access : read-write
VPEN : ICx_VPEN output value
bits : 9 - 8 (0 bit)
access : read-write
CLKOUTEN : ICx_CLK output enable bit
bits : 12 - 11 (0 bit)
access : read-write
RSTOUTEN : ICx_RST output enable bit
bits : 13 - 12 (0 bit)
access : read-write
VCCOUTEN : ICx_VCC output enable bit
bits : 14 - 13 (0 bit)
access : read-write
VPENOUTEN : ICx_VPEN output enable bit
bits : 15 - 14 (0 bit)
access : read-write
Data Register [HW]
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Transmit/Received data
bits : 0 - 7 (8 bit)
access : read-write
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