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MFSI2S

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x4 Bytes (0x0)
size : 0x2 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x9 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CNTLREG

I2SCLK

I2SRST

I2SST


CNTLREG

Control Register [BHW]
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTLREG CNTLREG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAML I2SMOD FSPL I2SEN CKOE MSKB I2SRUN

FRAML : Frame length select bit
bits : 0 - -1 (0 bit)
access : read-write

I2SMOD : I2S mode select bit
bits : 3 - 2 (0 bit)
access : read-write

FSPL : I2SWS polarity set bit
bits : 4 - 3 (0 bit)
access : read-write

I2SEN : I2S mode enable bit
bits : 5 - 4 (0 bit)
access : read-write

CKOE : I2SCK and I2SWS output enable bit
bits : 6 - 5 (0 bit)
access : read-write

MSKB : Mask bit output bit
bits : 8 - 7 (0 bit)
access : read-write

I2SRUN : I2S clock generate enable bit
bits : 10 - 9 (0 bit)
access : read-write


I2SCLK

I2S Clock Register [BHW]
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SCLK I2SCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2SDIV MCKOE MCKIE

I2SDIV : I2S clock division set bit
bits : 0 - 6 (7 bit)
access : read-write

MCKOE : Main clock output enable bit
bits : 14 - 13 (0 bit)
access : read-write

MCKIE : Main clock input enable bit
bits : 15 - 14 (0 bit)
access : read-write


I2SRST

I2S Reset Register [BHW]
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

I2SRST I2SRST write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 I2SRST

I2SRST : I2S software reset bit
bits : 0 - 6 (7 bit)
access : write-only


I2SST

I2S Status Register [BHW]
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2SST I2SST read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKSTP BUSY

CKSTP : Clock stop indication bit
bits : 0 - -1 (0 bit)
access : read-only

BUSY : Bus busy indication for transmit bit
bits : 1 - 0 (0 bit)
access : read-only



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