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ETHERNET_MAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x200 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xD8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x98 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x78 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x180 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x208 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x210 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x250 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x700 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x800 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1000 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x102C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x1048 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MCR

GAR

MMC_CNTL

BMR

TPDR

RPDR

RDLAR

TDLAR

SR

OMR

IER

MFBOCR

RIWTR

AHBSR

MMC_INTR_RX

CHTDR

CHRDR

CHTBAR

CHRBAR

MMC_INTR_TX

MMC_INTR_MASK_RX

MMC_INTR_MASK_TX

TXOCTETCOUNT_GB

TXFRAMECOUNT_GB

TXBROADCASTFRAMES_G

TXMULTICASTFRAMES_G

TX64OCTETS_GB

TX65TO127OCTETS_GB

TX128TO255OCTETS_GB

TX256TO511OCTETS_GB

TX512TO1023OCTETS_GB

TX1024TOMAXOCTETS_GB

TXUNICASTFRAMES_GB

GDR

TXMULTICASTFRAMES_GB

TXBROADCASTFRAMES_GB

TXUNDERFLOWERROR

TXSINGLECOL_G

TXMULTICOL_G

TXDEFERRED

TXLATECOL

TXEXESSCOL

TXCARRIERERROR

TXOCTETCOUNT_G

TXFRAMECOUNT_G

TXEXECESSDEF_G

TXPAUSEFRAMES

TXVLANFRAMES_G

FCR

RXFRAMECOUNT_GB

RXOCTETCOUNT_GB

RXOCTETCOUNT_G

RXBROADCASTFRAMES_G

RXMULTICASTFRAMES_G

RXCRCERROR

RXALLIGNMENTERROR

RXRUNTERROR

RXJABBERERROR

RXUNDERSIZE_G

RXOVERSIZE_G

RX64OCTETS_GB

RX65TO127OCTETS_GB

RX128TO255OCTETS_GB

RX256TO511OCTETS_GB

RX512TO1023OCTETS_GB

VTR

RX1024TOMAXOCTETS_GB

RXUNICASTFRAMES_G

RXLENGTHERROR

RXOUTOFRANGETYPE

RXPAUSEFRAMES

RXFIFOOVERFLOW

RXVLANFRAMES_GB

RXWATCHDOGERROR

MMC_IPC_INTR_MASK_RX

MMC_IPC_INTR_RX

RXIPV4_GD_FRMS

RXIPV4_HDRERR_FRMS

RXIPV4_NOPAY_FRMS

RXIPV4_FRAG_FRMS

RXIPV4_UDSBL_FRMS

RXIPV6_GD_FRMS

RXIPV6_HDRERR_FRMS

RXIPV6_NOPAY_FRMS

RXUDP_GD_FRMS

RXUDP_ERR_FRMS

RXTCP_GD_FRMS

RXTCP_ERR_FRMS

RXICMP_GD_FRMS

RXICMP_ERR_FRMS

RXIPV4_GD_OCTETS

RXIPV4_HDRERR_OCTETS

RXIPV4_NOPAY_OCTETS

RXIPV4_FRAG_OCTETS

RXIPV4_UDSBL_OCTETS

RXIPV6_GD_OCTETS

RXIPV6_HDRERR_OCTETS

RXIPV6_NOPAY_OCTETS

RXUDP_GD_OCTETS

RXUDP_ERR_OCTETS

RXTCP_GD_OCTETS

RXTCP_ERR_OCTETS

RWFFR

RXICMP_GD_OCTETS

RXICMP_ERR_OCTETS

PMTR

LPICSR

LPITCR

ISR

IMR

MFFR

MAR0H

MAR0L

MAR1H

MAR1L

MAR2H

MAR2L

MAR3H

MAR3L

MAR4H

MAR4L

MAR5H

MAR5L

MAR6H

TSCR

SSIR

STSR

STNR

STSUR

STNUR

TSAR

TTSR

TTNR

STHWSR

TSR

PPSCR

ATNR

ATSR

MAR6L

MAR7H

MAR7L

MHTRH

MAR8H

MAR16H

MAR16L

MAR17H

MAR17L

MAR18H

MAR18L

MAR19H

MAR19L

MAR20H

MAR20L

MAR21H

MAR21L

MAR22H

MAR22L

MAR23H

MAR23L

MAR8L

MAR24H

MAR24L

MAR25H

MAR25L

MAR26H

MAR26L

MAR27H

MAR27L

MAR28H

MAR28L

MAR29H

MAR29L

MAR30H

MAR30L

MAR31H

MAR31L

MAR9H

MAR9L

MAR10H

MAR10L

MAR11H

MAR11L

MAR12H

MAR12L

MAR13H

MAR13L

MAR14H

MAR14L

MAR15H

MAR15L

MHTRL

RGSR


MCR

MAC Configuration Register [BHW]
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RE TE DC BL ACS LUD DR IPC DM LM DO FES PS DCRS IFG JE BE JD WD TC CST

RE : Receiver Enable
bits : 2 - 1 (0 bit)
access : read-write

TE : Transmitter Enable
bits : 3 - 2 (0 bit)
access : read-write

DC : Deferral Check
bits : 4 - 3 (0 bit)
access : read-write

BL : Back-off Limit
bits : 5 - 5 (1 bit)
access : read-write

ACS : Automatic Pad/CRC Stripping
bits : 7 - 6 (0 bit)
access : read-write

LUD : Link Up/Down in RGMII
bits : 8 - 7 (0 bit)
access : read-write

DR : Disable Retry
bits : 9 - 8 (0 bit)
access : read-write

IPC : Checksum Offload
bits : 10 - 9 (0 bit)
access : read-write

DM : Duplex mode
bits : 11 - 10 (0 bit)
access : read-write

LM : Loop-back Mode
bits : 12 - 11 (0 bit)
access : read-write

DO : Disable Receive Own
bits : 13 - 12 (0 bit)
access : read-write

FES : Speed
bits : 14 - 13 (0 bit)
access : read-write

PS : Port Select
bits : 15 - 14 (0 bit)
access : read-write

DCRS : Disable Carrier Sense During Transaction
bits : 16 - 15 (0 bit)
access : read-write

IFG : Inter-Frame GAP
bits : 17 - 18 (2 bit)
access : read-write

JE : Jumbo Frame Enable
bits : 20 - 19 (0 bit)
access : read-write

BE : Frame Burst Enable
bits : 21 - 20 (0 bit)
access : read-write

JD : Jabber Disable
bits : 22 - 21 (0 bit)
access : read-write

WD : Watchdog Disable
bits : 23 - 22 (0 bit)
access : read-write

TC : Transmit Configuration in RGMII
bits : 24 - 23 (0 bit)
access : read-write

CST : CRC stripping for Type frames
bits : 25 - 24 (0 bit)
access : read-write


GAR

GMII/MII Address Register [BHW]
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GAR GAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GB GW CR GR PA

GB : GMII/MII Busy
bits : 0 - -1 (0 bit)
access : read-write

GW : GMII/MII Write
bits : 1 - 0 (0 bit)
access : read-write

CR : Application Clock Range
bits : 2 - 4 (3 bit)
access : read-write

GR : GMII Register
bits : 6 - 9 (4 bit)
access : read-write

PA : Physical Layer Address
bits : 11 - 14 (4 bit)
access : read-write


MMC_CNTL

MMC Control Register [BHW]
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMC_CNTL MMC_CNTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B

B : Bits of MMC_CNTL
bits : 0 - 4 (5 bit)
access : read-write


BMR

Bus Mode Register [BHW]
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BMR BMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWR DA DSL ATDS PBL PR FB RPBL USP _8XPBL AAL MB TXPR

SWR : Software Reset
bits : 0 - -1 (0 bit)
access : read-write

DA : DMA Arbitration scheme
bits : 1 - 0 (0 bit)
access : read-write

DSL : Descriptor Skip Length
bits : 2 - 5 (4 bit)
access : read-write

ATDS : Alternate Descriptor Size
bits : 7 - 6 (0 bit)
access : read-write

PBL : Programmable Burst Length
bits : 8 - 12 (5 bit)
access : read-write

PR : Rx:Tx priority ratio
bits : 14 - 14 (1 bit)
access : read-write

FB : Fixed Burst
bits : 16 - 15 (0 bit)
access : read-write

RPBL : RxDMA PBL
bits : 17 - 21 (5 bit)
access : read-write

USP : Use Separate PBL
bits : 23 - 22 (0 bit)
access : read-write

_8XPBL : 8xPBL Mode
bits : 24 - 23 (0 bit)
access : read-write

AAL : Address-Aligned Beats
bits : 25 - 24 (0 bit)
access : read-write

MB : Mixed Burst
bits : 26 - 25 (0 bit)
access : read-write

TXPR : Transmit Priority
bits : 27 - 26 (0 bit)
access : read-write


TPDR

Transmit Poll Demand Register) [BHW]
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPDR TPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPD

TPD : Transmit Poll Demand
bits : 0 - 30 (31 bit)
access : read-write


RPDR

Receive Poll Demand Register [BHW]
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPDR RPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPD

RPD : Receive Poll Demand
bits : 0 - 30 (31 bit)
access : read-write


RDLAR

Receive Descriptor List Address Register) [BHW]
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLAR RDLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRL

SRL : Start of Receive List
bits : 2 - 30 (29 bit)
access : read-write


TDLAR

Transmit Descriptor List Address Register [BHW]
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDLAR TDLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STL

STL : Start of Transmit List
bits : 2 - 30 (29 bit)
access : read-write


SR

Status Register [BHW]
address_offset : 0x1014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TI TPS TU TJT OVF UNF RI RU RPS RWT ETI FBI ERI AIS NIS RS TS EB GLI GMI GPI TTI GLPII

TI : Transmit Interrupt
bits : 0 - -1 (0 bit)
access : read-only

TPS : Transmit Process Stopped
bits : 1 - 0 (0 bit)
access : read-only

TU : Transmit Buffer Unavailable
bits : 2 - 1 (0 bit)
access : read-only

TJT : Transmit Jabber Timeout
bits : 3 - 2 (0 bit)
access : read-only

OVF : Receive Overflow
bits : 4 - 3 (0 bit)
access : read-only

UNF : Transmit underflow
bits : 5 - 4 (0 bit)
access : read-only

RI : Receive Interrupt
bits : 6 - 5 (0 bit)
access : read-only

RU : Receive Buffer Unavailable
bits : 7 - 6 (0 bit)
access : read-only

RPS : Receive process Stopped
bits : 8 - 7 (0 bit)
access : read-only

RWT : Receive Watchdog Timeout
bits : 9 - 8 (0 bit)
access : read-only

ETI : Early Transmit Interrupt
bits : 10 - 9 (0 bit)
access : read-only

FBI : Fatal Bus Error Interrupt
bits : 13 - 12 (0 bit)
access : read-only

ERI : Early Receive Interrupt
bits : 14 - 13 (0 bit)
access : read-only

AIS : Abnormal Interrupt Summary
bits : 15 - 14 (0 bit)
access : read-only

NIS : Normal Interrupt Summary
bits : 16 - 15 (0 bit)
access : read-only

RS : Receive Process State
bits : 17 - 18 (2 bit)
access : read-only

TS : Transmit Process State
bits : 20 - 21 (2 bit)
access : read-only

EB : Error Bits
bits : 23 - 24 (2 bit)
access : read-only

GLI : GMAC Line interface Interrupt
bits : 26 - 25 (0 bit)
access : read-only

GMI : GMAC MMC Interrupt
bits : 27 - 26 (0 bit)
access : read-only

GPI : GMAC PMT Interrupt
bits : 28 - 27 (0 bit)
access : read-only

TTI : Time-Stamp Trigger Interrupt
bits : 29 - 28 (0 bit)
access : read-only

GLPII : GMAC LPI Interrupt
bits : 30 - 29 (0 bit)
access : read-only


OMR

Operation Mode Register [BHW]
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OMR OMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR OSF RTC FUF FEF ST TTC FTF TSF DFF RSF DT

SR : Start/Stop Receive
bits : 1 - 0 (0 bit)
access : read-write

OSF : Operate on Second Frame
bits : 2 - 1 (0 bit)
access : read-write

RTC : Receive Threshold Control
bits : 3 - 3 (1 bit)
access : read-write

FUF : Forward Undersized Good Frames
bits : 6 - 5 (0 bit)
access : read-write

FEF : Forward Error Frames
bits : 7 - 6 (0 bit)
access : read-write

ST : Start/Stop Transmission Command
bits : 13 - 12 (0 bit)
access : read-write

TTC : Transmit Threshold Control
bits : 14 - 15 (2 bit)
access : read-write

FTF : Flush Transmit FIFO
bits : 20 - 19 (0 bit)
access : read-write

TSF : Transmit Store Forward
bits : 21 - 20 (0 bit)
access : read-write

DFF : Disable Flushing of Received Frames
bits : 24 - 23 (0 bit)
access : read-write

RSF : Receive Store and Forward
bits : 25 - 24 (0 bit)
access : read-write

DT : Disable Dropping of TCP/IP Checksum Error Frames
bits : 26 - 25 (0 bit)
access : read-write


IER

Interrupt Enable Register [BHW]
address_offset : 0x101C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIE TSE TUE TJE OVE UNE RIE RUE RSE RWE ETE FBE ERE AIE NIE

TIE : Transmit Interrupt
bits : 0 - -1 (0 bit)
access : read-write

TSE : Transmit Process Stopped
bits : 1 - 0 (0 bit)
access : read-write

TUE : Transmit Buffer Unavailable
bits : 2 - 1 (0 bit)
access : read-write

TJE : Transmit Jabber Timeout
bits : 3 - 2 (0 bit)
access : read-write

OVE : Receive Overflow Enable
bits : 4 - 3 (0 bit)
access : read-only

UNE : Transmit underflow Enable
bits : 5 - 4 (0 bit)
access : read-write

RIE : Receive Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

RUE : Receive Buffer Unavailable Enable
bits : 7 - 6 (0 bit)
access : read-write

RSE : Receive Process Stopped Enable
bits : 8 - 7 (0 bit)
access : read-write

RWE : Receive Watchdog Timeout Enable
bits : 9 - 8 (0 bit)
access : read-write

ETE : Early Transmit Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write

FBE : Fatal Bus Error Enable
bits : 13 - 12 (0 bit)
access : read-write

ERE : Early Receive Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write

AIE : Abnormal Interrupt Summary Enable
bits : 15 - 14 (0 bit)
access : read-write

NIE : Normal Interrupt Summary Enable
bits : 16 - 15 (0 bit)
access : read-write


MFBOCR

Missed Frame and Buffer Overflow Counter Register [BHW]
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MFBOCR MFBOCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMFH ONMFH NMFF ONMFF

NMFH : Number of Missed frame by HOST
bits : 0 - 14 (15 bit)
access : read-only

ONMFH : Overflow NMFH
bits : 16 - 15 (0 bit)
access : read-only

NMFF : Number of Missed frame by Ethernet-MAC
bits : 17 - 26 (10 bit)
access : read-only

ONMFF : Overflow NMFF
bits : 28 - 27 (0 bit)
access : read-only


RIWTR

Receive Interrupt Watchdog Timer Register [BHW]
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIWTR RIWTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIWT

RIWT : RI Watchdog Timer count
bits : 0 - 6 (7 bit)
access : read-only


AHBSR

AHB Status Register [BHW]
address_offset : 0x102C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AHBSR AHBSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHBS

AHBS : AHB Status
bits : 0 - -1 (0 bit)
access : read-only


MMC_INTR_RX

Receive Interrupt Register [BHW]
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMC_INTR_RX MMC_INTR_RX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B

B : Bits of MMC_INTR_RX
bits : 0 - 22 (23 bit)
access : read-write


CHTDR

Current Host Transmit Descriptor Register [BHW]
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHTDR CHTDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTDAP

HTDAP : Host Transmit Descriptor Address Pointer
bits : 0 - 30 (31 bit)
access : read-only


CHRDR

Current Host Receive Descriptor Register [BHW]
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHRDR CHRDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRDAP

HRDAP : Host Receive Descriptor Address Pointer
bits : 0 - 30 (31 bit)
access : read-only


CHTBAR

Current Host Transmit Buffer Address Register [BHW]
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHTBAR CHTBAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTBAR

HTBAR : Host Transmit Buffer Address Register
bits : 0 - 30 (31 bit)
access : read-only


CHRBAR

Current Host Receive Buffer Address Register [BHW]
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHRBAR CHRBAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRBAR

HRBAR : Host Receive Buffer Address Register
bits : 0 - 30 (31 bit)
access : read-only


MMC_INTR_TX

MMC Transmit Interrupt Register [BHW]
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMC_INTR_TX MMC_INTR_TX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B

B : Bits of MMC_INTR_TX
bits : 0 - 23 (24 bit)
access : read-write


MMC_INTR_MASK_RX

MMC Receive Interrupt Mask Register [BHW]
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMC_INTR_MASK_RX MMC_INTR_MASK_RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B

B : Bits of MMC_INTR_MASK_RX
bits : 0 - 22 (23 bit)
access : read-write


MMC_INTR_MASK_TX

MMC Transmit Interrupt Mask Register [BHW]
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMC_INTR_MASK_TX MMC_INTR_MASK_TX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B

B : Bits of MMC_INTR_MASK_TX
bits : 0 - 23 (24 bit)
access : read-write


TXOCTETCOUNT_GB

Number of bytes transmitted (exclusive of preamble and retried bytes) in good and bad frames [BHW]
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXOCTETCOUNT_GB TXOCTETCOUNT_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFRAMECOUNT_GB

Number of good and bad frames transmitted exclusive of retried frames [BHW]
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXFRAMECOUNT_GB TXFRAMECOUNT_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXBROADCASTFRAMES_G

Number of good broadcast frames transmitted [BHW]
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXBROADCASTFRAMES_G TXBROADCASTFRAMES_G read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXMULTICASTFRAMES_G

Number of good multicast frames transmitted[BHW]
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXMULTICASTFRAMES_G TXMULTICASTFRAMES_G read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TX64OCTETS_GB

Number of good and bad frames transmitted with length of 64 bytes exclusive of preamble and retried frames [BHW]
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TX64OCTETS_GB TX64OCTETS_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TX65TO127OCTETS_GB

Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried frames [BHW]
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TX65TO127OCTETS_GB TX65TO127OCTETS_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TX128TO255OCTETS_GB

Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes exclusive of preamble and retried frames [BHW]
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TX128TO255OCTETS_GB TX128TO255OCTETS_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TX256TO511OCTETS_GB

Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes exclusive of preamble and retried frames [BHW]
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TX256TO511OCTETS_GB TX256TO511OCTETS_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TX512TO1023OCTETS_GB

Number of good and bad frames transmitted with length between 512 and 1023 (inclusive) bytes exclusive of preamble and retried frames [BHW]
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TX512TO1023OCTETS_GB TX512TO1023OCTETS_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TX1024TOMAXOCTETS_GB

Number of good and bad frames transmitted with length between 1024 and Maxsize (inclusive) bytes exclusive of preamble and retried frames [BHW]
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TX1024TOMAXOCTETS_GB TX1024TOMAXOCTETS_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXUNICASTFRAMES_GB

Number of good and bad unicast frames transmitted [BHW]
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXUNICASTFRAMES_GB TXUNICASTFRAMES_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GDR

GMII/MII Data Register [BHW]
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GDR GDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GD

GD : GMII/MII Data Register
bits : 0 - 14 (15 bit)
access : read-write


TXMULTICASTFRAMES_GB

Number of good and bad multicast frames transmitted [BHW]
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXMULTICASTFRAMES_GB TXMULTICASTFRAMES_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXBROADCASTFRAMES_GB

Number of good and bad broadcast frames transmitted [BHW]
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXBROADCASTFRAMES_GB TXBROADCASTFRAMES_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXUNDERFLOWERROR

Number of frames aborted due to frame underflow error [BHW]
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXUNDERFLOWERROR TXUNDERFLOWERROR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXSINGLECOL_G

Number of successfully transmitted frames after a single collision in Half-duplex mode [BHW]
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXSINGLECOL_G TXSINGLECOL_G read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXMULTICOL_G

Number of successfully transmitted frames after more than a single collision in Half-duplex mode [BHW]
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXMULTICOL_G TXMULTICOL_G read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXDEFERRED

Number of successfully transmitted frames after a deferral in Half-duplex mode [BHW]
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXDEFERRED TXDEFERRED read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXLATECOL

Number of frames aborted due to late collision error [BHW]
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXLATECOL TXLATECOL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXEXESSCOL

Number of frames aborted due to excessive (16) collision errors [BHW]
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXEXESSCOL TXEXESSCOL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXCARRIERERROR

Number of frames aborted due to carrier sense error (no carrier or loss of carrier). [BHW]
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXCARRIERERROR TXCARRIERERROR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXOCTETCOUNT_G

Number of bytes transmitted (exclusive of preamble) in good frames only [BHW]
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXOCTETCOUNT_G TXOCTETCOUNT_G read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXFRAMECOUNT_G

Number of good frames transmitted [BHW]
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXFRAMECOUNT_G TXFRAMECOUNT_G read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXEXECESSDEF_G

Number of frames aborted due to excessive deferral error (deferred for more than two max-sized frame times) [BHW]
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXEXECESSDEF_G TXEXECESSDEF_G read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXPAUSEFRAMES

Number of good PAUSE frames transmitted [BHW]
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXPAUSEFRAMES TXPAUSEFRAMES read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TXVLANFRAMES_G

Number of good VLAN frames transmitted exclusive of retried frames [BHW]
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXVLANFRAMES_G TXVLANFRAMES_G read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FCR

Flow Control Register [BHW]
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCR FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCB_BPA TFE RFE UP PLT DZPQ PT

FCB_BPA : Flow Control Busy/Backpressure Activate
bits : 0 - -1 (0 bit)
access : read-write

TFE : Transmit Flow Control Enable
bits : 1 - 0 (0 bit)
access : read-write

RFE : Receive Flow Control Enable
bits : 2 - 1 (0 bit)
access : read-write

UP : Unicast Pause Frame detect
bits : 3 - 2 (0 bit)
access : read-write

PLT : Pause Low Threshold
bits : 4 - 4 (1 bit)
access : read-write

DZPQ : Disable Zero-Quanta Pause
bits : 7 - 6 (0 bit)
access : read-write

PT : Pause Time
bits : 16 - 30 (15 bit)
access : read-write


RXFRAMECOUNT_GB

Number of good and bad frames received [BHW]
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXFRAMECOUNT_GB RXFRAMECOUNT_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXOCTETCOUNT_GB

Number of bytes received (exclusive of preamble) in good and bad frames. [BHW]
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXOCTETCOUNT_GB RXOCTETCOUNT_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXOCTETCOUNT_G

Number of bytes received (exclusive of preamble) only in good frames [BHW]
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXOCTETCOUNT_G RXOCTETCOUNT_G read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXBROADCASTFRAMES_G

Number of good broadcast frames received [BHW]
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXBROADCASTFRAMES_G RXBROADCASTFRAMES_G read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXMULTICASTFRAMES_G

Number of good multicast frames received [BHW]
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXMULTICASTFRAMES_G RXMULTICASTFRAMES_G read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXCRCERROR

Number of frames received with CRC error[BHW]
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXCRCERROR RXCRCERROR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXALLIGNMENTERROR

Number of frames received with alignment (dribble) error. Valid only in 10/100 mode [BHW]
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXALLIGNMENTERROR RXALLIGNMENTERROR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXRUNTERROR

Number of frames received with runt (64 bytes and CRC error) error [BHW]
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXRUNTERROR RXRUNTERROR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXJABBERERROR

Number of frames received with length greater than 1518 bytes with CRC error [BHW]
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXJABBERERROR RXJABBERERROR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXUNDERSIZE_G

Number of frames received with length less than 64 bytes without any errors. [BHW]
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXUNDERSIZE_G RXUNDERSIZE_G read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXOVERSIZE_G

Number of frames received with length greater than the maxsize without error [BHW]
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXOVERSIZE_G RXOVERSIZE_G read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RX64OCTETS_GB

Number of good and bad frames received with length 64 bytes exclusive of preamble [BHW]
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX64OCTETS_GB RX64OCTETS_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RX65TO127OCTETS_GB

Number of good and bad frames received with length between 65 and 127 (inclusive) bytes exclusive of preamble. [BHW]
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX65TO127OCTETS_GB RX65TO127OCTETS_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RX128TO255OCTETS_GB

Number of good and bad frames received with length between 128 and 255 (inclusive) bytes exclusive of preamble. [BHW]
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX128TO255OCTETS_GB RX128TO255OCTETS_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RX256TO511OCTETS_GB

Number of good and bad frames received with length between 256 and 511 (inclusive) bytes exclusive of preamble. [BHW]
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX256TO511OCTETS_GB RX256TO511OCTETS_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RX512TO1023OCTETS_GB

Number of good and bad frames received with length between 512 and 1023 (inclusive) bytes exclusive of preamble. [BHW]
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX512TO1023OCTETS_GB RX512TO1023OCTETS_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VTR

VLAN TAG Register [BHW]
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VTR VTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VL ETV

VL : VLAN Tag Identifier
bits : 0 - 14 (15 bit)
access : read-write

ETV : Enable 12-Bit VLAN Tag Comparison
bits : 16 - 15 (0 bit)
access : read-write


RX1024TOMAXOCTETS_GB

Number of good and bad frames received with length between 1024 and maxsize (inclusive) bytes exclusive of preamble [BHW]
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX1024TOMAXOCTETS_GB RX1024TOMAXOCTETS_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXUNICASTFRAMES_G

Number of good unicast frames received [BHW]
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXUNICASTFRAMES_G RXUNICASTFRAMES_G read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXLENGTHERROR

Number of frames received with length error (Length type field is not the frame size) for all frames with valid length field [BHW]
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXLENGTHERROR RXLENGTHERROR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXOUTOFRANGETYPE

Number of frames received with length/type field not equal to the valid frame size (Greater than 1500) [BHW]
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXOUTOFRANGETYPE RXOUTOFRANGETYPE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXPAUSEFRAMES

Number of good and valid PAUSE frames received [BHW]
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXPAUSEFRAMES RXPAUSEFRAMES read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXFIFOOVERFLOW

Number of missed received frames due to FIFO overflow [BHW]
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXFIFOOVERFLOW RXFIFOOVERFLOW read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXVLANFRAMES_GB

Number of good and bad VLAN frames received [BHW]
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXVLANFRAMES_GB RXVLANFRAMES_GB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXWATCHDOGERROR

Number of frames received with error due to watchdog timeout error (frames with a data load larger than 2048 bytes) [BHW]
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXWATCHDOGERROR RXWATCHDOGERROR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MMC_IPC_INTR_MASK_RX

MMC Receive Checksum Offload Interrupt Mask Register [BHW]
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMC_IPC_INTR_MASK_RX MMC_IPC_INTR_MASK_RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BL BH

BL : Lower bits of MMC_IPC_INTR_MASK_RX
bits : 0 - 12 (13 bit)
access : read-write

BH : Higher bits of MMC_IPC_INTR_MASK_RX
bits : 16 - 28 (13 bit)
access : read-write


MMC_IPC_INTR_RX

MMC Receive Checksum Offload Interrupt Register [BHW]
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMC_IPC_INTR_RX MMC_IPC_INTR_RX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BL BH

BL : Lower bits of MMC_IPC_INTR_RX
bits : 0 - 12 (13 bit)
access : read-write

BH : Higher bits of MMC_IPC_INTR_RX
bits : 16 - 28 (13 bit)
access : read-write


RXIPV4_GD_FRMS

Number of good IPv4 datagrams received with the TCP/UDP or ICMP payload [BHW]
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV4_GD_FRMS RXIPV4_GD_FRMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV4_HDRERR_FRMS

Number of IPv4 datagrams received with header errors (checksum/length or version mismatch) [BHW]
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV4_HDRERR_FRMS RXIPV4_HDRERR_FRMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV4_NOPAY_FRMS

Number of IPv4 datagram frames received that did not have a TCP/UDP or ICMP payload processed by the Checksum engine [BHW]
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV4_NOPAY_FRMS RXIPV4_NOPAY_FRMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV4_FRAG_FRMS

Number of good IPv4 datagrams with fragmentation [BHW]
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV4_FRAG_FRMS RXIPV4_FRAG_FRMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV4_UDSBL_FRMS

Number of good IPv4 datagrams received that had a UDP payload with checksum disabled [BHW]
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV4_UDSBL_FRMS RXIPV4_UDSBL_FRMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV6_GD_FRMS

Number of good IPv6 datagrams received with TCP/UDP or ICMP payloads [BHW]
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV6_GD_FRMS RXIPV6_GD_FRMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV6_HDRERR_FRMS

Number of IPv6 datagrams received with header errors (length or version mismatch) [BHW]
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV6_HDRERR_FRMS RXIPV6_HDRERR_FRMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV6_NOPAY_FRMS

Number of IPv6 datagram frames received that did not have a TCP/UDP or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers [BHW]
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV6_NOPAY_FRMS RXIPV6_NOPAY_FRMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXUDP_GD_FRMS

Number of good IP datagrams with a good UDP payload. This counter is not updated when the rxipv4_udsbl_frms counter is incremented [BHW]
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXUDP_GD_FRMS RXUDP_GD_FRMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXUDP_ERR_FRMS

Number of good IP datagrams whose UDP payload has a checksum error [BHW]
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXUDP_ERR_FRMS RXUDP_ERR_FRMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXTCP_GD_FRMS

Number of good IP datagrams with a good TCP payload [BHW]
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXTCP_GD_FRMS RXTCP_GD_FRMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXTCP_ERR_FRMS

Number of good IP datagrams whose TCP payload has a checksum error [BHW]
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXTCP_ERR_FRMS RXTCP_ERR_FRMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXICMP_GD_FRMS

Number of good IP datagrams with a good ICMP payload [BHW]
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXICMP_GD_FRMS RXICMP_GD_FRMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXICMP_ERR_FRMS

Number of good IP datagrams whose ICMP payload has a checksum error [BHW]
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXICMP_ERR_FRMS RXICMP_ERR_FRMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV4_GD_OCTETS

Number of bytes received in good IPv4 datagrams encapsulating TCP/UDP or ICMP data. (Ethernet header/FCS/pad or IP pad bytes are not included in this counter or in the octet counters listed below). [BHW]
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV4_GD_OCTETS RXIPV4_GD_OCTETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV4_HDRERR_OCTETS

Number of bytes received in IPv4 datagrams with header errors (checksum/length version mismatch). The value in the Length field of IPv4 header is used to update this counter [BHW]
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV4_HDRERR_OCTETS RXIPV4_HDRERR_OCTETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV4_NOPAY_OCTETS

Number of bytes received in IPv4 datagrams that did not have a TCP/UDP or ICMP payload. The value in the IPv4 header's Length field is used to update this counter [BHW]
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV4_NOPAY_OCTETS RXIPV4_NOPAY_OCTETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV4_FRAG_OCTETS

Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 header's Length field is used to update this counter [BHW]
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV4_FRAG_OCTETS RXIPV4_FRAG_OCTETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV4_UDSBL_OCTETS

Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes [BHW]
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV4_UDSBL_OCTETS RXIPV4_UDSBL_OCTETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV6_GD_OCTETS

Number of bytes received in good IPv6 datagrams encapsulating TCP/UDP or ICMPv6 data [BHW]
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV6_GD_OCTETS RXIPV6_GD_OCTETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV6_HDRERR_OCTETS

Number of bytes received in IPv6 datagrams with header errors (length/version mismatch). The value in the IPv6 header's Length field is used to update this counter. [BHW]
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV6_HDRERR_OCTETS RXIPV6_HDRERR_OCTETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXIPV6_NOPAY_OCTETS

Number of bytes received in IPv6 datagrams that did not have a TCP/UDP or ICMP payload. The value in the IPv6 header's Length field is used to update this counter [BHW]
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXIPV6_NOPAY_OCTETS RXIPV6_NOPAY_OCTETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXUDP_GD_OCTETS

Number of bytes received in a good UDP segment. This counter (and the counters below) does not count IP header bytes [BHW]
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXUDP_GD_OCTETS RXUDP_GD_OCTETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXUDP_ERR_OCTETS

Number of bytes received in a UDP segment that had checksum errors [BHW]
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXUDP_ERR_OCTETS RXUDP_ERR_OCTETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXTCP_GD_OCTETS

Number of bytes received in a good TCP segment [BHW]
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXTCP_GD_OCTETS RXTCP_GD_OCTETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXTCP_ERR_OCTETS

Number of bytes received in a TCP segment with checksum errors [BHW]
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXTCP_ERR_OCTETS RXTCP_ERR_OCTETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RWFFR

Remote Wake-up Frame Filter Register [BHW]
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RWFFR RWFFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWFFR

RWFFR : Remote Wake-up Frame Filter Register
bits : 0 - 30 (31 bit)
access : read-write


RXICMP_GD_OCTETS

Number of bytes received in a good ICMP segment [BHW]
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXICMP_GD_OCTETS RXICMP_GD_OCTETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXICMP_ERR_OCTETS

Number of bytes received in an ICMP segment with checksum errors [BHW]
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXICMP_ERR_OCTETS RXICMP_ERR_OCTETS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PMTR

PMT Register [BHW]
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMTR PMTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD MPE WFE MPR WPR GU RWFFRPR

PD : Power Down
bits : 0 - -1 (0 bit)
access : read-write

MPE : Magic Packet Enable
bits : 1 - 0 (0 bit)
access : read-write

WFE : Wake-Up Frame Enable
bits : 2 - 1 (0 bit)
access : read-write

MPR : Magic Packet Received
bits : 5 - 4 (0 bit)
access : read-only

WPR : Wake Up Frame Receive
bits : 6 - 5 (0 bit)
access : read-only

GU : Global Unicast
bits : 9 - 8 (0 bit)
access : read-write

RWFFRPR : Remote Wake-up Frame Filter Register Pointer Reset
bits : 31 - 30 (0 bit)
access : read-write


LPICSR

LPI Control and Status Register [BHW]
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPICSR LPICSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TLPIEN TLPIEX RLPIEN RLPIEX TLPIST RLPIST LPIEN PLS PLSEN LPITXA

TLPIEN : Transmit LPI Entry
bits : 0 - -1 (0 bit)
access : read-only

TLPIEX : Transmit LPI Exit
bits : 1 - 0 (0 bit)
access : read-only

RLPIEN : Receive LPI Entry
bits : 2 - 1 (0 bit)
access : read-only

RLPIEX : Receive LPI Exit
bits : 3 - 2 (0 bit)
access : read-only

TLPIST : Transmit LPI State
bits : 8 - 7 (0 bit)
access : read-only

RLPIST : Receive LPI State
bits : 9 - 8 (0 bit)
access : read-only

LPIEN : LPI Enable
bits : 16 - 15 (0 bit)
access : read-write

PLS : PHY Link Status
bits : 17 - 16 (0 bit)
access : read-write

PLSEN : PHY Link Status Enable
bits : 18 - 17 (0 bit)
access : read-write

LPITXA : LPI TX Automate
bits : 19 - 18 (0 bit)
access : read-write


LPITCR

LPI Timers Control Register [BHW]
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPITCR LPITCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TWT LIT

TWT : LPI TW TIMER
bits : 0 - 14 (15 bit)
access : read-write

LIT : LPI LS TIMER
bits : 16 - 24 (9 bit)
access : read-write


ISR

Interrupt Status Register [BHW]
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGIS PIS MIS RIS TIS COIS TSIS LPIIS

RGIS : RGMII Interrupt Status
bits : 0 - -1 (0 bit)
access : read-only

PIS : PMT Interrupt Status
bits : 3 - 2 (0 bit)
access : read-only

MIS : MMC Interrupt Status
bits : 4 - 3 (0 bit)
access : read-only

RIS : MMC Receive Interrupt Status
bits : 5 - 4 (0 bit)
access : read-only

TIS : MMC Transmit Interrupt Status
bits : 6 - 5 (0 bit)
access : read-only

COIS : MMC Receive Checksum Offload Interrupt Status
bits : 7 - 6 (0 bit)
access : read-only

TSIS : Time Stamp Interrupt Status
bits : 9 - 8 (0 bit)
access : read-only

LPIIS : LPI Interrupt Status
bits : 10 - 9 (0 bit)
access : read-only


IMR

Interrupt Mask Register [BHW]
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGIM PIM TSIM LPIIM

RGIM : RGMII Interrupt Mask
bits : 0 - -1 (0 bit)
access : read-write

PIM : PMT Interrupt Mask
bits : 3 - 2 (0 bit)
access : read-write

TSIM : Time Stamp Interrupt Mask
bits : 9 - 8 (0 bit)
access : read-write

LPIIM : LPI Interrupt Mask
bits : 10 - 9 (0 bit)
access : read-write


MFFR

MAC Frame Filter Register [BHW]
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MFFR MFFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PR HUC HMC DAIF PM DB PCF SAIF SAF HPF RA

PR : Promiscuous Mode
bits : 0 - -1 (0 bit)
access : read-write

HUC : Hash Unicast
bits : 1 - 0 (0 bit)
access : read-write

HMC : Hash Multicast
bits : 2 - 1 (0 bit)
access : read-write

DAIF : DA Inverse Filtering
bits : 3 - 2 (0 bit)
access : read-write

PM : Pass All Multicast
bits : 4 - 3 (0 bit)
access : read-write

DB : Disable Broadcast Frames
bits : 5 - 4 (0 bit)
access : read-write

PCF : Pass Control Frames
bits : 6 - 6 (1 bit)
access : read-write

SAIF : Source Address Inverse Filter
bits : 8 - 7 (0 bit)
access : read-write

SAF : Source Address Filter
bits : 9 - 8 (0 bit)
access : read-write

HPF : Hash or Perfect Filter
bits : 10 - 9 (0 bit)
access : read-write

RA : Receive All
bits : 31 - 30 (0 bit)
access : read-write


MAR0H

MAC Address0 Register (High) [BHW]
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR0H MAR0H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0 MO

A0 : MAC Address0
bits : 0 - 14 (15 bit)
access : read-write

MO : Must be one
bits : 31 - 30 (0 bit)
access : read-only


MAR0L

MAC Address0 Register (Low) [BHW]
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR0L MAR0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A0

A0 : MAC Address0
bits : 0 - 30 (31 bit)
access : read-write


MAR1H

MAC Address1 Register -High [BHW]
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR1H MAR1H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A MBC SA AE

A : MAC Address
bits : 0 - 14 (15 bit)
access : read-write

MBC : Mask Byte Control
bits : 24 - 28 (5 bit)
access : read-write

SA : Source Address
bits : 30 - 29 (0 bit)
access : read-write

AE : Address Enable
bits : 31 - 30 (0 bit)
access : read-write


MAR1L

MAC Address1 Register -Low [BHW]
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR1L MAR1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A

A : MAC Address
bits : 0 - 30 (31 bit)
access : read-write


MAR2H

MAC Address2 Register -High [BHW]
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR2H MAR2H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR2L

MAC Address2 Register -Low [BHW]
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR2L MAR2L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR3H

MAC Address3 Register -High [BHW]
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR3H MAR3H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR3L

MAC Address3 Register -Low [BHW]
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR3L MAR3L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR4H

MAC Address4 Register -High [BHW]
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR4H MAR4H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR4L

MAC Address4 Register -Low [BHW]
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR4L MAR4L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR5H

MAC Address5 Register -High [BHW]
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR5H MAR5H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR5L

MAC Address5 Register -Low [BHW]
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR5L MAR5L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR6H

MAC Address6 Register -High [BHW]
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR6H MAR6H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TSCR

Time Stamp Control Register [BHW]
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSCR TSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSE TFCU TSI TSU TITE TARU TSEA TSDB TSV2E TETSP TSIP6E TSIP4E TETSEM TSMRM TSPS TSENMF ATSFC

TSE : Time Stamp Enable
bits : 0 - -1 (0 bit)
access : read-write

TFCU : Time Stamp Fine or Coarse Update
bits : 1 - 0 (0 bit)
access : read-write

TSI : Time Stamp Initialize
bits : 2 - 1 (0 bit)
access : read-write

TSU : Time Stamp Update
bits : 3 - 2 (0 bit)
access : read-write

TITE : Time Stamp Interrupt Trigger Enable
bits : 4 - 3 (0 bit)
access : read-write

TARU : Addend Register Update
bits : 5 - 4 (0 bit)
access : read-write

TSEA : Enable Time Stamp for All Frames
bits : 8 - 7 (0 bit)
access : read-write

TSDB : Time Stamp Digital or Binary rollover control
bits : 9 - 8 (0 bit)
access : read-write

TSV2E : Enable PTP packet snooping for version 2 format
bits : 10 - 9 (0 bit)
access : read-write

TETSP : Enable Time Stamp Snapshot for PTP over Ethernet frames
bits : 11 - 10 (0 bit)
access : read-write

TSIP6E : Enable Time Stamp Snapshot for IPv6 frames
bits : 12 - 11 (0 bit)
access : read-write

TSIP4E : Enable Time Stamp Snapshot for IPv4 frames
bits : 13 - 12 (0 bit)
access : read-write

TETSEM : Enable Time Stamp Snapshot for Event Messages
bits : 14 - 13 (0 bit)
access : read-write

TSMRM : Enable Snapshot for Messages Relevant to Master
bits : 15 - 14 (0 bit)
access : read-write

TSPS : SelectPTP packets for taking snapshots
bits : 16 - 16 (1 bit)
access : read-write

TSENMF : Enable MAC address for PTP frame filtering
bits : 18 - 17 (0 bit)
access : read-write

ATSFC : Auxiliary Snapshot FIFO Clear
bits : 24 - 23 (0 bit)
access : read-write


SSIR

Sub-Second Increment Register [BHW]
address_offset : 0x704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSIR SSIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSINC

SSINC : Sub-Second Increment Value
bits : 0 - 6 (7 bit)
access : read-write


STSR

System Time - Seconds Register [BHW]
address_offset : 0x708 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STSR STSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSS

TSS : Time Stamp Second
bits : 0 - 30 (31 bit)
access : read-only


STNR

System Time - Nanoseconds Register [BHW]
address_offset : 0x70C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STNR STNR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSSS

TSSS : Time Stamp Sub-Seconds
bits : 0 - 29 (30 bit)
access : read-only


STSUR

System Time - Seconds Update Register [BHW]
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STSUR STSUR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSS

TSS : Time Stamp Second
bits : 0 - 30 (31 bit)
access : read-write


STNUR

System Time - Nanoseconds Update Register [BHW]
address_offset : 0x714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STNUR STNUR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSSS ADDSUB

TSSS : Time Stamp Sub-Seconds
bits : 0 - 29 (30 bit)
access : read-write

ADDSUB : Add or Subtract Time
bits : 31 - 30 (0 bit)
access : read-write


TSAR

Time Stamp Addend Register [BHW]
address_offset : 0x718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSAR TSAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSAR

TSAR : Time Stamp Addend Register
bits : 0 - 30 (31 bit)
access : read-write


TTSR

Target Time Seconds Register [BHW]
address_offset : 0x71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TTSR TTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSTR

TSTR : Target Time Stamp Seconds Register
bits : 0 - 30 (31 bit)
access : read-write


TTNR

Target Time Nanoseconds Register [BHW]
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TTNR TTNR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSTR

TSTR : Target Time Stamp Nanoseconds Register
bits : 0 - 29 (30 bit)
access : read-write


STHWSR

System Time - Higher Word Seconds Register [BHW]
address_offset : 0x724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STHWSR STHWSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSHWR

TSHWR : Time Stamp Higher Word Register
bits : 0 - 14 (15 bit)
access : read-write


TSR

Time Stamp Status Register [BHW]
address_offset : 0x728 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TSR TSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSSOVF TSTART ATSTS TRGTER ATSSTM ATSNS

TSSOVF : Time Stamp Seconds Overflow
bits : 0 - -1 (0 bit)
access : read-only

TSTART : Time Stamp Target Time Reached
bits : 1 - 0 (0 bit)
access : read-only

ATSTS : Auxiliary Time Stamp Trigger Snapshot
bits : 2 - 1 (0 bit)
access : read-only

TRGTER : Timestamp Target Time Error
bits : 3 - 2 (0 bit)
access : read-only

ATSSTM : Auxiliary Time Stamp Snapshot Trigger Missed
bits : 24 - 23 (0 bit)
access : read-only

ATSNS : Auxiliary Time Stamp Number of Snapshots
bits : 25 - 26 (2 bit)
access : read-only


PPSCR

PPS Control Register [BHW]
address_offset : 0x72C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PPSCR PPSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PPSCTRL

PPSCTRL : Controls the frequency of the PPS output
bits : 0 - 2 (3 bit)
access : read-write


ATNR

Auxiliary Time Stamp - Nanoseconds Register [BHW]
address_offset : 0x730 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ATNR ATNR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATN

ATN : ATN
bits : 0 - 29 (30 bit)
access : read-only


ATSR

Auxiliary Time Stamp - Seconds Register [BHW]
address_offset : 0x734 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ATSR ATSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATS

ATS : ATS
bits : 0 - 30 (31 bit)
access : read-only


MAR6L

MAC Address6 Register -Low [BHW]
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR6L MAR6L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR7H

MAC Address7 Register -High [BHW]
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR7H MAR7H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR7L

MAC Address7 Register -Low [BHW]
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR7L MAR7L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MHTRH

MAC Hash Table Register (High) [BHW]
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MHTRH MHTRH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTH

HTH : the upper 32 bits of the hash table in the HTH
bits : 0 - 30 (31 bit)
access : read-write


MAR8H

MAC Address8 Register -High [BHW]
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR8H MAR8H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR16H

MAC Address16 Register -High [BHW]
address_offset : 0x800 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR16H MAR16H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR16L

MAC Address16 Register -Low [BHW]
address_offset : 0x804 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR16L MAR16L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR17H

MAC Address17 Register -High [BHW]
address_offset : 0x808 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR17H MAR17H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR17L

MAC Address17 Register -Low [BHW]
address_offset : 0x80C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR17L MAR17L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR18H

MAC Address18 Register -High [BHW]
address_offset : 0x810 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR18H MAR18H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR18L

MAC Address18 Register -Low [BHW]
address_offset : 0x814 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR18L MAR18L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR19H

MAC Address19 Register -High [BHW]
address_offset : 0x818 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR19H MAR19H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR19L

MAC Address19 Register -Low [BHW]
address_offset : 0x81C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR19L MAR19L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR20H

MAC Address20 Register -High [BHW]
address_offset : 0x820 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR20H MAR20H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR20L

MAC Address20 Register -Low [BHW]
address_offset : 0x824 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR20L MAR20L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR21H

MAC Address21 Register -High [BHW]
address_offset : 0x828 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR21H MAR21H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR21L

MAC Address21 Register -Low [BHW]
address_offset : 0x82C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR21L MAR21L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR22H

MAC Address22 Register -High [BHW]
address_offset : 0x830 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR22H MAR22H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR22L

MAC Address22 Register -Low [BHW]
address_offset : 0x834 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR22L MAR22L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR23H

MAC Address23 Register -High [BHW]
address_offset : 0x838 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR23H MAR23H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR23L

MAC Address23 Register -Low [BHW]
address_offset : 0x83C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR23L MAR23L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR8L

MAC Address8 Register -Low [BHW]
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR8L MAR8L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR24H

MAC Address24 Register -High [BHW]
address_offset : 0x840 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR24H MAR24H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR24L

MAC Address24 Register -Low [BHW]
address_offset : 0x844 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR24L MAR24L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR25H

MAC Address25 Register -High [BHW]
address_offset : 0x848 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR25H MAR25H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR25L

MAC Address25 Register -Low [BHW]
address_offset : 0x84C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR25L MAR25L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR26H

MAC Address26 Register -High [BHW]
address_offset : 0x850 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR26H MAR26H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR26L

MAC Address26 Register -Low [BHW]
address_offset : 0x854 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR26L MAR26L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR27H

MAC Address27 Register -High [BHW]
address_offset : 0x858 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR27H MAR27H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR27L

MAC Address27 Register -Low [BHW]
address_offset : 0x85C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR27L MAR27L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR28H

MAC Address28 Register -High [BHW]
address_offset : 0x860 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR28H MAR28H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR28L

MAC Address28 Register -Low [BHW]
address_offset : 0x864 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR28L MAR28L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR29H

MAC Address29 Register -High [BHW]
address_offset : 0x868 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR29H MAR29H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR29L

MAC Address29 Register -Low [BHW]
address_offset : 0x86C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR29L MAR29L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR30H

MAC Address30 Register -High [BHW]
address_offset : 0x870 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR30H MAR30H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR30L

MAC Address30 Register -Low [BHW]
address_offset : 0x874 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR30L MAR30L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR31H

MAC Address31 Register -High [BHW]
address_offset : 0x878 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR31H MAR31H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR31L

MAC Address31 Register -Low [BHW]
address_offset : 0x87C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR31L MAR31L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR9H

MAC Address9 Register -High [BHW]
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR9H MAR9H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR9L

MAC Address9 Register -Low [BHW]
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR9L MAR9L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR10H

MAC Address10 Register -High [BHW]
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR10H MAR10H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR10L

MAC Address10 Register -Low [BHW]
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR10L MAR10L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR11H

MAC Address11 Register -High [BHW]
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR11H MAR11H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR11L

MAC Address11 Register -Low [BHW]
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR11L MAR11L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR12H

MAC Address12 Register -High [BHW]
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR12H MAR12H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR12L

MAC Address12 Register -Low [BHW]
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR12L MAR12L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR13H

MAC Address13 Register -High [BHW]
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR13H MAR13H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR13L

MAC Address13 Register -Low [BHW]
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR13L MAR13L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR14H

MAC Address14 Register -High [BHW]
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR14H MAR14H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR14L

MAC Address14 Register -Low [BHW]
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR14L MAR14L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR15H

MAC Address15 Register -High [BHW]
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR15H MAR15H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAR15L

MAC Address15 Register -Low [BHW]
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAR15L MAR15L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MHTRL

MAC Hash Table Register (Low) [BHW]
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MHTRL MHTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTL

HTL : the lower 32 bits of the hash table in the HTL
bits : 0 - 30 (31 bit)
access : read-write


RGSR

RGMII Status Register) [BHW]
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RGSR RGSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LM LSP LS

LM : Link Mode
bits : 0 - -1 (0 bit)
access : read-only

LSP : Link Speed
bits : 1 - 1 (1 bit)
access : read-only

LS : Link Status
bits : 3 - 2 (0 bit)
access : read-only



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