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ETHERNET_CONTROL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ETH_MODE

ETH_CLKG


ETH_MODE

Mode Select Register [BHW]
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_MODE ETH_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFMODE RST0 RST1 PPSSEL

IFMODE : Mode selector
bits : 0 - -1 (0 bit)
access : read-write

RST0 : reset signal against Ethernet-MAC (ch.0)
bits : 8 - 7 (0 bit)
access : read-write

RST1 : reset signal against Ethernet-MAC (ch.1)
bits : 9 - 8 (0 bit)
access : read-write

PPSSEL : Select either of the system time counter pulse outputs of the Ethernet-MAC PTP function to output to E_PPS0_PPS1 pin
bits : 28 - 27 (0 bit)
access : read-write


ETH_CLKG

Clock Gating Register [BHW]
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETH_CLKG ETH_CLKG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACEN

MACEN : Select the system clock supply to Ethernet-MAC
bits : 0 - 0 (1 bit)
access : read-write



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