\n
address_offset : 0x0 Bytes (0x0)
size : 0x1 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
CRC Control Register [BHW]
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initialization bit
bits : 0 - -1 (0 bit)
access : read-write
CRC32 : CRC mode selection bit
bits : 1 - 0 (0 bit)
access : read-write
LTLEND : Byte-order setting bit
bits : 2 - 1 (0 bit)
access : read-write
LSBFST : Bit-order setting bit
bits : 3 - 2 (0 bit)
access : read-write
CRCLTE : CRC result byte-order setting bit
bits : 4 - 3 (0 bit)
access : read-write
CRCLSF : CRC result bit-order setting bit
bits : 5 - 4 (0 bit)
access : read-write
FXOR : Final XOR control bit
bits : 6 - 5 (0 bit)
access : read-write
Initial Value Register [BHW]
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D : Initial value
bits : 0 - 30 (31 bit)
access : read-write
Input Data Register [BHW]
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D : Input data
bits : 0 - 30 (31 bit)
access : read-write
CRC Register [BHW]
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
D : CRC Data
bits : 0 - 30 (31 bit)
access : read-only
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