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GPMI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x134 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL0

COMPARE

READ_DDR_DLL_CTRL

WRITE_DDR_DLL_CTRL

READ_DDR_DLL_STS

WRITE_DDR_DLL_STS

ECCCTRL

ECCCTRL_SET

ECCCTRL_CLR

ECCCTRL_TOG

ECCCOUNT

CTRL0_SET

PAYLOAD

AUXILIARY

CTRL1

CTRL1_SET

CTRL1_CLR

CTRL1_TOG

TIMING0

CTRL0_CLR

TIMING1

TIMING2

DATA

STAT

CTRL0_TOG

DEBUG

VERSION

DEBUG2

DEBUG3


CTRL0

GPMI Control Register 0 Description
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0 CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFER_COUNT ADDRESS_INCREMENT ADDRESS CS WORD_LENGTH COMMAND_MODE UDMA LOCK_CS DEV_IRQ_EN RUN CLKGATE SFTRST

XFER_COUNT : no description available
bits : 0 - 15 (16 bit)
access : read-write

ADDRESS_INCREMENT : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Address does not increment.

#1 : 1

Increment address.

End of enumeration elements list.

ADDRESS : no description available
bits : 17 - 19 (3 bit)
access : read-write

CS : no description available
bits : 20 - 22 (3 bit)
access : read-write

WORD_LENGTH : no description available
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#1 : 1

8-bit Data Bus mode.

End of enumeration elements list.

COMMAND_MODE : no description available
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

Write mode.

#01 : 01

Read Mode.

#10 : 10

Read and Compare Mode (setting sense flop).

#11 : 11

Wait for Ready.

End of enumeration elements list.

UDMA : no description available
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Use ATA-PIO mode on the external bus.

#1 : 1

Use ATA-Ultra DMA mode on the external bus.

End of enumeration elements list.

LOCK_CS : no description available
bits : 27 - 27 (1 bit)
access : read-write

DEV_IRQ_EN : no description available
bits : 28 - 28 (1 bit)
access : read-write

RUN : no description available
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write

SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write


COMPARE

GPMI Compare Register Description
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPARE COMPARE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFERENCE MASK

REFERENCE : no description available
bits : 0 - 15 (16 bit)
access : read-write

MASK : no description available
bits : 16 - 31 (16 bit)
access : read-write


READ_DDR_DLL_CTRL

GPMI Double Rate Read DLL Control Register Description
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READ_DDR_DLL_CTRL READ_DDR_DLL_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RESET SLV_FORCE_UPD SLV_DLY_TARGET GATE_UPDATE REFCLK_ON SLV_OVERRIDE SLV_OVERRIDE_VAL RSVD1 SLV_UPDATE_INT REF_UPDATE_INT

ENABLE : no description available
bits : 0 - 0 (1 bit)
access : read-write

RESET : no description available
bits : 1 - 1 (1 bit)
access : read-write

SLV_FORCE_UPD : no description available
bits : 2 - 2 (1 bit)
access : read-write

SLV_DLY_TARGET : no description available
bits : 3 - 6 (4 bit)
access : read-write

GATE_UPDATE : no description available
bits : 7 - 7 (1 bit)
access : read-write

REFCLK_ON : no description available
bits : 8 - 8 (1 bit)
access : read-write

SLV_OVERRIDE : no description available
bits : 9 - 9 (1 bit)
access : read-write

SLV_OVERRIDE_VAL : no description available
bits : 10 - 17 (8 bit)
access : read-write

RSVD1 : no description available
bits : 18 - 19 (2 bit)
access : read-only

SLV_UPDATE_INT : no description available
bits : 20 - 27 (8 bit)
access : read-write

REF_UPDATE_INT : no description available
bits : 28 - 31 (4 bit)
access : read-write


WRITE_DDR_DLL_CTRL

GPMI Double Rate Write DLL Control Register Description
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRITE_DDR_DLL_CTRL WRITE_DDR_DLL_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE RESET SLV_FORCE_UPD SLV_DLY_TARGET GATE_UPDATE REFCLK_ON SLV_OVERRIDE SLV_OVERRIDE_VAL RSVD1 SLV_UPDATE_INT REF_UPDATE_INT

ENABLE : no description available
bits : 0 - 0 (1 bit)
access : read-write

RESET : no description available
bits : 1 - 1 (1 bit)
access : read-write

SLV_FORCE_UPD : no description available
bits : 2 - 2 (1 bit)
access : read-write

SLV_DLY_TARGET : no description available
bits : 3 - 6 (4 bit)
access : read-write

GATE_UPDATE : no description available
bits : 7 - 7 (1 bit)
access : read-write

REFCLK_ON : no description available
bits : 8 - 8 (1 bit)
access : read-write

SLV_OVERRIDE : no description available
bits : 9 - 9 (1 bit)
access : read-write

SLV_OVERRIDE_VAL : no description available
bits : 10 - 17 (8 bit)
access : read-write

RSVD1 : no description available
bits : 18 - 19 (2 bit)
access : read-only

SLV_UPDATE_INT : no description available
bits : 20 - 27 (8 bit)
access : read-write

REF_UPDATE_INT : no description available
bits : 28 - 31 (4 bit)
access : read-write


READ_DDR_DLL_STS

GPMI Double Rate Read DLL Status Register Description
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

READ_DDR_DLL_STS READ_DDR_DLL_STS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLV_LOCK SLV_SEL RSVD0 REF_LOCK REF_SEL RSVD1

SLV_LOCK : no description available
bits : 0 - 0 (1 bit)
access : read-only

SLV_SEL : no description available
bits : 1 - 8 (8 bit)
access : read-only

RSVD0 : no description available
bits : 9 - 15 (7 bit)
access : read-only

REF_LOCK : no description available
bits : 16 - 16 (1 bit)
access : read-only

REF_SEL : no description available
bits : 17 - 24 (8 bit)
access : read-only

RSVD1 : no description available
bits : 25 - 31 (7 bit)
access : read-only


WRITE_DDR_DLL_STS

GPMI Double Rate Write DLL Status Register Description
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WRITE_DDR_DLL_STS WRITE_DDR_DLL_STS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLV_LOCK SLV_SEL RSVD0 REF_LOCK REF_SEL RSVD1

SLV_LOCK : no description available
bits : 0 - 0 (1 bit)
access : read-only

SLV_SEL : no description available
bits : 1 - 8 (8 bit)
access : read-only

RSVD0 : no description available
bits : 9 - 15 (7 bit)
access : read-only

REF_LOCK : no description available
bits : 16 - 16 (1 bit)
access : read-only

REF_SEL : no description available
bits : 17 - 24 (8 bit)
access : read-only

RSVD1 : no description available
bits : 25 - 31 (7 bit)
access : read-only


ECCCTRL

GPMI Integrated ECC Control Register Description
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCCTRL ECCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_MASK RANDOMIZER_ENABLE ENABLE_ECC ECC_CMD RSVD2 HANDLE

BUFFER_MASK : no description available
bits : 0 - 8 (9 bit)
access : read-write

RANDOMIZER_ENABLE : no description available
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

disable

#1 : 1

enable

End of enumeration elements list.

ENABLE_ECC : no description available
bits : 12 - 12 (1 bit)
access : read-write

ECC_CMD : no description available
bits : 13 - 14 (2 bit)
access : read-write

RSVD2 : no description available
bits : 15 - 15 (1 bit)
access : read-write

HANDLE : no description available
bits : 16 - 31 (16 bit)
access : read-write


ECCCTRL_SET

GPMI Integrated ECC Control Register Description
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCCTRL_SET ECCCTRL_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_MASK RANDOMIZER_ENABLE ENABLE_ECC ECC_CMD RSVD2 HANDLE

BUFFER_MASK : no description available
bits : 0 - 8 (9 bit)
access : read-write

RANDOMIZER_ENABLE : no description available
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

disable

#1 : 1

enable

End of enumeration elements list.

ENABLE_ECC : no description available
bits : 12 - 12 (1 bit)
access : read-write

ECC_CMD : no description available
bits : 13 - 14 (2 bit)
access : read-write

RSVD2 : no description available
bits : 15 - 15 (1 bit)
access : read-write

HANDLE : no description available
bits : 16 - 31 (16 bit)
access : read-write


ECCCTRL_CLR

GPMI Integrated ECC Control Register Description
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCCTRL_CLR ECCCTRL_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_MASK RANDOMIZER_ENABLE ENABLE_ECC ECC_CMD RSVD2 HANDLE

BUFFER_MASK : no description available
bits : 0 - 8 (9 bit)
access : read-write

RANDOMIZER_ENABLE : no description available
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

disable

#1 : 1

enable

End of enumeration elements list.

ENABLE_ECC : no description available
bits : 12 - 12 (1 bit)
access : read-write

ECC_CMD : no description available
bits : 13 - 14 (2 bit)
access : read-write

RSVD2 : no description available
bits : 15 - 15 (1 bit)
access : read-write

HANDLE : no description available
bits : 16 - 31 (16 bit)
access : read-write


ECCCTRL_TOG

GPMI Integrated ECC Control Register Description
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCCTRL_TOG ECCCTRL_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_MASK RANDOMIZER_ENABLE ENABLE_ECC ECC_CMD RSVD2 HANDLE

BUFFER_MASK : no description available
bits : 0 - 8 (9 bit)
access : read-write

RANDOMIZER_ENABLE : no description available
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

disable

#1 : 1

enable

End of enumeration elements list.

ENABLE_ECC : no description available
bits : 12 - 12 (1 bit)
access : read-write

ECC_CMD : no description available
bits : 13 - 14 (2 bit)
access : read-write

RSVD2 : no description available
bits : 15 - 15 (1 bit)
access : read-write

HANDLE : no description available
bits : 16 - 31 (16 bit)
access : read-write


ECCCOUNT

GPMI Integrated ECC Transfer Count Register Description
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCCOUNT ECCCOUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT RANDOMIZER_PAGE

COUNT : no description available
bits : 0 - 15 (16 bit)
access : read-write

RANDOMIZER_PAGE : no description available
bits : 16 - 23 (8 bit)
access : read-write


CTRL0_SET

GPMI Control Register 0 Description
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0_SET CTRL0_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFER_COUNT ADDRESS_INCREMENT ADDRESS CS WORD_LENGTH COMMAND_MODE UDMA LOCK_CS DEV_IRQ_EN RUN CLKGATE SFTRST

XFER_COUNT : no description available
bits : 0 - 15 (16 bit)
access : read-write

ADDRESS_INCREMENT : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Address does not increment.

#1 : 1

Increment address.

End of enumeration elements list.

ADDRESS : no description available
bits : 17 - 19 (3 bit)
access : read-write

CS : no description available
bits : 20 - 22 (3 bit)
access : read-write

WORD_LENGTH : no description available
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#1 : 1

8-bit Data Bus mode.

End of enumeration elements list.

COMMAND_MODE : no description available
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

Write mode.

#01 : 01

Read Mode.

#10 : 10

Read and Compare Mode (setting sense flop).

#11 : 11

Wait for Ready.

End of enumeration elements list.

UDMA : no description available
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Use ATA-PIO mode on the external bus.

#1 : 1

Use ATA-Ultra DMA mode on the external bus.

End of enumeration elements list.

LOCK_CS : no description available
bits : 27 - 27 (1 bit)
access : read-write

DEV_IRQ_EN : no description available
bits : 28 - 28 (1 bit)
access : read-write

RUN : no description available
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write

SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write


PAYLOAD

GPMI Payload Address Register Description
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAYLOAD PAYLOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 ADDRESS

RSVD0 : no description available
bits : 0 - 1 (2 bit)
access : read-only

ADDRESS : no description available
bits : 2 - 31 (30 bit)
access : read-write


AUXILIARY

GPMI Auxiliary Address Register Description
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUXILIARY AUXILIARY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 ADDRESS

RSVD0 : no description available
bits : 0 - 1 (2 bit)
access : read-only

ADDRESS : no description available
bits : 2 - 31 (30 bit)
access : read-write


CTRL1

GPMI Control Register 1 Description
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPMI_MODE CAMERA_MODE ATA_IRQRDY_POLARITY DEV_RESET ABORT_WAIT_FOR_READY_CHANNEL ABORT_WAIT_REQUEST BURST_EN TIMEOUT_IRQ DEV_IRQ DMA2ECC_MODE RDN_DELAY HALF_PERIOD DLL_ENABLE BCH_MODE GANGED_RDYBUSY TIMEOUT_IRQ_EN TEST_TRIGGER WRN_DLY_SEL DECOUPLE_CS SSYNCMODE UPDATE_CS GPMI_CLK_DIV2_EN TOGGLE_MODE WRITE_CLK_STOP SSYNC_CLK_STOP DEV_CLK_STOP

GPMI_MODE : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

NAND mode.

#1 : 1

ATA mode.

End of enumeration elements list.

CAMERA_MODE : no description available
bits : 1 - 1 (1 bit)
access : read-write

ATA_IRQRDY_POLARITY : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.

#1 : 1

External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.

End of enumeration elements list.

DEV_RESET : no description available
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

NANDF_WP_B pin is held low (asserted).

#1 : 1

NANDF_WP_B pin is held high (de-asserted).

End of enumeration elements list.

ABORT_WAIT_FOR_READY_CHANNEL : no description available
bits : 4 - 6 (3 bit)
access : read-write

ABORT_WAIT_REQUEST : no description available
bits : 7 - 7 (1 bit)
access : read-write

BURST_EN : no description available
bits : 8 - 8 (1 bit)
access : read-write

TIMEOUT_IRQ : no description available
bits : 9 - 9 (1 bit)
access : read-write

DEV_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write

DMA2ECC_MODE : no description available
bits : 11 - 11 (1 bit)
access : read-write

RDN_DELAY : no description available
bits : 12 - 15 (4 bit)
access : read-write

HALF_PERIOD : no description available
bits : 16 - 16 (1 bit)
access : read-write

DLL_ENABLE : no description available
bits : 17 - 17 (1 bit)
access : read-write

BCH_MODE : no description available
bits : 18 - 18 (1 bit)
access : read-write

GANGED_RDYBUSY : no description available
bits : 19 - 19 (1 bit)
access : read-write

TIMEOUT_IRQ_EN : no description available
bits : 20 - 20 (1 bit)
access : read-write

TEST_TRIGGER : no description available
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

WRN_DLY_SEL : no description available
bits : 22 - 23 (2 bit)
access : read-write

DECOUPLE_CS : no description available
bits : 24 - 24 (1 bit)
access : read-write

SSYNCMODE : no description available
bits : 25 - 25 (1 bit)
access : read-write

UPDATE_CS : no description available
bits : 26 - 26 (1 bit)
access : read-write

GPMI_CLK_DIV2_EN : no description available
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

internal factor-2 clock divider is disabled

#1 : 1

internal factor-2 clock divider is enabled.

End of enumeration elements list.

TOGGLE_MODE : no description available
bits : 28 - 28 (1 bit)
access : read-write

WRITE_CLK_STOP : no description available
bits : 29 - 29 (1 bit)
access : read-write

SSYNC_CLK_STOP : no description available
bits : 30 - 30 (1 bit)
access : read-write

DEV_CLK_STOP : no description available
bits : 31 - 31 (1 bit)
access : read-write


CTRL1_SET

GPMI Control Register 1 Description
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1_SET CTRL1_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPMI_MODE CAMERA_MODE ATA_IRQRDY_POLARITY DEV_RESET ABORT_WAIT_FOR_READY_CHANNEL ABORT_WAIT_REQUEST BURST_EN TIMEOUT_IRQ DEV_IRQ DMA2ECC_MODE RDN_DELAY HALF_PERIOD DLL_ENABLE BCH_MODE GANGED_RDYBUSY TIMEOUT_IRQ_EN TEST_TRIGGER WRN_DLY_SEL DECOUPLE_CS SSYNCMODE UPDATE_CS GPMI_CLK_DIV2_EN TOGGLE_MODE WRITE_CLK_STOP SSYNC_CLK_STOP DEV_CLK_STOP

GPMI_MODE : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

NAND mode.

#1 : 1

ATA mode.

End of enumeration elements list.

CAMERA_MODE : no description available
bits : 1 - 1 (1 bit)
access : read-write

ATA_IRQRDY_POLARITY : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.

#1 : 1

External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.

End of enumeration elements list.

DEV_RESET : no description available
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

NANDF_WP_B pin is held low (asserted).

#1 : 1

NANDF_WP_B pin is held high (de-asserted).

End of enumeration elements list.

ABORT_WAIT_FOR_READY_CHANNEL : no description available
bits : 4 - 6 (3 bit)
access : read-write

ABORT_WAIT_REQUEST : no description available
bits : 7 - 7 (1 bit)
access : read-write

BURST_EN : no description available
bits : 8 - 8 (1 bit)
access : read-write

TIMEOUT_IRQ : no description available
bits : 9 - 9 (1 bit)
access : read-write

DEV_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write

DMA2ECC_MODE : no description available
bits : 11 - 11 (1 bit)
access : read-write

RDN_DELAY : no description available
bits : 12 - 15 (4 bit)
access : read-write

HALF_PERIOD : no description available
bits : 16 - 16 (1 bit)
access : read-write

DLL_ENABLE : no description available
bits : 17 - 17 (1 bit)
access : read-write

BCH_MODE : no description available
bits : 18 - 18 (1 bit)
access : read-write

GANGED_RDYBUSY : no description available
bits : 19 - 19 (1 bit)
access : read-write

TIMEOUT_IRQ_EN : no description available
bits : 20 - 20 (1 bit)
access : read-write

TEST_TRIGGER : no description available
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

WRN_DLY_SEL : no description available
bits : 22 - 23 (2 bit)
access : read-write

DECOUPLE_CS : no description available
bits : 24 - 24 (1 bit)
access : read-write

SSYNCMODE : no description available
bits : 25 - 25 (1 bit)
access : read-write

UPDATE_CS : no description available
bits : 26 - 26 (1 bit)
access : read-write

GPMI_CLK_DIV2_EN : no description available
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

internal factor-2 clock divider is disabled

#1 : 1

internal factor-2 clock divider is enabled.

End of enumeration elements list.

TOGGLE_MODE : no description available
bits : 28 - 28 (1 bit)
access : read-write

WRITE_CLK_STOP : no description available
bits : 29 - 29 (1 bit)
access : read-write

SSYNC_CLK_STOP : no description available
bits : 30 - 30 (1 bit)
access : read-write

DEV_CLK_STOP : no description available
bits : 31 - 31 (1 bit)
access : read-write


CTRL1_CLR

GPMI Control Register 1 Description
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1_CLR CTRL1_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPMI_MODE CAMERA_MODE ATA_IRQRDY_POLARITY DEV_RESET ABORT_WAIT_FOR_READY_CHANNEL ABORT_WAIT_REQUEST BURST_EN TIMEOUT_IRQ DEV_IRQ DMA2ECC_MODE RDN_DELAY HALF_PERIOD DLL_ENABLE BCH_MODE GANGED_RDYBUSY TIMEOUT_IRQ_EN TEST_TRIGGER WRN_DLY_SEL DECOUPLE_CS SSYNCMODE UPDATE_CS GPMI_CLK_DIV2_EN TOGGLE_MODE WRITE_CLK_STOP SSYNC_CLK_STOP DEV_CLK_STOP

GPMI_MODE : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

NAND mode.

#1 : 1

ATA mode.

End of enumeration elements list.

CAMERA_MODE : no description available
bits : 1 - 1 (1 bit)
access : read-write

ATA_IRQRDY_POLARITY : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.

#1 : 1

External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.

End of enumeration elements list.

DEV_RESET : no description available
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

NANDF_WP_B pin is held low (asserted).

#1 : 1

NANDF_WP_B pin is held high (de-asserted).

End of enumeration elements list.

ABORT_WAIT_FOR_READY_CHANNEL : no description available
bits : 4 - 6 (3 bit)
access : read-write

ABORT_WAIT_REQUEST : no description available
bits : 7 - 7 (1 bit)
access : read-write

BURST_EN : no description available
bits : 8 - 8 (1 bit)
access : read-write

TIMEOUT_IRQ : no description available
bits : 9 - 9 (1 bit)
access : read-write

DEV_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write

DMA2ECC_MODE : no description available
bits : 11 - 11 (1 bit)
access : read-write

RDN_DELAY : no description available
bits : 12 - 15 (4 bit)
access : read-write

HALF_PERIOD : no description available
bits : 16 - 16 (1 bit)
access : read-write

DLL_ENABLE : no description available
bits : 17 - 17 (1 bit)
access : read-write

BCH_MODE : no description available
bits : 18 - 18 (1 bit)
access : read-write

GANGED_RDYBUSY : no description available
bits : 19 - 19 (1 bit)
access : read-write

TIMEOUT_IRQ_EN : no description available
bits : 20 - 20 (1 bit)
access : read-write

TEST_TRIGGER : no description available
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

WRN_DLY_SEL : no description available
bits : 22 - 23 (2 bit)
access : read-write

DECOUPLE_CS : no description available
bits : 24 - 24 (1 bit)
access : read-write

SSYNCMODE : no description available
bits : 25 - 25 (1 bit)
access : read-write

UPDATE_CS : no description available
bits : 26 - 26 (1 bit)
access : read-write

GPMI_CLK_DIV2_EN : no description available
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

internal factor-2 clock divider is disabled

#1 : 1

internal factor-2 clock divider is enabled.

End of enumeration elements list.

TOGGLE_MODE : no description available
bits : 28 - 28 (1 bit)
access : read-write

WRITE_CLK_STOP : no description available
bits : 29 - 29 (1 bit)
access : read-write

SSYNC_CLK_STOP : no description available
bits : 30 - 30 (1 bit)
access : read-write

DEV_CLK_STOP : no description available
bits : 31 - 31 (1 bit)
access : read-write


CTRL1_TOG

GPMI Control Register 1 Description
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1_TOG CTRL1_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPMI_MODE CAMERA_MODE ATA_IRQRDY_POLARITY DEV_RESET ABORT_WAIT_FOR_READY_CHANNEL ABORT_WAIT_REQUEST BURST_EN TIMEOUT_IRQ DEV_IRQ DMA2ECC_MODE RDN_DELAY HALF_PERIOD DLL_ENABLE BCH_MODE GANGED_RDYBUSY TIMEOUT_IRQ_EN TEST_TRIGGER WRN_DLY_SEL DECOUPLE_CS SSYNCMODE UPDATE_CS GPMI_CLK_DIV2_EN TOGGLE_MODE WRITE_CLK_STOP SSYNC_CLK_STOP DEV_CLK_STOP

GPMI_MODE : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

NAND mode.

#1 : 1

ATA mode.

End of enumeration elements list.

CAMERA_MODE : no description available
bits : 1 - 1 (1 bit)
access : read-write

ATA_IRQRDY_POLARITY : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.

#1 : 1

External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.

End of enumeration elements list.

DEV_RESET : no description available
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

NANDF_WP_B pin is held low (asserted).

#1 : 1

NANDF_WP_B pin is held high (de-asserted).

End of enumeration elements list.

ABORT_WAIT_FOR_READY_CHANNEL : no description available
bits : 4 - 6 (3 bit)
access : read-write

ABORT_WAIT_REQUEST : no description available
bits : 7 - 7 (1 bit)
access : read-write

BURST_EN : no description available
bits : 8 - 8 (1 bit)
access : read-write

TIMEOUT_IRQ : no description available
bits : 9 - 9 (1 bit)
access : read-write

DEV_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write

DMA2ECC_MODE : no description available
bits : 11 - 11 (1 bit)
access : read-write

RDN_DELAY : no description available
bits : 12 - 15 (4 bit)
access : read-write

HALF_PERIOD : no description available
bits : 16 - 16 (1 bit)
access : read-write

DLL_ENABLE : no description available
bits : 17 - 17 (1 bit)
access : read-write

BCH_MODE : no description available
bits : 18 - 18 (1 bit)
access : read-write

GANGED_RDYBUSY : no description available
bits : 19 - 19 (1 bit)
access : read-write

TIMEOUT_IRQ_EN : no description available
bits : 20 - 20 (1 bit)
access : read-write

TEST_TRIGGER : no description available
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

WRN_DLY_SEL : no description available
bits : 22 - 23 (2 bit)
access : read-write

DECOUPLE_CS : no description available
bits : 24 - 24 (1 bit)
access : read-write

SSYNCMODE : no description available
bits : 25 - 25 (1 bit)
access : read-write

UPDATE_CS : no description available
bits : 26 - 26 (1 bit)
access : read-write

GPMI_CLK_DIV2_EN : no description available
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

internal factor-2 clock divider is disabled

#1 : 1

internal factor-2 clock divider is enabled.

End of enumeration elements list.

TOGGLE_MODE : no description available
bits : 28 - 28 (1 bit)
access : read-write

WRITE_CLK_STOP : no description available
bits : 29 - 29 (1 bit)
access : read-write

SSYNC_CLK_STOP : no description available
bits : 30 - 30 (1 bit)
access : read-write

DEV_CLK_STOP : no description available
bits : 31 - 31 (1 bit)
access : read-write


TIMING0

GPMI Timing Register 0 Description
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMING0 TIMING0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_SETUP DATA_HOLD ADDRESS_SETUP RSVD1

DATA_SETUP : no description available
bits : 0 - 7 (8 bit)
access : read-write

DATA_HOLD : no description available
bits : 8 - 15 (8 bit)
access : read-write

ADDRESS_SETUP : no description available
bits : 16 - 23 (8 bit)
access : read-write

RSVD1 : no description available
bits : 24 - 31 (8 bit)
access : write-only


CTRL0_CLR

GPMI Control Register 0 Description
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0_CLR CTRL0_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFER_COUNT ADDRESS_INCREMENT ADDRESS CS WORD_LENGTH COMMAND_MODE UDMA LOCK_CS DEV_IRQ_EN RUN CLKGATE SFTRST

XFER_COUNT : no description available
bits : 0 - 15 (16 bit)
access : read-write

ADDRESS_INCREMENT : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Address does not increment.

#1 : 1

Increment address.

End of enumeration elements list.

ADDRESS : no description available
bits : 17 - 19 (3 bit)
access : read-write

CS : no description available
bits : 20 - 22 (3 bit)
access : read-write

WORD_LENGTH : no description available
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#1 : 1

8-bit Data Bus mode.

End of enumeration elements list.

COMMAND_MODE : no description available
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

Write mode.

#01 : 01

Read Mode.

#10 : 10

Read and Compare Mode (setting sense flop).

#11 : 11

Wait for Ready.

End of enumeration elements list.

UDMA : no description available
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Use ATA-PIO mode on the external bus.

#1 : 1

Use ATA-Ultra DMA mode on the external bus.

End of enumeration elements list.

LOCK_CS : no description available
bits : 27 - 27 (1 bit)
access : read-write

DEV_IRQ_EN : no description available
bits : 28 - 28 (1 bit)
access : read-write

RUN : no description available
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write

SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write


TIMING1

GPMI Timing Register 1 Description
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMING1 TIMING1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD1 DEVICE_BUSY_TIMEOUT

RSVD1 : no description available
bits : 0 - 15 (16 bit)
access : read-only

DEVICE_BUSY_TIMEOUT : no description available
bits : 16 - 31 (16 bit)
access : read-write


TIMING2

GPMI Timing Register 2 Description
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMING2 TIMING2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_PAUSE CMDADD_PAUSE POSTAMBLE_DELAY PREAMBLE_DELAY CE_DELAY RSVD0 READ_LATENCY TCR TRPSTH

DATA_PAUSE : no description available
bits : 0 - 3 (4 bit)
access : read-write

CMDADD_PAUSE : no description available
bits : 4 - 7 (4 bit)
access : read-write

POSTAMBLE_DELAY : no description available
bits : 8 - 11 (4 bit)
access : read-write

PREAMBLE_DELAY : no description available
bits : 12 - 15 (4 bit)
access : read-write

CE_DELAY : no description available
bits : 16 - 20 (5 bit)
access : read-write

RSVD0 : no description available
bits : 21 - 23 (3 bit)
access : read-only

READ_LATENCY : no description available
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 000

READ LATENCY is 0

#001 : 001

READ LATENCY is 1

#010 : 010

READ LATENCY is 2

#011 : 011

READ LATENCY is 3

#100 : 100

READ LATENCY is 4

#101 : 101

READ LATENCY is 5

End of enumeration elements list.

TCR : no description available
bits : 27 - 28 (2 bit)
access : read-write

TRPSTH : no description available
bits : 29 - 31 (3 bit)
access : read-write


DATA

GPMI DMA Data Transfer Register Description
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : no description available
bits : 0 - 31 (32 bit)
access : read-write


STAT

GPMI Status Register Description
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESENT FIFO_FULL FIFO_EMPTY INVALID_BUFFER_MASK ATA_IRQ RSVD1 DEV0_ERROR DEV1_ERROR DEV2_ERROR DEV3_ERROR DEV4_ERROR DEV5_ERROR DEV6_ERROR DEV7_ERROR RDY_TIMEOUT READY_BUSY

PRESENT : no description available
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

GPMI is not present in this product.

#1 : 1

GPMI is present is in this product.

End of enumeration elements list.

FIFO_FULL : no description available
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

FIFO is not full.

#1 : 1

FIFO is full.

End of enumeration elements list.

FIFO_EMPTY : no description available
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

FIFO is not empty.

#1 : 1

FIFO is empty.

End of enumeration elements list.

INVALID_BUFFER_MASK : no description available
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

ECC Buffer Mask is not invalid.

#1 : 1

ECC Buffer Mask is invalid.

End of enumeration elements list.

ATA_IRQ : no description available
bits : 4 - 4 (1 bit)
access : read-only

RSVD1 : no description available
bits : 5 - 7 (3 bit)
access : read-only

DEV0_ERROR : no description available
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

No error condition present on ATA/NAND Device accessed by DMA channel 0.

#1 : 1

An Error has occurred on ATA/NAND Device accessed by

End of enumeration elements list.

DEV1_ERROR : no description available
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

#0 : 0

No error condition present on ATA/NAND Device accessed by DMA channel 1.

#1 : 1

An Error has occurred on ATA/NAND Device accessed by

End of enumeration elements list.

DEV2_ERROR : no description available
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

#0 : 0

No error condition present on ATA/NAND Device accessed by DMA channel 2.

#1 : 1

An Error has occurred on ATA/NAND Device accessed by

End of enumeration elements list.

DEV3_ERROR : no description available
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

#0 : 0

No error condition present on ATA/NAND Device accessed by DMA channel 3.

#1 : 1

An Error has occurred on ATA/NAND Device accessed by

End of enumeration elements list.

DEV4_ERROR : no description available
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

#0 : 0

No error condition present on ATA/NAND Device accessed by DMA channel 4.

#1 : 1

An Error has occurred on ATA/NAND Device accessed by

End of enumeration elements list.

DEV5_ERROR : no description available
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

#0 : 0

No error condition present on ATA/NAND Device accessed by DMA channel 5.

#1 : 1

An Error has occurred on ATA/NAND Device accessed by

End of enumeration elements list.

DEV6_ERROR : no description available
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

#0 : 0

No error condition present on ATA/NAND Device accessed by DMA channel 6.

#1 : 1

An Error has occurred on ATA/NAND Device accessed by

End of enumeration elements list.

DEV7_ERROR : no description available
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#0 : 0

No error condition present on ATA/NAND Device accessed by DMA channel 7.

#1 : 1

An Error has occurred on ATA/NAND Device accessed by

End of enumeration elements list.

RDY_TIMEOUT : no description available
bits : 16 - 23 (8 bit)
access : read-only

READY_BUSY : no description available
bits : 24 - 31 (8 bit)
access : read-only


CTRL0_TOG

GPMI Control Register 0 Description
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0_TOG CTRL0_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFER_COUNT ADDRESS_INCREMENT ADDRESS CS WORD_LENGTH COMMAND_MODE UDMA LOCK_CS DEV_IRQ_EN RUN CLKGATE SFTRST

XFER_COUNT : no description available
bits : 0 - 15 (16 bit)
access : read-write

ADDRESS_INCREMENT : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Address does not increment.

#1 : 1

Increment address.

End of enumeration elements list.

ADDRESS : no description available
bits : 17 - 19 (3 bit)
access : read-write

CS : no description available
bits : 20 - 22 (3 bit)
access : read-write

WORD_LENGTH : no description available
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#1 : 1

8-bit Data Bus mode.

End of enumeration elements list.

COMMAND_MODE : no description available
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

Write mode.

#01 : 01

Read Mode.

#10 : 10

Read and Compare Mode (setting sense flop).

#11 : 11

Wait for Ready.

End of enumeration elements list.

UDMA : no description available
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Use ATA-PIO mode on the external bus.

#1 : 1

Use ATA-Ultra DMA mode on the external bus.

End of enumeration elements list.

LOCK_CS : no description available
bits : 27 - 27 (1 bit)
access : read-write

DEV_IRQ_EN : no description available
bits : 28 - 28 (1 bit)
access : read-write

RUN : no description available
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write

SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write


DEBUG

GPMI Debug Information Register Description
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEBUG DEBUG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_END DMAREQ DMA_SENSE WAIT_FOR_READY_END

CMD_END : no description available
bits : 0 - 7 (8 bit)
access : read-only

DMAREQ : no description available
bits : 8 - 15 (8 bit)
access : read-only

DMA_SENSE : no description available
bits : 16 - 23 (8 bit)
access : read-only

WAIT_FOR_READY_END : no description available
bits : 24 - 31 (8 bit)
access : read-only


VERSION

GPMI Version Register Description
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STEP MINOR MAJOR

STEP : no description available
bits : 0 - 15 (16 bit)
access : read-only

MINOR : no description available
bits : 16 - 23 (8 bit)
access : read-only

MAJOR : no description available
bits : 24 - 31 (8 bit)
access : read-only


DEBUG2

GPMI Debug2 Information Register Description
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG2 DEBUG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDN_TAP UPDATE_WINDOW VIEW_DELAYED_RDN SYND2GPMI_READY SYND2GPMI_VALID GPMI2SYND_READY GPMI2SYND_VALID SYND2GPMI_BE MAIN_STATE PIN_STATE BUSY UDMA_STATE RSVD1

RDN_TAP : no description available
bits : 0 - 5 (6 bit)
access : read-only

UPDATE_WINDOW : no description available
bits : 6 - 6 (1 bit)
access : read-only

VIEW_DELAYED_RDN : no description available
bits : 7 - 7 (1 bit)
access : read-write

SYND2GPMI_READY : no description available
bits : 8 - 8 (1 bit)
access : read-only

SYND2GPMI_VALID : no description available
bits : 9 - 9 (1 bit)
access : read-only

GPMI2SYND_READY : no description available
bits : 10 - 10 (1 bit)
access : read-only

GPMI2SYND_VALID : no description available
bits : 11 - 11 (1 bit)
access : read-only

SYND2GPMI_BE : no description available
bits : 12 - 15 (4 bit)
access : read-only

MAIN_STATE : no description available
bits : 16 - 19 (4 bit)
access : read-only

PIN_STATE : no description available
bits : 20 - 22 (3 bit)
access : read-only

BUSY : no description available
bits : 23 - 23 (1 bit)
access : read-only

UDMA_STATE : no description available
bits : 24 - 27 (4 bit)
access : read-only

RSVD1 : no description available
bits : 28 - 31 (4 bit)
access : read-write


DEBUG3

GPMI Debug3 Information Register Description
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEBUG3 DEBUG3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEV_WORD_CNTR APB_WORD_CNTR

DEV_WORD_CNTR : no description available
bits : 0 - 15 (16 bit)
access : read-only

APB_WORD_CNTR : no description available
bits : 16 - 31 (16 bit)
access : read-only



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