Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection : not protected
Receive Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ECSPI_RXDATA : no description available
bits : 0 - 31 (32 bit)
access : read-only
Interrupt Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEEN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
TDREN : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
TFEN : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
RREN : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
RDREN : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
RFEN : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
ROEN : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
TCEN : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
DMA Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_THRESHOLD : no description available
bits : 0 - 5 (6 bit)
access : read-write
TEDEN : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
RX_THRESHOLD : no description available
bits : 16 - 21 (6 bit)
access : read-write
RXDEN : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
RX_DMA_LENGTH : no description available
bits : 24 - 29 (6 bit)
access : read-write
RXTDEN : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TE : no description available
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
TXFIFO contains one or more words.
#1 : 1
TXFIFO is empty.
End of enumeration elements list.
TDR : no description available
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Number of empty slots in TXFIFO is greater than TX_THRESHOLD.
#1 : 1
Number of empty slots in TXFIFO is not greater than TX_THRESHOLD.
End of enumeration elements list.
TF : no description available
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
TXFIFO is not Full.
#1 : 1
TXFIFO is Full.
End of enumeration elements list.
RR : no description available
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
No valid data in RXFIFO.
#1 : 1
More than 1 word in RXFIFO.
End of enumeration elements list.
RDR : no description available
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD.
#1 : 1
When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists.
End of enumeration elements list.
RF : no description available
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not Full.
#1 : 1
Full.
End of enumeration elements list.
RO : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
RXFIFO has no overflow.
#1 : 1
RXFIFO has overflowed.
End of enumeration elements list.
TC : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer in progress.
#1 : 1
Transfer completed.
End of enumeration elements list.
Sample Period Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAMPLE_PERIOD : no description available
bits : 0 - 14 (15 bit)
access : read-write
Enumeration:
#0 : 0
0 wait states inserted
#1 : 1
1 wait state inserted
#111111111111110 : 111111111111110
32766 wait states inserted
#111111111111111 : 111111111111111
32767 wait states inserted
End of enumeration elements list.
CSRC : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI Clock (SCLK)
#1 : 1
Low-Frequency Reference Clock (32.768 KHz)
End of enumeration elements list.
CSD_CTL : no description available
bits : 16 - 21 (6 bit)
access : read-write
Test Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCNT : no description available
bits : 0 - 6 (7 bit)
access : read-write
RXCNT : no description available
bits : 8 - 14 (7 bit)
access : read-write
LBC : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not connected.
#1 : 1
Transmitter and receiver sections internally connected for Loopback.
End of enumeration elements list.
Transmit Data Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ECSPI_TXDATA : no description available
bits : 0 - 31 (32 bit)
access : write-only
Message Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ECSPI_MSGDATA : no description available
bits : 0 - 31 (32 bit)
access : write-only
Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the block.
#1 : 1
Enable the block.
End of enumeration elements list.
HT : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable HT mode.
#1 : 1
Enable HT mode.
End of enumeration elements list.
XCH : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Idle.
#1 : 1
Initiates exchange (write) or busy (read).
End of enumeration elements list.
SMC : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL descriptions.
#1 : 1
Immediately starts a SPI burst when data is written in TXFIFO.
End of enumeration elements list.
CHANNEL_MODE : no description available
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode.
#1 : 1
Master mode.
End of enumeration elements list.
POST_DIVIDER : no description available
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1.
#0001 : 0001
Divide by 2.
#0010 : 0010
Divide by 4.
#1110 : 1110
Divide by 2 14 .
#1111 : 1111
Divide by 2 15 .
End of enumeration elements list.
PRE_DIVIDER : no description available
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1.
#0001 : 0001
Divide by 2.
#0010 : 0010
Divide by 3.
#1101 : 1101
Divide by 14.
#1110 : 1110
Divide by 15.
#1111 : 1111
Divide by 16.
End of enumeration elements list.
DRCTL : no description available
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
The SPI_RDY signal is a don't care.
#01 : 01
Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered).
#10 : 10
Burst will be triggered by a low level of the SPI_RDY signal (level-triggered).
End of enumeration elements list.
CHANNEL_SELECT : no description available
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
Channel 0 is selected. Chip Select 0 (SS0) will be asserted.
#01 : 01
Channel 1 is selected. Chip Select 1 (SS1) will be asserted.
#10 : 10
Channel 2 is selected. Chip Select 2 (SS2) will be asserted.
#11 : 11
Channel 3 is selected. Chip Select 3 (SS3) will be asserted.
End of enumeration elements list.
BURST_LENGTH : no description available
bits : 20 - 31 (12 bit)
access : read-write
Enumeration:
#0 : 0
A SPI burst contains the 1 LSB in a word.
#1 : 1
A SPI burst contains the 2 LSB in a word.
#10 : 10
A SPI burst contains the 3 LSB in a word.
#11111 : 11111
A SPI burst contains all 32 bits in a word.
#100000 : 100000
A SPI burst contains the 1 LSB in first word and all 32 bits in second word.
#100001 : 100001
A SPI burst contains the 2 LSB in first word and all 32 bits in second word.
#111111111110 : 111111111110
A SPI burst contains the 31 LSB in first word and 2^7 -1 words.
#111111111111 : 111111111111
A SPI burst contains 2^7 words.
End of enumeration elements list.
Config Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCLK_PHA : no description available
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0 : 0
Phase 0 operation.
#1 : 1
Phase 1 operation.
End of enumeration elements list.
SCLK_POL : no description available
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0 : 0
Active high polarity (0 = Idle).
#1 : 1
Active low polarity (1 = Idle).
End of enumeration elements list.
SS_CTL : no description available
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0 : 0
In master mode - only one SPI burst will be transmitted.
#1 : 1
In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be transmitted. The SPI transfer will automatically stop when the TXFIFO is empty.
End of enumeration elements list.
SS_POL : no description available
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0 : 0
Active low.
#1 : 1
Active high.
End of enumeration elements list.
DATA_CTL : no description available
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0 : 0
Stay high.
#1 : 1
Stay low.
End of enumeration elements list.
SCLK_CTL : no description available
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0 : 0
Stay low.
#1 : 1
Stay high.
End of enumeration elements list.
HT_LENGTH : no description available
bits : 24 - 28 (5 bit)
access : read-write
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