Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x5C byte (0x0)
mem_usage : registers
protection : not protected
SSI Transmit Data Register n
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STXn : no description available
bits : 0 - 31 (32 bit)
access : read-write
SSI Receive Data Register n
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SRXn : no description available
bits : 0 - 31 (32 bit)
access : read-only
SSI Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSIEN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SSI is disabled.
#1 : 1
SSI is enabled.
End of enumeration elements list.
TE : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit section disabled.
#1 : 1
Transmit section enabled.
End of enumeration elements list.
RE : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive section disabled.
#1 : 1
Receive section enabled.
End of enumeration elements list.
NET : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Network mode not selected.
#1 : 1
Network mode selected.
End of enumeration elements list.
SYN : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Asynchronous mode selected.
#1 : 1
Synchronous mode selected.
End of enumeration elements list.
I2S_MODE : no description available
bits : 5 - 6 (2 bit)
access : read-write
SYS_CLK_EN : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
network clock not output on SRCK port.
#1 : 1
network clock output on SRCK port.
End of enumeration elements list.
TCH_EN : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Two-channel mode disabled.
#1 : 1
Two-channel mode enabled.
End of enumeration elements list.
CLK_IST : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock idle state is '0'.
#1 : 1
Clock idle state is '1'.
End of enumeration elements list.
TFR_CLK_DIS : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Continue Frame-sync/Clock generation after current frame during which TE is cleared. This may be required when Frame-sync and Clocks are required from SSI, even when no data is to be received.
#1 : 1
Stop Frame-sync/Clock generation at next frame boundary. This will be effective also in case where transmitter is already disabled in current or previous frames.
End of enumeration elements list.
RFR_CLK_DIS : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Continue Frame-sync/Clock generation after current frame during which RE is cleared. This may be required when Frame-sync and Clocks are required from SSI, even when no data is to be received.
#1 : 1
Stop Frame-sync/Clock generation at next frame boundary. This will be effective also in case where receiver is already disabled in current or previous frames.
End of enumeration elements list.
SYNC_TX_FS : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
TE not latched with FS occurrence & used directly for transmitter enable/disable.
#1 : 1
TE latched with FS occurrence & latched-TE used for transmitter enable/disable.
End of enumeration elements list.
SSI Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFE0 : no description available
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO0 has data for transmission.
#1 : 1
Transmit FIFO0 is empty.
End of enumeration elements list.
TFE1 : no description available
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO1 has data for transmission.
#1 : 1
Transmit FIFO1 is empty.
End of enumeration elements list.
RFF0 : no description available
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Space available in Receive FIFO0.
#1 : 1
Receive FIFO0 is full.
End of enumeration elements list.
RFF1 : no description available
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Space available in Receive FIFO1.
#1 : 1
Receive FIFO1 is full.
End of enumeration elements list.
RLS : no description available
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Current time slot is not last time slot of frame.
#1 : 1
Current time slot is the last receive time slot of frame.
End of enumeration elements list.
TLS : no description available
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Current time slot is not last time slot of frame.
#1 : 1
Current time slot is the last transmit time slot of frame.
End of enumeration elements list.
RFS : no description available
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Occurrence of Receive frame sync.
#1 : 1
Receive frame sync occurred during reception of next word in SRX registers.
End of enumeration elements list.
TFS : no description available
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No Occurrence of Transmit frame sync.
#1 : 1
Transmit frame sync occurred during transmission of last word written to STX registers.
End of enumeration elements list.
TUE0 : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Default interrupt issued to the Core.
#1 : 1
Exception interrupt issued to the Core.
End of enumeration elements list.
TUE1 : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Default interrupt issued to the Core.
#1 : 1
Exception interrupt issued to the Core.
End of enumeration elements list.
ROE0 : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Default interrupt issued to the Core.
#1 : 1
Exception interrupt issued to the Core.
End of enumeration elements list.
ROE1 : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Default interrupt issued to the Core.
#1 : 1
Exception interrupt issued to the Core.
End of enumeration elements list.
TDE0 : no description available
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data available for transmission.
#1 : 1
Data needs to be written by the Core for transmission.
End of enumeration elements list.
TDE1 : no description available
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data available for transmission.
#1 : 1
Data needs to be written by the Core for transmission.
End of enumeration elements list.
RDR0 : no description available
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
No new data for Core to read.
#1 : 1
New data for Core to read.
End of enumeration elements list.
RDR1 : no description available
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
No new data for Core to read.
#1 : 1
New data for Core to read.
End of enumeration elements list.
RXT : no description available
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
No change in SATAG register.
#1 : 1
SATAG register updated with different value.
End of enumeration elements list.
CMDDU : no description available
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
No change in SACDAT register.
#1 : 1
SACDAT register updated with different value.
End of enumeration elements list.
CMDAU : no description available
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
No change in SACADD register.
#1 : 1
SACADD register updated with different value.
End of enumeration elements list.
TFRC : no description available
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
End of Frame not reached
#1 : 1
End of frame reached after disabling TE or disabling TFR_CLK_DIS, when transmitter is already disabled.
End of enumeration elements list.
RFRC : no description available
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
End of Frame not reached
#1 : 1
End of frame reached after disabling RE or disabling RFR_CLK_DIS, when receiver is already disabled.
End of enumeration elements list.
SSI Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFE0IE : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TFE1IE : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RFF0IE : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RFF1IE : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RLSIE : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TLSIE : no description available
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RFSIE : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TFSIE : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TUE0IE : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TUE1IE : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
ROE0IE : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
ROE1IE : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TDE0IE : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TDE1IE : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RDR0IE : no description available
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RDR1IE : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RXTIE : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
CMDDUIE : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
CMDAUIE : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
TIE : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
SSI Transmitter Interrupt requests disabled.
#1 : 1
SSI Transmitter Interrupt requests enabled.
End of enumeration elements list.
TDMAE : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
SSI Transmitter DMA requests disabled.
#1 : 1
SSI Transmitter DMA requests enabled.
End of enumeration elements list.
RIE : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
SSI Receiver Interrupt requests disabled.
#1 : 1
SSI Receiver Interrupt requests enabled.
End of enumeration elements list.
RDMAE : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
SSI Receiver DMA requests disabled.
#1 : 1
SSI Receiver DMA requests enabled.
End of enumeration elements list.
TFRCIE : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
RFRCIE : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding status bit cannot issue interrupt.
#1 : 1
Corresponding status bit can issue interrupt.
End of enumeration elements list.
SSI Receive Data Register n
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SRXn : no description available
bits : 0 - 31 (32 bit)
access : read-only
SSI Transmit Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEFS : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit frame sync initiated as the first bit of data is transmitted.
#1 : 1
Transmit frame sync is initiated one bit before the data is transmitted.
End of enumeration elements list.
TFSL : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit frame sync is one-word long.
#1 : 1
Transmit frame sync is one-clock-bit long.
End of enumeration elements list.
TFSI : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit frame sync is active high.
#1 : 1
Transmit frame sync is active low.
End of enumeration elements list.
TSCKP : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data clocked out on rising edge of bit clock.
#1 : 1
Data clocked out on falling edge of bit clock.
End of enumeration elements list.
TSHFD : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data transmitted MSB first.
#1 : 1
Data transmitted LSB first.
End of enumeration elements list.
TXDIR : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit Clock is external.
#1 : 1
Transmit Clock generated internally.
End of enumeration elements list.
TFDIR : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame Sync is external.
#1 : 1
Frame Sync generated internally.
End of enumeration elements list.
TFEN0 : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit FIFO 0 disabled.
#1 : 1
Transmit FIFO 0 enabled.
End of enumeration elements list.
TFEN1 : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit FIFO 1 disabled.
#1 : 1
Transmit FIFO 1 enabled.
End of enumeration elements list.
TXBIT0 : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or 12) of transmit shift register (MSB aligned).
#1 : 1
Shifting with respect to bit 0 of transmit shift register (LSB aligned).
End of enumeration elements list.
SSI Receive Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFS : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive frame sync initiated as the first bit of data is received.
#1 : 1
Receive frame sync is initiated one bit before the data is received.
End of enumeration elements list.
RFSL : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive frame sync is one-word long.
#1 : 1
Receive frame sync is one-clock-bit long.
End of enumeration elements list.
RFSI : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive frame sync is active high.
#1 : 1
Receive frame sync is active low.
End of enumeration elements list.
RSCKP : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data latched on falling edge of bit clock.
#1 : 1
Data latched on rising edge of bit clock.
End of enumeration elements list.
RSHFD : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data received MSB first.
#1 : 1
Data received LSB first.
End of enumeration elements list.
RXDIR : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive Clock is external.
#1 : 1
Receive Clock generated internally.
End of enumeration elements list.
RFDIR : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame Sync is external.
#1 : 1
Frame Sync generated internally.
End of enumeration elements list.
RFEN0 : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO 0 disabled.
#1 : 1
Receive FIFO 0 enabled.
End of enumeration elements list.
RFEN1 : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO 1 disabled.
#1 : 1
Receive FIFO 1 enabled.
End of enumeration elements list.
RXBIT0 : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or 12) of receive shift register (MSB aligned).
#1 : 1
Shifting with respect to bit 0 of receive shift register (LSB aligned).
End of enumeration elements list.
RXEXT : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sign extension turned off.
#1 : 1
Sign extension turned on.
End of enumeration elements list.
SSI Transmit Clock Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PM7_PM0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
DC4_DC0 : no description available
bits : 8 - 12 (5 bit)
access : read-write
WL3_WL0 : no description available
bits : 13 - 16 (4 bit)
access : read-write
PSR : no description available
bits : 17 - 17 (1 bit)
access : read-write
DIV2 : no description available
bits : 18 - 18 (1 bit)
access : read-write
SSI Receive Clock Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PM7_PM0 : no description available
bits : 0 - 7 (8 bit)
access : read-write
DC4_DC0 : no description available
bits : 8 - 12 (5 bit)
access : read-write
WL3_WL0 : no description available
bits : 13 - 16 (4 bit)
access : read-write
PSR : no description available
bits : 17 - 17 (1 bit)
access : read-write
DIV2 : no description available
bits : 18 - 18 (1 bit)
access : read-write
SSI FIFO Control/Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFWM0 : no description available
bits : 0 - 3 (4 bit)
access : read-write
RFWM0 : no description available
bits : 4 - 7 (4 bit)
access : read-write
TFCNT0 : no description available
bits : 8 - 11 (4 bit)
access : read-write
RFCNT0 : no description available
bits : 12 - 15 (4 bit)
access : read-write
TFWM1 : no description available
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0001 : 0001
TFE set when there are more than or equal to 1 empty slots in Transmit FIFO (default). Transmit FIFO empty is set when TxFIFO <= 14 data.
#0010 : 0010
TFE set when there are more than or equal to 2 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=13 data.
#0011 : 0011
TFE set when there are more than or equal to 3 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=12 data.
#0100 : 0100
TFE set when there are more than or equal to 4 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=11 data.
#0101 : 0101
TFE set when there are more than or equal to 5 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=10 data.
#0110 : 0110
TFE set when there are more than or equal to 6 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=9 data.
#0111 : 0111
TFE set when there are more than or equal to 7 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=8 data.
#1000 : 1000
TFE set when there are more than or equal to 8 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <=7 data.
#1001 : 1001
TFE set when there are more than or equal to 9 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 6 data.
#1010 : 1010
TFE set when there are more than or equal to 10 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 5 data.
#1011 : 1011
TFE set when there are more than or equal to 11 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 4 data.
#1100 : 1100
TFE set when there are more than or equal to 12 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 3 data.
#1101 : 1101
TFE set when there are more than or equal to 13 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 2 data.
#1110 : 1110
TFE set when there are more than or equal to 14 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO <= 1 data.
#1111 : 1111
TFE set when there are 15 empty slots in Transmit FIFO. Transmit FIFO empty is set when TxFIFO = 0 data.
End of enumeration elements list.
RFWM1 : no description available
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0001 : 0001
RFF set when at least one data word has been written to the Receive FIFO. Set when RxFIFO = 1,2.....15 data words
#0010 : 0010
RFF set when 2 or more data words have been written to the Receive FIFO. Set when RxFIFO = 2,3.....15 data words
#0011 : 0011
RFF set when 3 or more data words have been written to the Receive FIFO. Set when RxFIFO = 3,4.....15 data words
#0100 : 0100
RFF set when 4 or more data words have been written to the Receive FIFO. Set when RxFIFO = 4,5.....15 data words
#0101 : 0101
RFF set when 5 or more data words have been written to the Receive FIFO. Set when RxFIFO = 5,6.....15 data words
#0110 : 0110
RFF set when 6 or more data words have been written to the Receive.. Set when RxFIFO = 6,7......15 data words
#0111 : 0111
RFF set when 7 or more data words have been written to the Receive FIFO. Set when RxFIFO = 7,8......15 data words
#1000 : 1000
RFF set when 8 or more data words have been written to the Receive FIFO. Set when RxFIFO =8,9..... 15 data words
#1001 : 1001
RFF set when 9 or more data words have been written to the Receive FIFO. Set when RxFIFO = 9,10.....15 data words
#1010 : 1010
RFF set when 10 or more data words have been written to the Receive FIFO. Set when RxFIFO = 10,11.....15 data words
#1011 : 1011
RFF set when 11 or more data words have been written to the Receive FIFO. Set when RxFIFO = 11,12.....15 data words
#1100 : 1100
RFF set when 12 or more data words have been written to the Receive FIFO. Set when RxFIFO = 12,13.....15 data words
#1101 : 1101
RFF set when 13 or more data words have been written to the Receive FIFO. Set when RxFIFO = 13,14,15data words
#1110 : 1110
RFF set when 14 or more data words have been written to the Receive FIFO. Set when RxFIFO = 14,15 data words
#1111 : 1111
RFF set when 15 data words have been written to the Receive FIFO (default). Set when RxFIFO = 15 data words
End of enumeration elements list.
TFCNT1 : no description available
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
0 data word in transmit FIFO
#0001 : 0001
1 data word in transmit FIFO
#0010 : 0010
2 data word in transmit FIFO
#0011 : 0011
3 data word in transmit FIFO
#0100 : 0100
4 data word in transmit FIFO
#0101 : 0101
5 data word in transmit FIFO
#0110 : 0110
6 data word in transmit FIFO
#0111 : 0111
7 data word in transmit FIFO
#1000 : 1000
8 data word in transmit FIFO
#1001 : 1001
9 data word in transmit FIFO
#1010 : 1010
10 data word in transmit FIFO
#1011 : 1011
11 data word in transmit FIFO
#1100 : 1100
12 data word in transmit FIFO
#1101 : 1101
13 data word in transmit FIFO
#1110 : 1110
14 data word in transmit FIFO
#1111 : 1111
15 data word in transmit FIFO
End of enumeration elements list.
RFCNT1 : no description available
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
0 data word in receive FIFO
#0001 : 0001
1 data word in receive FIFO
#0010 : 0010
2 data word in receive FIFO
#0011 : 0011
3 data word in receive FIFO
#0100 : 0100
4 data word in receive FIFO
#0101 : 0101
5 data word in receive FIFO
#0110 : 0110
6 data word in receive FIFO
#0111 : 0111
7 data word in receive FIFO
#1000 : 1000
8 data word in receive FIFO
#1001 : 1001
9 data word in receive FIFO
#1010 : 1010
10 data word in receive FIFO
#1011 : 1011
11 data word in receive FIFO
#1100 : 1100
12 data word in receive FIFO
#1101 : 1101
13 data word in receive FIFO
#1110 : 1110
14 data word in receive FIFO
#1111 : 1111
15 data word in receive FIFO
End of enumeration elements list.
SSI AC97 Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AC97EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
AC97 mode disabled.
#1 : 1
SSI in AC97 mode.
End of enumeration elements list.
FV : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
AC97 Fixed Mode.
#1 : 1
AC97 Variable Mode.
End of enumeration elements list.
TIF : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tag info stored in SATAG register.
#1 : 1
Tag info stored in Rx FIFO 0.
End of enumeration elements list.
RD : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Next frame will not have a Read Command.
#1 : 1
Next frame will have a Read Command.
End of enumeration elements list.
WR : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Next frame will not have a Write Command.
#1 : 1
Next frame will have a Write Command.
End of enumeration elements list.
FRDIV : no description available
bits : 5 - 10 (6 bit)
access : read-write
SSI AC97 Command Address Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SACADD : no description available
bits : 0 - 18 (19 bit)
access : read-write
SSI Transmit Data Register n
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STXn : no description available
bits : 0 - 31 (32 bit)
access : read-write
SSI AC97 Command Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SACDAT : no description available
bits : 0 - 19 (20 bit)
access : read-write
SSI AC97 Tag Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SATAG : no description available
bits : 0 - 15 (16 bit)
access : read-write
SSI Transmit Time Slot Mask Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STMSK : no description available
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
#0 : 0
Valid Time Slot.
#1 : 1
Time Slot masked (no data transmitted in this time slot).
End of enumeration elements list.
SSI Receive Time Slot Mask Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRMSK : no description available
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
#0 : 0
Valid Time Slot.
#1 : 1
Time Slot masked (no data received in this time slot).
End of enumeration elements list.
SSI AC97 Channel Status Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SACCST : no description available
bits : 0 - 9 (10 bit)
access : read-only
Enumeration:
#0 : 0
Data channel disabled.
#1 : 1
Data channel enabled.
End of enumeration elements list.
SSI AC97 Channel Enable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SACCEN : no description available
bits : 0 - 9 (10 bit)
access : write-only
Enumeration:
#0 : 0
Write Has no effect.
#1 : 1
Write Enables the corresponding data channel.
End of enumeration elements list.
SSI AC97 Channel Disable Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SACCDIS : no description available
bits : 0 - 9 (10 bit)
access : write-only
Enumeration:
#0 : 0
Write Has no effect.
#1 : 1
Write Disables the corresponding data channel.
End of enumeration elements list.
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