\n
address_offset : 0x110 Bytes (0x0)
size : 0x16C byte (0x0)
mem_usage : registers
protection : not protected
Regulator 1P1 Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : no description available
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : no description available
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : no description available
bits : 2 - 2 (1 bit)
access : read-write
ENABLE_PULLDOWN : no description available
bits : 3 - 3 (1 bit)
access : read-write
BO_OFFSET : no description available
bits : 4 - 6 (3 bit)
access : read-write
OUTPUT_TRG : no description available
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
#100 : 100
0.8V
#10000 : 10000
1.1V
#0x1 : 0x1
1.375V
End of enumeration elements list.
BO_VDD1P1 : no description available
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD1P1 : no description available
bits : 17 - 17 (1 bit)
access : read-only
ENABLE_WEAK_LINREG : no description available
bits : 18 - 18 (1 bit)
access : read-write
SELREF_WEAK_LINREG : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Weak-linreg output tracks low-power-bandgap voltage
#1 : 1
Weak-linreg output tracks VDD_SOC_CAP voltage
End of enumeration elements list.
Regulator 3P0 Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : no description available
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : no description available
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : no description available
bits : 2 - 2 (1 bit)
access : read-write
BO_OFFSET : no description available
bits : 4 - 6 (3 bit)
access : read-write
VBUS_SEL : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Utilize VBUS OTG1 for power
#1 : 1
Utilize VBUS OTG2 power
End of enumeration elements list.
OUTPUT_TRG : no description available
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
#0 : 0
2.625V
#1111 : 1111
3.000V
#11111 : 11111
3.400V
End of enumeration elements list.
BO_VDD3P0 : no description available
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD3P0 : no description available
bits : 17 - 17 (1 bit)
access : read-only
Regulator 2P5 Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : no description available
bits : 0 - 0 (1 bit)
access : read-write
ENABLE_BO : no description available
bits : 1 - 1 (1 bit)
access : read-write
ENABLE_ILIMIT : no description available
bits : 2 - 2 (1 bit)
access : read-write
ENABLE_PULLDOWN : no description available
bits : 3 - 3 (1 bit)
access : read-write
BO_OFFSET : no description available
bits : 4 - 6 (3 bit)
access : read-write
OUTPUT_TRG : no description available
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
#0 : 0
2.10V
#10000 : 10000
2.50V
#11111 : 11111
2.875V
End of enumeration elements list.
BO_VDD2P5 : no description available
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD2P5 : no description available
bits : 17 - 17 (1 bit)
access : read-only
ENABLE_WEAK_LINREG : no description available
bits : 18 - 18 (1 bit)
access : read-write
Digital Regulator Core Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG0_TARG : no description available
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Power gated off
#00001 : 00001
Target core voltage = 0.725V
#00010 : 00010
Target core voltage = 0.750V
#00011 : 00011
Target core voltage = 0.775V
#10000 : 10000
Target core voltage = 1.100V
#11110 : 11110
Target core voltage = 1.450V
#11111 : 11111
Power FET switched full on. No regulation.
End of enumeration elements list.
REG1_TARG : no description available
bits : 9 - 13 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Power gated off
#00001 : 00001
Target core voltage = 0.725V
#00010 : 00010
Target core voltage = 0.750V
#00011 : 00011
Target core voltage = 0.775V
#10000 : 10000
Target core voltage = 1.100V
#11110 : 11110
Target core voltage = 1.450V
#11111 : 11111
Power FET switched full on. No regulation.
End of enumeration elements list.
REG2_TARG : no description available
bits : 18 - 22 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Power gated off
#00001 : 00001
Target core voltage = 0.725V
#00010 : 00010
Target core voltage = 0.750V
#00011 : 00011
Target core voltage = 0.775V
#10000 : 10000
Target core voltage = 1.100V
#11110 : 11110
Target core voltage = 1.450V
#11111 : 11111
Power FET switched full on. No regulation.
End of enumeration elements list.
RAMP_RATE : no description available
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
#00 : 00
Fast
#01 : 01
Medium Fast
#10 : 10
Medium Slow
#11 : 11
Slow
End of enumeration elements list.
FET_ODRIVE : no description available
bits : 29 - 29 (1 bit)
access : read-write
Miscellaneous Register 0
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFTOP_PWD : no description available
bits : 0 - 0 (1 bit)
access : read-write
REFTOP_SELFBIASOFF : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Uses coarse bias currents for startup
#1 : 1
Uses bandgap-based bias currents for best performance.
End of enumeration elements list.
REFTOP_VBGADJ : no description available
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
Nominal VBG
#001 : 001
VBG+0.78%
#010 : 010
VBG+1.56%
#011 : 011
VBG+2.34%
#100 : 100
VBG-0.78%
#101 : 101
VBG-1.56%
#110 : 110
VBG-2.34%
#111 : 111
VBG-3.12%
End of enumeration elements list.
REFTOP_VBGUP : no description available
bits : 7 - 7 (1 bit)
access : read-write
STOP_MODE_CONFIG : no description available
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
SUSPEND (DSM)
#01 : 01
Analog regulators are ON.
#10 : 10
STOP (lower power)
#11 : 11
STOP (very lower power)
End of enumeration elements list.
RTC_RINGOSC_EN : no description available
bits : 12 - 12 (1 bit)
access : read-write
OSC_I : no description available
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#00 : 00
Nominal
#01 : 01
Decrease current by 12.5%
#10 : 10
Decrease current by 25.0%
#11 : 11
Decrease current by 37.5%
End of enumeration elements list.
OSC_XTALOK : no description available
bits : 15 - 15 (1 bit)
access : read-only
OSC_XTALOK_EN : no description available
bits : 16 - 16 (1 bit)
access : read-write
CLKGATE_CTRL : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Allow the logic to automatically gate the clock when the XTAL is powered down.
#1 : 1
Prevent the logic from ever gating off the clock.
End of enumeration elements list.
CLKGATE_DELAY : no description available
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
#000 : 000
0.5ms
#001 : 001
1.0ms
#010 : 010
2.0ms
#011 : 011
3.0ms
#100 : 100
4.0ms
#101 : 101
5.0ms
#110 : 110
6.0ms
#111 : 111
7.0ms
End of enumeration elements list.
RTC_XTAL_SOURCE : no description available
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal ring oscillator
#1 : 1
RTC_XTAL
End of enumeration elements list.
XTAL_24M_PWD : no description available
bits : 30 - 30 (1 bit)
access : read-write
VID_PLL_PREDIV : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divide by 1
#1 : 1
Divide by 2
End of enumeration elements list.
Miscellaneous Register 1
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDS1_CLK_SEL : no description available
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Arm PLL
#00001 : 00001
System PLL
#00010 : 00010
ref_pfd4_clk == pll2_pfd0_clk
#00011 : 00011
ref_pfd5_clk == pll2_pfd1_clk
#00100 : 00100
ref_pfd6_clk == pll2_pfd2_clk
#00101 : 00101
ref_pfd7_clk == pll2_pfd3_clk
#00110 : 00110
Audio PLL
#00111 : 00111
Video PLL
#01001 : 01001
ethernet ref clock (ENET_PLL)
#01100 : 01100
USB1 PLL clock
#01101 : 01101
USB2 PLL clock
#01110 : 01110
ref_pfd0_clk == pll3_pfd0_clk
#01111 : 01111
ref_pfd1_clk == pll3_pfd1_clk
#10000 : 10000
ref_pfd2_clk == pll3_pfd2_clk
#10001 : 10001
ref_pfd3_clk == pll3_pfd3_clk
#10010 : 10010
xtal (24M)
End of enumeration elements list.
LVDS2_CLK_SEL : no description available
bits : 5 - 9 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Arm PLL
#00001 : 00001
System PLL
#00010 : 00010
ref_pfd4_clk == pll2_pfd0_clk
#00011 : 00011
ref_pfd5_clk == pll2_pfd1_clk
#00100 : 00100
ref_pfd6_clk == pll2_pfd2_clk
#00101 : 00101
ref_pfd7_clk == pll2_pfd3_clk
#00110 : 00110
Audio PLL
#00111 : 00111
Video PLL
#01000 : 01000
MLB PLL
#01001 : 01001
ethernet ref clock (ENET_PLL)
#01010 : 01010
PCIe ref clock (125M)
#01100 : 01100
USB1 PLL clock
#01101 : 01101
USB2 PLL clock
#01110 : 01110
ref_pfd0_clk == pll3_pfd0_clk
#01111 : 01111
ref_pfd1_clk == pll3_pfd1_clk
#10000 : 10000
ref_pfd2_clk == pll3_pfd2_clk
#10001 : 10001
ref_pfd3_clk == pll3_pfd3_clk
#10010 : 10010
xtal (24M)
#10011 : 10011
LVDS1 (loopback)
#10100 : 10100
LVDS2 (not useful)
End of enumeration elements list.
LVDSCLK1_OBEN : no description available
bits : 10 - 10 (1 bit)
access : read-write
LVDSCLK2_OBEN : no description available
bits : 11 - 11 (1 bit)
access : read-write
LVDSCLK1_IBEN : no description available
bits : 12 - 12 (1 bit)
access : read-write
LVDSCLK2_IBEN : no description available
bits : 13 - 13 (1 bit)
access : read-write
PFD_480_AUTOGATE_EN : no description available
bits : 16 - 16 (1 bit)
access : read-write
PFD_528_AUTOGATE_EN : no description available
bits : 17 - 17 (1 bit)
access : read-write
IRQ_TEMPPANIC : no description available
bits : 27 - 27 (1 bit)
access : read-write
IRQ_TEMPLOW : no description available
bits : 28 - 28 (1 bit)
access : read-write
IRQ_TEMPHIGH : no description available
bits : 29 - 29 (1 bit)
access : read-write
IRQ_ANA_BO : no description available
bits : 30 - 30 (1 bit)
access : read-write
IRQ_DIG_BO : no description available
bits : 31 - 31 (1 bit)
access : read-write
Miscellaneous Register 1
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDS1_CLK_SEL : no description available
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Arm PLL
#00001 : 00001
System PLL
#00010 : 00010
ref_pfd4_clk == pll2_pfd0_clk
#00011 : 00011
ref_pfd5_clk == pll2_pfd1_clk
#00100 : 00100
ref_pfd6_clk == pll2_pfd2_clk
#00101 : 00101
ref_pfd7_clk == pll2_pfd3_clk
#00110 : 00110
Audio PLL
#00111 : 00111
Video PLL
#01001 : 01001
ethernet ref clock (ENET_PLL)
#01100 : 01100
USB1 PLL clock
#01101 : 01101
USB2 PLL clock
#01110 : 01110
ref_pfd0_clk == pll3_pfd0_clk
#01111 : 01111
ref_pfd1_clk == pll3_pfd1_clk
#10000 : 10000
ref_pfd2_clk == pll3_pfd2_clk
#10001 : 10001
ref_pfd3_clk == pll3_pfd3_clk
#10010 : 10010
xtal (24M)
End of enumeration elements list.
LVDS2_CLK_SEL : no description available
bits : 5 - 9 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Arm PLL
#00001 : 00001
System PLL
#00010 : 00010
ref_pfd4_clk == pll2_pfd0_clk
#00011 : 00011
ref_pfd5_clk == pll2_pfd1_clk
#00100 : 00100
ref_pfd6_clk == pll2_pfd2_clk
#00101 : 00101
ref_pfd7_clk == pll2_pfd3_clk
#00110 : 00110
Audio PLL
#00111 : 00111
Video PLL
#01000 : 01000
MLB PLL
#01001 : 01001
ethernet ref clock (ENET_PLL)
#01010 : 01010
PCIe ref clock (125M)
#01100 : 01100
USB1 PLL clock
#01101 : 01101
USB2 PLL clock
#01110 : 01110
ref_pfd0_clk == pll3_pfd0_clk
#01111 : 01111
ref_pfd1_clk == pll3_pfd1_clk
#10000 : 10000
ref_pfd2_clk == pll3_pfd2_clk
#10001 : 10001
ref_pfd3_clk == pll3_pfd3_clk
#10010 : 10010
xtal (24M)
#10011 : 10011
LVDS1 (loopback)
#10100 : 10100
LVDS2 (not useful)
End of enumeration elements list.
LVDSCLK1_OBEN : no description available
bits : 10 - 10 (1 bit)
access : read-write
LVDSCLK2_OBEN : no description available
bits : 11 - 11 (1 bit)
access : read-write
LVDSCLK1_IBEN : no description available
bits : 12 - 12 (1 bit)
access : read-write
LVDSCLK2_IBEN : no description available
bits : 13 - 13 (1 bit)
access : read-write
PFD_480_AUTOGATE_EN : no description available
bits : 16 - 16 (1 bit)
access : read-write
PFD_528_AUTOGATE_EN : no description available
bits : 17 - 17 (1 bit)
access : read-write
IRQ_TEMPPANIC : no description available
bits : 27 - 27 (1 bit)
access : read-write
IRQ_TEMPLOW : no description available
bits : 28 - 28 (1 bit)
access : read-write
IRQ_TEMPHIGH : no description available
bits : 29 - 29 (1 bit)
access : read-write
IRQ_ANA_BO : no description available
bits : 30 - 30 (1 bit)
access : read-write
IRQ_DIG_BO : no description available
bits : 31 - 31 (1 bit)
access : read-write
Miscellaneous Register 1
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDS1_CLK_SEL : no description available
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Arm PLL
#00001 : 00001
System PLL
#00010 : 00010
ref_pfd4_clk == pll2_pfd0_clk
#00011 : 00011
ref_pfd5_clk == pll2_pfd1_clk
#00100 : 00100
ref_pfd6_clk == pll2_pfd2_clk
#00101 : 00101
ref_pfd7_clk == pll2_pfd3_clk
#00110 : 00110
Audio PLL
#00111 : 00111
Video PLL
#01001 : 01001
ethernet ref clock (ENET_PLL)
#01100 : 01100
USB1 PLL clock
#01101 : 01101
USB2 PLL clock
#01110 : 01110
ref_pfd0_clk == pll3_pfd0_clk
#01111 : 01111
ref_pfd1_clk == pll3_pfd1_clk
#10000 : 10000
ref_pfd2_clk == pll3_pfd2_clk
#10001 : 10001
ref_pfd3_clk == pll3_pfd3_clk
#10010 : 10010
xtal (24M)
End of enumeration elements list.
LVDS2_CLK_SEL : no description available
bits : 5 - 9 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Arm PLL
#00001 : 00001
System PLL
#00010 : 00010
ref_pfd4_clk == pll2_pfd0_clk
#00011 : 00011
ref_pfd5_clk == pll2_pfd1_clk
#00100 : 00100
ref_pfd6_clk == pll2_pfd2_clk
#00101 : 00101
ref_pfd7_clk == pll2_pfd3_clk
#00110 : 00110
Audio PLL
#00111 : 00111
Video PLL
#01000 : 01000
MLB PLL
#01001 : 01001
ethernet ref clock (ENET_PLL)
#01010 : 01010
PCIe ref clock (125M)
#01100 : 01100
USB1 PLL clock
#01101 : 01101
USB2 PLL clock
#01110 : 01110
ref_pfd0_clk == pll3_pfd0_clk
#01111 : 01111
ref_pfd1_clk == pll3_pfd1_clk
#10000 : 10000
ref_pfd2_clk == pll3_pfd2_clk
#10001 : 10001
ref_pfd3_clk == pll3_pfd3_clk
#10010 : 10010
xtal (24M)
#10011 : 10011
LVDS1 (loopback)
#10100 : 10100
LVDS2 (not useful)
End of enumeration elements list.
LVDSCLK1_OBEN : no description available
bits : 10 - 10 (1 bit)
access : read-write
LVDSCLK2_OBEN : no description available
bits : 11 - 11 (1 bit)
access : read-write
LVDSCLK1_IBEN : no description available
bits : 12 - 12 (1 bit)
access : read-write
LVDSCLK2_IBEN : no description available
bits : 13 - 13 (1 bit)
access : read-write
PFD_480_AUTOGATE_EN : no description available
bits : 16 - 16 (1 bit)
access : read-write
PFD_528_AUTOGATE_EN : no description available
bits : 17 - 17 (1 bit)
access : read-write
IRQ_TEMPPANIC : no description available
bits : 27 - 27 (1 bit)
access : read-write
IRQ_TEMPLOW : no description available
bits : 28 - 28 (1 bit)
access : read-write
IRQ_TEMPHIGH : no description available
bits : 29 - 29 (1 bit)
access : read-write
IRQ_ANA_BO : no description available
bits : 30 - 30 (1 bit)
access : read-write
IRQ_DIG_BO : no description available
bits : 31 - 31 (1 bit)
access : read-write
Miscellaneous Register 1
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDS1_CLK_SEL : no description available
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Arm PLL
#00001 : 00001
System PLL
#00010 : 00010
ref_pfd4_clk == pll2_pfd0_clk
#00011 : 00011
ref_pfd5_clk == pll2_pfd1_clk
#00100 : 00100
ref_pfd6_clk == pll2_pfd2_clk
#00101 : 00101
ref_pfd7_clk == pll2_pfd3_clk
#00110 : 00110
Audio PLL
#00111 : 00111
Video PLL
#01001 : 01001
ethernet ref clock (ENET_PLL)
#01100 : 01100
USB1 PLL clock
#01101 : 01101
USB2 PLL clock
#01110 : 01110
ref_pfd0_clk == pll3_pfd0_clk
#01111 : 01111
ref_pfd1_clk == pll3_pfd1_clk
#10000 : 10000
ref_pfd2_clk == pll3_pfd2_clk
#10001 : 10001
ref_pfd3_clk == pll3_pfd3_clk
#10010 : 10010
xtal (24M)
End of enumeration elements list.
LVDS2_CLK_SEL : no description available
bits : 5 - 9 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Arm PLL
#00001 : 00001
System PLL
#00010 : 00010
ref_pfd4_clk == pll2_pfd0_clk
#00011 : 00011
ref_pfd5_clk == pll2_pfd1_clk
#00100 : 00100
ref_pfd6_clk == pll2_pfd2_clk
#00101 : 00101
ref_pfd7_clk == pll2_pfd3_clk
#00110 : 00110
Audio PLL
#00111 : 00111
Video PLL
#01000 : 01000
MLB PLL
#01001 : 01001
ethernet ref clock (ENET_PLL)
#01010 : 01010
PCIe ref clock (125M)
#01100 : 01100
USB1 PLL clock
#01101 : 01101
USB2 PLL clock
#01110 : 01110
ref_pfd0_clk == pll3_pfd0_clk
#01111 : 01111
ref_pfd1_clk == pll3_pfd1_clk
#10000 : 10000
ref_pfd2_clk == pll3_pfd2_clk
#10001 : 10001
ref_pfd3_clk == pll3_pfd3_clk
#10010 : 10010
xtal (24M)
#10011 : 10011
LVDS1 (loopback)
#10100 : 10100
LVDS2 (not useful)
End of enumeration elements list.
LVDSCLK1_OBEN : no description available
bits : 10 - 10 (1 bit)
access : read-write
LVDSCLK2_OBEN : no description available
bits : 11 - 11 (1 bit)
access : read-write
LVDSCLK1_IBEN : no description available
bits : 12 - 12 (1 bit)
access : read-write
LVDSCLK2_IBEN : no description available
bits : 13 - 13 (1 bit)
access : read-write
PFD_480_AUTOGATE_EN : no description available
bits : 16 - 16 (1 bit)
access : read-write
PFD_528_AUTOGATE_EN : no description available
bits : 17 - 17 (1 bit)
access : read-write
IRQ_TEMPPANIC : no description available
bits : 27 - 27 (1 bit)
access : read-write
IRQ_TEMPLOW : no description available
bits : 28 - 28 (1 bit)
access : read-write
IRQ_TEMPHIGH : no description available
bits : 29 - 29 (1 bit)
access : read-write
IRQ_ANA_BO : no description available
bits : 30 - 30 (1 bit)
access : read-write
IRQ_DIG_BO : no description available
bits : 31 - 31 (1 bit)
access : read-write
Miscellaneous Control Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG0_BO_OFFSET : no description available
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
#100 : 100
Brownout offset = 0.100V
#111 : 111
Brownout offset = 0.175V
End of enumeration elements list.
REG0_BO_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#1 : 1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG0_ENABLE_BO : no description available
bits : 5 - 5 (1 bit)
access : read-write
PLL3_disable : no description available
bits : 7 - 7 (1 bit)
access : read-write
REG1_BO_OFFSET : no description available
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
#100 : 100
Brownout offset = 0.100V
#111 : 111
Brownout offset = 0.175V
End of enumeration elements list.
REG1_BO_STATUS : no description available
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#1 : 1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG1_ENABLE_BO : no description available
bits : 13 - 13 (1 bit)
access : read-write
AUDIO_DIV_LSB : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#00 : 00
divide by 1 (Default)
#01 : 01
divide by 2
End of enumeration elements list.
REG2_BO_OFFSET : no description available
bits : 16 - 18 (3 bit)
access : read-only
Enumeration:
#100 : 100
Brownout offset = 0.100V
#111 : 111
Brownout offset = 0.175V
End of enumeration elements list.
REG2_BO_STATUS : no description available
bits : 19 - 19 (1 bit)
access : read-only
REG2_ENABLE_BO : no description available
bits : 21 - 21 (1 bit)
access : read-write
REG2_OK : no description available
bits : 22 - 22 (1 bit)
access : read-only
AUDIO_DIV_MSB : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#00 : 00
divide by 1 (Default)
#01 : 01
divide by 2
End of enumeration elements list.
REG0_STEP_TIME : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
64
#01 : 01
128
#10 : 10
256
#11 : 11
512
End of enumeration elements list.
REG1_STEP_TIME : no description available
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
64
#01 : 01
128
#10 : 10
256
#11 : 11
512
End of enumeration elements list.
REG2_STEP_TIME : no description available
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 00
64
#01 : 01
128
#10 : 10
256
#11 : 11
512
End of enumeration elements list.
VIDEO_DIV : no description available
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
divide by 1 (Default)
#01 : 01
divide by 2
#10 : 10
divide by 1
#11 : 11
divide by 4
End of enumeration elements list.
Miscellaneous Control Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG0_BO_OFFSET : no description available
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
#100 : 100
Brownout offset = 0.100V
#111 : 111
Brownout offset = 0.175V
End of enumeration elements list.
REG0_BO_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#1 : 1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG0_ENABLE_BO : no description available
bits : 5 - 5 (1 bit)
access : read-write
PLL3_disable : no description available
bits : 7 - 7 (1 bit)
access : read-write
REG1_BO_OFFSET : no description available
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
#100 : 100
Brownout offset = 0.100V
#111 : 111
Brownout offset = 0.175V
End of enumeration elements list.
REG1_BO_STATUS : no description available
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#1 : 1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG1_ENABLE_BO : no description available
bits : 13 - 13 (1 bit)
access : read-write
AUDIO_DIV_LSB : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#00 : 00
divide by 1 (Default)
#01 : 01
divide by 2
End of enumeration elements list.
REG2_BO_OFFSET : no description available
bits : 16 - 18 (3 bit)
access : read-only
Enumeration:
#100 : 100
Brownout offset = 0.100V
#111 : 111
Brownout offset = 0.175V
End of enumeration elements list.
REG2_BO_STATUS : no description available
bits : 19 - 19 (1 bit)
access : read-only
REG2_ENABLE_BO : no description available
bits : 21 - 21 (1 bit)
access : read-write
REG2_OK : no description available
bits : 22 - 22 (1 bit)
access : read-only
AUDIO_DIV_MSB : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#00 : 00
divide by 1 (Default)
#01 : 01
divide by 2
End of enumeration elements list.
REG0_STEP_TIME : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
64
#01 : 01
128
#10 : 10
256
#11 : 11
512
End of enumeration elements list.
REG1_STEP_TIME : no description available
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
64
#01 : 01
128
#10 : 10
256
#11 : 11
512
End of enumeration elements list.
REG2_STEP_TIME : no description available
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 00
64
#01 : 01
128
#10 : 10
256
#11 : 11
512
End of enumeration elements list.
VIDEO_DIV : no description available
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
divide by 1 (Default)
#01 : 01
divide by 2
#10 : 10
divide by 1
#11 : 11
divide by 4
End of enumeration elements list.
Miscellaneous Control Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG0_BO_OFFSET : no description available
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
#100 : 100
Brownout offset = 0.100V
#111 : 111
Brownout offset = 0.175V
End of enumeration elements list.
REG0_BO_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#1 : 1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG0_ENABLE_BO : no description available
bits : 5 - 5 (1 bit)
access : read-write
PLL3_disable : no description available
bits : 7 - 7 (1 bit)
access : read-write
REG1_BO_OFFSET : no description available
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
#100 : 100
Brownout offset = 0.100V
#111 : 111
Brownout offset = 0.175V
End of enumeration elements list.
REG1_BO_STATUS : no description available
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#1 : 1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG1_ENABLE_BO : no description available
bits : 13 - 13 (1 bit)
access : read-write
AUDIO_DIV_LSB : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#00 : 00
divide by 1 (Default)
#01 : 01
divide by 2
End of enumeration elements list.
REG2_BO_OFFSET : no description available
bits : 16 - 18 (3 bit)
access : read-only
Enumeration:
#100 : 100
Brownout offset = 0.100V
#111 : 111
Brownout offset = 0.175V
End of enumeration elements list.
REG2_BO_STATUS : no description available
bits : 19 - 19 (1 bit)
access : read-only
REG2_ENABLE_BO : no description available
bits : 21 - 21 (1 bit)
access : read-write
REG2_OK : no description available
bits : 22 - 22 (1 bit)
access : read-only
AUDIO_DIV_MSB : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#00 : 00
divide by 1 (Default)
#01 : 01
divide by 2
End of enumeration elements list.
REG0_STEP_TIME : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
64
#01 : 01
128
#10 : 10
256
#11 : 11
512
End of enumeration elements list.
REG1_STEP_TIME : no description available
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
64
#01 : 01
128
#10 : 10
256
#11 : 11
512
End of enumeration elements list.
REG2_STEP_TIME : no description available
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 00
64
#01 : 01
128
#10 : 10
256
#11 : 11
512
End of enumeration elements list.
VIDEO_DIV : no description available
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
divide by 1 (Default)
#01 : 01
divide by 2
#10 : 10
divide by 1
#11 : 11
divide by 4
End of enumeration elements list.
Miscellaneous Control Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REG0_BO_OFFSET : no description available
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
#100 : 100
Brownout offset = 0.100V
#111 : 111
Brownout offset = 0.175V
End of enumeration elements list.
REG0_BO_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#1 : 1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG0_ENABLE_BO : no description available
bits : 5 - 5 (1 bit)
access : read-write
PLL3_disable : no description available
bits : 7 - 7 (1 bit)
access : read-write
REG1_BO_OFFSET : no description available
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
#100 : 100
Brownout offset = 0.100V
#111 : 111
Brownout offset = 0.175V
End of enumeration elements list.
REG1_BO_STATUS : no description available
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#1 : 1
Brownout, supply is below target minus brownout offset.
End of enumeration elements list.
REG1_ENABLE_BO : no description available
bits : 13 - 13 (1 bit)
access : read-write
AUDIO_DIV_LSB : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#00 : 00
divide by 1 (Default)
#01 : 01
divide by 2
End of enumeration elements list.
REG2_BO_OFFSET : no description available
bits : 16 - 18 (3 bit)
access : read-only
Enumeration:
#100 : 100
Brownout offset = 0.100V
#111 : 111
Brownout offset = 0.175V
End of enumeration elements list.
REG2_BO_STATUS : no description available
bits : 19 - 19 (1 bit)
access : read-only
REG2_ENABLE_BO : no description available
bits : 21 - 21 (1 bit)
access : read-write
REG2_OK : no description available
bits : 22 - 22 (1 bit)
access : read-only
AUDIO_DIV_MSB : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#00 : 00
divide by 1 (Default)
#01 : 01
divide by 2
End of enumeration elements list.
REG0_STEP_TIME : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
64
#01 : 01
128
#10 : 10
256
#11 : 11
512
End of enumeration elements list.
REG1_STEP_TIME : no description available
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
64
#01 : 01
128
#10 : 10
256
#11 : 11
512
End of enumeration elements list.
REG2_STEP_TIME : no description available
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 00
64
#01 : 01
128
#10 : 10
256
#11 : 11
512
End of enumeration elements list.
VIDEO_DIV : no description available
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
divide by 1 (Default)
#01 : 01
divide by 2
#10 : 10
divide by 1
#11 : 11
divide by 4
End of enumeration elements list.
Low Power Control Register
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC_OSC_EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use XTAL OSC to source the 24MHz clock
#1 : 1
Use RC OSC
End of enumeration elements list.
RC_OSC_PROG : no description available
bits : 1 - 3 (3 bit)
access : read-write
OSC_SEL : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
XTAL OSC
#1 : 1
RC OSC
End of enumeration elements list.
LPBG_SEL : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal power bandgap
#1 : 1
Low power bandgap
End of enumeration elements list.
LPBG_TEST : no description available
bits : 6 - 6 (1 bit)
access : read-write
REFTOP_IBIAS_OFF : no description available
bits : 7 - 7 (1 bit)
access : read-write
L1_PWRGATE : no description available
bits : 8 - 8 (1 bit)
access : read-write
L2_PWRGATE : no description available
bits : 9 - 9 (1 bit)
access : read-write
CPU_PWRGATE : no description available
bits : 10 - 10 (1 bit)
access : read-write
DISPLAY_PWRGATE : no description available
bits : 11 - 11 (1 bit)
access : read-write
RCOSC_CG_OVERRIDE : no description available
bits : 13 - 13 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : no description available
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
0.25ms
#01 : 01
0.5ms
#10 : 10
1ms
#11 : 11
2ms
End of enumeration elements list.
XTALOSC_PWRUP_STAT : no description available
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not stable
#1 : 1
Stable and ready to use
End of enumeration elements list.
MIX_PWRGATE : no description available
bits : 17 - 17 (1 bit)
access : read-write
GPU_PWRGATE : no description available
bits : 18 - 18 (1 bit)
access : read-write
Low Power Control Register
address_offset : 0x754 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC_OSC_EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use XTAL OSC to source the 24MHz clock
#1 : 1
Use RC OSC
End of enumeration elements list.
RC_OSC_PROG : no description available
bits : 1 - 3 (3 bit)
access : read-write
OSC_SEL : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
XTAL OSC
#1 : 1
RC OSC
End of enumeration elements list.
LPBG_SEL : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal power bandgap
#1 : 1
Low power bandgap
End of enumeration elements list.
LPBG_TEST : no description available
bits : 6 - 6 (1 bit)
access : read-write
REFTOP_IBIAS_OFF : no description available
bits : 7 - 7 (1 bit)
access : read-write
L1_PWRGATE : no description available
bits : 8 - 8 (1 bit)
access : read-write
L2_PWRGATE : no description available
bits : 9 - 9 (1 bit)
access : read-write
CPU_PWRGATE : no description available
bits : 10 - 10 (1 bit)
access : read-write
DISPLAY_PWRGATE : no description available
bits : 11 - 11 (1 bit)
access : read-write
RCOSC_CG_OVERRIDE : no description available
bits : 13 - 13 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : no description available
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
0.25ms
#01 : 01
0.5ms
#10 : 10
1ms
#11 : 11
2ms
End of enumeration elements list.
XTALOSC_PWRUP_STAT : no description available
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not stable
#1 : 1
Stable and ready to use
End of enumeration elements list.
MIX_PWRGATE : no description available
bits : 17 - 17 (1 bit)
access : read-write
GPU_PWRGATE : no description available
bits : 18 - 18 (1 bit)
access : read-write
Low Power Control Register
address_offset : 0x9CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC_OSC_EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use XTAL OSC to source the 24MHz clock
#1 : 1
Use RC OSC
End of enumeration elements list.
RC_OSC_PROG : no description available
bits : 1 - 3 (3 bit)
access : read-write
OSC_SEL : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
XTAL OSC
#1 : 1
RC OSC
End of enumeration elements list.
LPBG_SEL : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal power bandgap
#1 : 1
Low power bandgap
End of enumeration elements list.
LPBG_TEST : no description available
bits : 6 - 6 (1 bit)
access : read-write
REFTOP_IBIAS_OFF : no description available
bits : 7 - 7 (1 bit)
access : read-write
L1_PWRGATE : no description available
bits : 8 - 8 (1 bit)
access : read-write
L2_PWRGATE : no description available
bits : 9 - 9 (1 bit)
access : read-write
CPU_PWRGATE : no description available
bits : 10 - 10 (1 bit)
access : read-write
DISPLAY_PWRGATE : no description available
bits : 11 - 11 (1 bit)
access : read-write
RCOSC_CG_OVERRIDE : no description available
bits : 13 - 13 (1 bit)
access : read-write
XTALOSC_PWRUP_DELAY : no description available
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
0.25ms
#01 : 01
0.5ms
#10 : 10
1ms
#11 : 11
2ms
End of enumeration elements list.
XTALOSC_PWRUP_STAT : no description available
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not stable
#1 : 1
Stable and ready to use
End of enumeration elements list.
MIX_PWRGATE : no description available
bits : 17 - 17 (1 bit)
access : read-write
GPU_PWRGATE : no description available
bits : 18 - 18 (1 bit)
access : read-write
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