\n

MLB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x3E0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MLBC0

MS1

MSS

MSD

MIEN

MLBC1

ACTL

ACSR0

ACSR1

ACMR0

ACMR1

HCTL

HCMR0

HCMR1

HCER0

HCER1

HCBR0

HCBR1

MS0

MDAT0

MDAT1

MDAT2

MDAT3

MLBPC2

MDWE0

MDWE1

MDWE2

MDWE3

MCTL

MADR


MLBC0

MediaLB Control 0 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MLBC0 MLBC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MLBEN MLBCLK_2_0 MLBLK ASYRETRY CTLRETRY FCNT

MLBEN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MLBCLK_2_0 : no description available
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

#000 : 000

256xFs (for MLBPEN = 0)

#001 : 001

512xFs (for MLBPEN = 0)

#010 : 010

1024xFs (for MLBPEN = 0)

End of enumeration elements list.

MLBLK : no description available
bits : 7 - 7 (1 bit)
access : read-only

ASYRETRY : no description available
bits : 12 - 12 (1 bit)
access : read-write

CTLRETRY : no description available
bits : 14 - 14 (1 bit)
access : read-write

FCNT : no description available
bits : 15 - 17 (3 bit)
access : read-write

Enumeration:

#000 : 000

1 frame per sub-buffer (Operation is the same as Standard mode.)

#001 : 001

2 frames per sub-buffer

#010 : 010

4 frames per sub-buffer

#011 : 011

8 frames per sub-buffer

#100 : 100

16 frames per sub-buffer

#101 : 101

32 frames per sub-buffer

#110 : 110

64 frames per sub-buffer

End of enumeration elements list.


MS1

MediaLB Channel Status1 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MS1 MS1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCS_63_32

MCS_63_32 : no description available
bits : 0 - 31 (32 bit)
access : read-only


MSS

MediaLB System Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSS MSS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTSYSCMD LKSYSCMD ULKSYSCMD CSSYSCMD SWSYSCMD SERVREQ

RSTSYSCMD : no description available
bits : 0 - 0 (1 bit)
access : read-only

LKSYSCMD : no description available
bits : 1 - 1 (1 bit)
access : read-only

ULKSYSCMD : no description available
bits : 2 - 2 (1 bit)
access : read-only

CSSYSCMD : no description available
bits : 3 - 3 (1 bit)
access : read-only

SWSYSCMD : no description available
bits : 4 - 4 (1 bit)
access : read-only

SERVREQ : no description available
bits : 5 - 5 (1 bit)
access : read-write


MSD

MediaLB System Data Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSD MSD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SD0_7_0 SD1_7_0 SD2_7_0 SD3_7_0

SD0_7_0 : no description available
bits : 0 - 7 (8 bit)
access : read-only

SD1_7_0 : no description available
bits : 8 - 15 (8 bit)
access : read-only

SD2_7_0 : no description available
bits : 16 - 23 (8 bit)
access : read-only

SD3_7_0 : no description available
bits : 24 - 31 (8 bit)
access : read-only


MIEN

MediaLB Interrupt Enable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIEN MIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISOC_PE ISOC_BUFO SYNC_PE ARX_DONE ARX_PE ARX_BREAK ATX_DONE ATX_PE ATX_BREAK CRX_DONE CRX_PE CRX_BREAK CTX_DONE CTX_PE CTX_BREAK

ISOC_PE : no description available
bits : 0 - 0 (1 bit)
access : read-write

ISOC_BUFO : no description available
bits : 1 - 1 (1 bit)
access : read-write

SYNC_PE : no description available
bits : 16 - 16 (1 bit)
access : read-write

ARX_DONE : no description available
bits : 17 - 17 (1 bit)
access : read-write

ARX_PE : no description available
bits : 18 - 18 (1 bit)
access : read-write

ARX_BREAK : no description available
bits : 19 - 19 (1 bit)
access : read-write

ATX_DONE : no description available
bits : 20 - 20 (1 bit)
access : read-write

ATX_PE : no description available
bits : 21 - 21 (1 bit)
access : read-write

ATX_BREAK : no description available
bits : 22 - 22 (1 bit)
access : read-write

CRX_DONE : no description available
bits : 24 - 24 (1 bit)
access : read-write

CRX_PE : no description available
bits : 25 - 25 (1 bit)
access : read-write

CRX_BREAK : no description available
bits : 26 - 26 (1 bit)
access : read-write

CTX_DONE : no description available
bits : 27 - 27 (1 bit)
access : read-write

CTX_PE : no description available
bits : 28 - 28 (1 bit)
access : read-write

CTX_BREAK : no description available
bits : 29 - 29 (1 bit)
access : read-write


MLBC1

MediaLB Control 1 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MLBC1 MLBC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK CLKM NDA_7_0

LOCK : no description available
bits : 6 - 6 (1 bit)
access : read-only

CLKM : no description available
bits : 7 - 7 (1 bit)
access : read-only

NDA_7_0 : no description available
bits : 8 - 15 (8 bit)
access : read-write


ACTL

AHB Control Register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACTL ACTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCE SMX DMA_MODE MPB

SCE : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Hardware clears interrupt after a ACSRn register read

#1 : 1

Software clears interrupt

End of enumeration elements list.

SMX : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

ACSR0 generates an interrupt on ahb_int[0]; ACSR1 generates an interrupt on ahb_int[1]

#1 : 1

ACSR0 and ACSR1 generate an interrupts on ahb_int[0] only

End of enumeration elements list.

DMA_MODE : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA Mode 0

#1 : 1

DMA Mode 1

End of enumeration elements list.

MPB : no description available
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Single-packet mode

#1 : 1

Multiple-packet mode

End of enumeration elements list.


ACSR0

AHB Channel Status 0 Register
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ACSR0 ACSR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHS

CHS : no description available
bits : 0 - 31 (32 bit)
access : read-only

Enumeration:

#0 : 0

None

#1 : 1

Interrupt

End of enumeration elements list.


ACSR1

AHB Channel Status 1 Register
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ACSR1 ACSR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHS

CHS : no description available
bits : 0 - 31 (32 bit)
access : read-only

Enumeration:

#0 : 0

None

#1 : 1

Interrupt

End of enumeration elements list.


ACMR0

AHB Channel Mask 0 Register
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMR0 ACMR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHM_31_0

CHM_31_0 : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

Masked

#1 : 1

Unmasked

End of enumeration elements list.


ACMR1

AHB Channel Mask 1 Register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMR1 ACMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHM

CHM : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

Masked

#1 : 1

Unmasked

End of enumeration elements list.


HCTL

HBI Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTL HCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RST0 RST1 EN

RST0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#1 : 1

reset

#0 : 0

active

End of enumeration elements list.

RST1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#1 : 1

reset

#0 : 0

active

End of enumeration elements list.

EN : no description available
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#1 : 1

enabled

#0 : 0

disabled

End of enumeration elements list.


HCMR0

HBI Channel Mask 0 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCMR0 HCMR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHM_31_0_P

CHM_31_0_P : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

masked

#1 : 1

unmasked

End of enumeration elements list.


HCMR1

HBI Channel Mask 1 Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCMR1 HCMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHM_63_32

CHM_63_32 : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

masked

#1 : 1

unmasked

End of enumeration elements list.


HCER0

HBI Channel Error 0 Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCER0 HCER0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CERR_31_0

CERR_31_0 : no description available
bits : 0 - 31 (32 bit)
access : read-only


HCER1

HBI Channel Error 1 Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCER1 HCER1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CERR_63_32

CERR_63_32 : no description available
bits : 0 - 31 (32 bit)
access : read-only


HCBR0

HBI Channel Busy 0 Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCBR0 HCBR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHB_31_0

CHB_31_0 : no description available
bits : 0 - 31 (32 bit)
access : read-only

Enumeration:

#0 : 0

idle

#1 : 1

busy

End of enumeration elements list.


HCBR1

HBI Channel Busy 1 Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCBR1 HCBR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHB_63_32

CHB_63_32 : no description available
bits : 0 - 31 (32 bit)
access : read-only

Enumeration:

#0 : 0

idle

#1 : 1

busy

End of enumeration elements list.


MS0

MediaLB Channel Status 0 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MS0 MS0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCS_31_0

MCS_31_0 : no description available
bits : 0 - 31 (32 bit)
access : read-only


MDAT0

MIF Data 0 Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDAT0 MDAT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_31_0

DATA_31_0 : no description available
bits : 0 - 31 (32 bit)
access : read-write


MDAT1

MIF Data 1 Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDAT1 MDAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_63_32

DATA_63_32 : no description available
bits : 0 - 31 (32 bit)
access : read-write


MDAT2

MIF Data 2 Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDAT2 MDAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_95_64

DATA_95_64 : no description available
bits : 0 - 31 (32 bit)
access : read-write


MDAT3

MIF Data 3 Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDAT3 MDAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_127_96

DATA_127_96 : no description available
bits : 0 - 31 (32 bit)
access : read-write


MLBPC2

MediaLB 6-pin Control 2 Register
address_offset : 0xD Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MLBPC2 MLBPC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDOPC MORCD MORCE

SDOPC : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

MLB_SIG / MLB_DATA launch at rising edge of MLB_CLK(default)

#1 : 1

MLB_SIG / MLB_DATA launch at falling edge of MLB_CLK

End of enumeration elements list.

MORCD : no description available
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

#0 : 0

Divider factor is 1.

#1 : 1

Divider factor is 2.

End of enumeration elements list.

MORCE : no description available
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable MLB output reference clock.

#1 : 1

Disable MLB output reference clock.

End of enumeration elements list.


MDWE0

MIF Data Write Enable 0 Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDWE0 MDWE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK_31_0

MASK_31_0 : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.


MDWE1

MIF Data Write Enable 1 Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDWE1 MDWE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK_63_32

MASK_63_32 : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.


MDWE2

MIF Data Write Enable 2 Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDWE2 MDWE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK_95_64

MASK_95_64 : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.


MDWE3

MIF Data Write Enable 3 Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDWE3 MDWE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK_127_96

MASK_127_96 : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

disabled

#1 : 1

enabled

End of enumeration elements list.


MCTL

MIF Control Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MCTL MCTL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XCMP

XCMP : no description available
bits : 0 - 0 (1 bit)
access : read-only


MADR

MIF Address Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MADR MADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR_7_0 ADDR_13_8 TB WNR

ADDR_7_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

ADDR_13_8 : no description available
bits : 8 - 13 (6 bit)
access : read-write

TB : no description available
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

selects CTR

#1 : 1

selects DBR

End of enumeration elements list.

WNR : no description available
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

read

#1 : 1

write

End of enumeration elements list.



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