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ESAI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ETDR

TFCR

TX0

TFSR

RX0

RFCR

TX1

RFSR

RX1

TX2

RX2

TX3

TX4

RX3

TX5

ERDR

ECR

TSR

ESR

SAISR

SAICR

TCR

TCCR

RCR

RCCR

TSMA

TSMB

RSMA

RSMB

PRRC

PCRC


ETDR

ESAI Transmit Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ETDR ETDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETDR

ETDR : no description available
bits : 0 - 31 (32 bit)
access : write-only


TFCR

Transmit FIFO Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TFCR TFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFE TFR TE0 TE1 TE2 TE3 TE4 TE5 TFWM TWA TIEN

TFE : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transmit FIFO disabled.

#1 : 1

Transmit FIFO enabled.

End of enumeration elements list.

TFR : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transmit FIFO not reset.

#1 : 1

Transmit FIFO reset.

End of enumeration elements list.

TE0 : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transmitter #0 is not using the Transmit FIFO.

#1 : 1

Transmitter #0 is using the Transmit FIFO.

End of enumeration elements list.

TE1 : no description available
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transmitter #1 is not using the Transmit FIFO.

#1 : 1

Transmitter #1 is using the Transmit FIFO.

End of enumeration elements list.

TE2 : no description available
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transmitter #2 is not using the Transmit FIFO.

#1 : 1

Transmitter #2 is using the Transmit FIFO.

End of enumeration elements list.

TE3 : no description available
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transmitter #3 is not using the Transmit FIFO.

#1 : 1

Transmitter #3 is using the Transmit FIFO.

End of enumeration elements list.

TE4 : no description available
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transmitter #4 is not using the Transmit FIFO.

#1 : 1

Transmitter #4 is using the Transmit FIFO.

End of enumeration elements list.

TE5 : no description available
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transmitter #5 is not using the Transmit FIFO.

#1 : 1

Transmitter #5 is using the Transmit FIFO.

End of enumeration elements list.

TFWM : no description available
bits : 8 - 15 (8 bit)
access : read-write

TWA : no description available
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 000

MSB of data is bit 31. Data bits 7-0 are ignored when passed to transmit shift register.

#001 : 001

MSB of data is bit 27. Data bits 3-0 are ignored when passed to transmit shift register.

#010 : 010

MSB of data is bit 23.

#011 : 011

MSB of data is bit 19. Bottom 4 bits of transmit shift register are zeroed.

#100 : 100

MSB of data is bit 15. Bottom 8 bits of transmit shift register are zeroed.

#101 : 101

MSB of data is bit 11. Bottom 12 bits of transmit shift register are zeroed.

#110 : 110

MSB of data is bit 7. Bottom 16 bits of transmit shift register are zeroed.

#111 : 111

MSB of data is bit 3. Bottom 20 bits of transmit shift register are zeroed.

End of enumeration elements list.

TIEN : no description available
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transmit Data Registers are not initialized from the FIFO once the Transmit FIFO is enabled. Software must manually initialize the Transmit Data Registers separately.

#1 : 1

Transmit Data Registers are initialized from the FIFO once the Transmit FIFO is enabled.

End of enumeration elements list.


TX0

Transmit Data Register n
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX0 TX0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXn

TXn : no description available
bits : 0 - 23 (24 bit)
access : write-only


TFSR

Transmit FIFO Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TFSR TFSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFCNT NTFI NTFO

TFCNT : no description available
bits : 0 - 7 (8 bit)
access : read-only

NTFI : no description available
bits : 8 - 10 (3 bit)
access : read-only

Enumeration:

#000 : 000

Transmitter #0 receives next word written to the Transmit FIFO.

#001 : 001

Transmitter #1 receives next word written to the Transmit FIFO.

#010 : 010

Transmitter #2 receives next word written to the Transmit FIFO.

#011 : 011

Transmitter #3 receives next word written to the Transmit FIFO.

#100 : 100

Transmitter #4 receives next word written to the Transmit FIFO.

#101 : 101

Transmitter #5 receives next word written to the Transmit FIFO.

End of enumeration elements list.

NTFO : no description available
bits : 12 - 14 (3 bit)
access : read-only

Enumeration:

#000 : 000

Transmitter #0 receives next word from the Transmit FIFO.

#001 : 001

Transmitter #1 receives next word from the Transmit FIFO.

#010 : 010

Transmitter #2 receives next word from the Transmit FIFO.

#011 : 011

Transmitter #3 receives next word from the Transmit FIFO.

#100 : 100

Transmitter #4 receives next word from the Transmit FIFO.

#101 : 101

Transmitter #5 receives next word from the Transmit FIFO.

End of enumeration elements list.


RX0

Receive Data Register n
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX0 RX0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXn

RXn : no description available
bits : 0 - 23 (24 bit)
access : read-only


RFCR

Receive FIFO Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFCR RFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFE RFR RE0 RE1 RE2 RE3 RFWM RWA REXT

RFE : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receive FIFO disabled.

#1 : 1

Receive FIFO enabled.

End of enumeration elements list.

RFR : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receive FIFO not reset.

#1 : 1

Receive FIFO reset.

End of enumeration elements list.

RE0 : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receiver #0 is not using the Receive FIFO.

#1 : 1

Receiver #0 is using the Receive FIFO.

End of enumeration elements list.

RE1 : no description available
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receiver #1 is not using the Receive FIFO.

#1 : 1

Receiver #1 is using the Receive FIFO.

End of enumeration elements list.

RE2 : no description available
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receiver #2 is not using the Receive FIFO.

#1 : 1

Receiver #2 is using the Receive FIFO.

End of enumeration elements list.

RE3 : no description available
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receiver #3 is not using the Receive FIFO.

#1 : 1

Receiver #3 is using the Receive FIFO.

End of enumeration elements list.

RFWM : no description available
bits : 8 - 15 (8 bit)
access : read-write

RWA : no description available
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 000

MSB of data is at bit 31. Data bits 7-0 are zeroed.

#001 : 001

MSB of data is at bit 27. Data bits 3-0 are zeroed.

#010 : 010

MSB of data is at bit 23.

#011 : 011

MSB of data is at bit 19. Data bits 3-0 from receive shift register are ignored.

#100 : 100

MSB of data is at bit 15. Data bits 7-0 from receive shift register are ignored.

#101 : 101

MSB of data is at bit 11. Data bits 11-0 from receive shift register are ignored.

#110 : 110

MSB of data is at bit 7. Data bits 15-0 from receive shift register are ignored.

#111 : 111

MSB of data is at bit 3. Data bits 19-0 from receive shift register are ignored.

End of enumeration elements list.

REXT : no description available
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Receive data is zero extended.

#1 : 1

Receive data is sign extended.

End of enumeration elements list.


TX1

Transmit Data Register n
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX1 TX1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXn

TXn : no description available
bits : 0 - 23 (24 bit)
access : write-only


RFSR

Receive FIFO Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RFSR RFSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFCNT NRFO NRFI

RFCNT : no description available
bits : 0 - 7 (8 bit)
access : read-only

NRFO : no description available
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

#00 : 00

Receiver #0 returns next word from the Receive FIFO.

#01 : 01

Receiver #1 returns next word from the Receive FIFO.

#10 : 10

Receiver #2 returns next word from the Receive FIFO.

#11 : 11

Receiver #3 returns next word from the Receive FIFO.

End of enumeration elements list.

NRFI : no description available
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

#00 : 00

Receiver #0 returns next word to the Receive FIFO.

#01 : 01

Receiver #1 returns next word to the Receive FIFO.

#10 : 10

Receiver #2 returns next word to the Receive FIFO.

#11 : 11

Receiver #3 returns next word to the Receive FIFO.

End of enumeration elements list.


RX1

Receive Data Register n
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX1 RX1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXn

RXn : no description available
bits : 0 - 23 (24 bit)
access : read-only


TX2

Transmit Data Register n
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX2 TX2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXn

TXn : no description available
bits : 0 - 23 (24 bit)
access : write-only


RX2

Receive Data Register n
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX2 RX2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXn

RXn : no description available
bits : 0 - 23 (24 bit)
access : read-only


TX3

Transmit Data Register n
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX3 TX3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXn

TXn : no description available
bits : 0 - 23 (24 bit)
access : write-only


TX4

Transmit Data Register n
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX4 TX4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXn

TXn : no description available
bits : 0 - 23 (24 bit)
access : write-only


RX3

Receive Data Register n
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX3 RX3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXn

RXn : no description available
bits : 0 - 23 (24 bit)
access : read-only


TX5

Transmit Data Register n
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX5 TX5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXn

TXn : no description available
bits : 0 - 23 (24 bit)
access : write-only


ERDR

ESAI Receive Data Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ERDR ERDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERDR

ERDR : no description available
bits : 0 - 31 (32 bit)
access : read-only


ECR

ESAI Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECR ECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ESAIEN ERST ERO ERI ETO ETI

ESAIEN : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

ESAI disabled.

#1 : 1

ESAI enabled.

End of enumeration elements list.

ERST : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

ESAI not reset.

#1 : 1

ESAI reset.

End of enumeration elements list.

ERO : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

HCKR pin has normal function.

#1 : 1

EXTAL driven onto HCKR pin.

End of enumeration elements list.

ERI : no description available
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

HCKR pin has normal function.

#1 : 1

EXTAL muxed into HCKR input.

End of enumeration elements list.

ETO : no description available
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

HCKT pin has normal function.

#1 : 1

EXTAL driven onto HCKT pin.

End of enumeration elements list.

ETI : no description available
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

HCKT pin has normal function.

#1 : 1

EXTAL muxed into HCKT input.

End of enumeration elements list.


TSR

ESAI Transmit Slot Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSR TSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSR

TSR : no description available
bits : 0 - 23 (24 bit)
access : write-only


ESR

ESAI Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ESR ESR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD RED RDE RLS TD TED TDE TLS TFE RFF TINIT

RD : no description available
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

RD is not the highest priority active interrupt.

#1 : 1

RD is the highest priority active interrupt.

End of enumeration elements list.

RED : no description available
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

RED is not the highest priority active interrupt.

#1 : 1

RED is the highest priority active interrupt.

End of enumeration elements list.

RDE : no description available
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

RDE is not the highest priority active interrupt.

#1 : 1

RDE is the highest priority active interrupt.

End of enumeration elements list.

RLS : no description available
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

RLS is not the highest priority active interrupt.

#1 : 1

RLS is the highest priority active interrupt.

End of enumeration elements list.

TD : no description available
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

TD is not the highest priority active interrupt.

#1 : 1

TD is the highest priority active interrupt.

End of enumeration elements list.

TED : no description available
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

TED is not the highest priority active interrupt.

#1 : 1

TED is the highest priority active interrupt.

End of enumeration elements list.

TDE : no description available
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

TDE is not the highest priority active interrupt.

#1 : 1

TDE is the highest priority active interrupt.

End of enumeration elements list.

TLS : no description available
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

TLS is not the highest priority active interrupt.

#1 : 1

TLS is the highest priority active interrupt.

End of enumeration elements list.

TFE : no description available
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

Number of empty slots in Transmit FIFO less than Transmit FIFO watermark.

#1 : 1

Number of empty slots in Transmit FIFO is equal to or greater than Transmit FIFO watermark.

End of enumeration elements list.

RFF : no description available
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

#0 : 0

Number of words in Receive FIFO less than Receive FIFO watermark.

#1 : 1

Number of words in Receive FIFO is equal to or greater than Receive FIFO watermark.

End of enumeration elements list.

TINIT : no description available
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

#0 : 0

Transmitter has finished initializing the Transmit Data Registers (or Transmit FIFO is not enabled or Transmit Initialization is not enabled).

#1 : 1

Transmitter has not finished initializing the Transmit Data Registers.

End of enumeration elements list.


SAISR

Serial Audio Interface Status Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SAISR SAISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IF0 IF1 IF2 RFS ROE RDF REDF RODF TFS TUE TDE TEDE TODFE

IF0 : no description available
bits : 0 - 0 (1 bit)
access : read-only

IF1 : no description available
bits : 1 - 1 (1 bit)
access : read-only

IF2 : no description available
bits : 2 - 2 (1 bit)
access : read-only

RFS : no description available
bits : 6 - 6 (1 bit)
access : read-only

ROE : no description available
bits : 7 - 7 (1 bit)
access : read-only

RDF : no description available
bits : 8 - 8 (1 bit)
access : read-only

REDF : no description available
bits : 9 - 9 (1 bit)
access : read-only

RODF : no description available
bits : 10 - 10 (1 bit)
access : read-only

TFS : no description available
bits : 13 - 13 (1 bit)
access : read-only

TUE : no description available
bits : 14 - 14 (1 bit)
access : read-only

TDE : no description available
bits : 15 - 15 (1 bit)
access : read-only

TEDE : no description available
bits : 16 - 16 (1 bit)
access : read-only

TODFE : no description available
bits : 17 - 17 (1 bit)
access : read-only


SAICR

Serial Audio Interface Control Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAICR SAICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF0 OF1 OF2 SYN TEBE ALC

OF0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

OF1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

OF2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

SYN : no description available
bits : 6 - 6 (1 bit)
access : read-write

TEBE : no description available
bits : 7 - 7 (1 bit)
access : read-write

ALC : no description available
bits : 8 - 8 (1 bit)
access : read-write


TCR

Transmit Control Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TE0 TE1 TE2 TE3 TE4 TE5 TSHFD TWA TMOD TSWS TFSL TFSR PADC TPR TEIE TEDIE TIE TLIE

TE0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

TE1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

TE2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

TE3 : no description available
bits : 3 - 3 (1 bit)
access : read-write

TE4 : no description available
bits : 4 - 4 (1 bit)
access : read-write

TE5 : no description available
bits : 5 - 5 (1 bit)
access : read-write

TSHFD : no description available
bits : 6 - 6 (1 bit)
access : read-write

TWA : no description available
bits : 7 - 7 (1 bit)
access : read-write

TMOD : no description available
bits : 8 - 9 (2 bit)
access : read-write

TSWS : no description available
bits : 10 - 14 (5 bit)
access : read-write

TFSL : no description available
bits : 15 - 15 (1 bit)
access : read-write

TFSR : no description available
bits : 16 - 16 (1 bit)
access : read-write

PADC : no description available
bits : 17 - 17 (1 bit)
access : read-write

TPR : no description available
bits : 19 - 19 (1 bit)
access : read-write

TEIE : no description available
bits : 20 - 20 (1 bit)
access : read-write

TEDIE : no description available
bits : 21 - 21 (1 bit)
access : read-write

TIE : no description available
bits : 22 - 22 (1 bit)
access : read-write

TLIE : no description available
bits : 23 - 23 (1 bit)
access : read-write


TCCR

Transmit Clock Control Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCCR TCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPM TPSR TDC TFP TCKP TFSP THCKP TCKD TFSD THCKD

TPM : no description available
bits : 0 - 7 (8 bit)
access : read-write

TPSR : no description available
bits : 8 - 8 (1 bit)
access : read-write

TDC : no description available
bits : 9 - 13 (5 bit)
access : read-write

TFP : no description available
bits : 14 - 17 (4 bit)
access : read-write

TCKP : no description available
bits : 18 - 18 (1 bit)
access : read-write

TFSP : no description available
bits : 19 - 19 (1 bit)
access : read-write

THCKP : no description available
bits : 20 - 20 (1 bit)
access : read-write

TCKD : no description available
bits : 21 - 21 (1 bit)
access : read-write

TFSD : no description available
bits : 22 - 22 (1 bit)
access : read-write

THCKD : no description available
bits : 23 - 23 (1 bit)
access : read-write


RCR

Receive Control Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RE0 RE1 RE2 RE3 RSHFD RWA RMOD RSWS RFSL RFSR RPR REIE REDIE RIE RLIE

RE0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

RE1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

RE2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

RE3 : no description available
bits : 3 - 3 (1 bit)
access : read-write

RSHFD : no description available
bits : 6 - 6 (1 bit)
access : read-write

RWA : no description available
bits : 7 - 7 (1 bit)
access : read-write

RMOD : no description available
bits : 8 - 9 (2 bit)
access : read-write

RSWS : no description available
bits : 10 - 14 (5 bit)
access : read-write

RFSL : no description available
bits : 15 - 15 (1 bit)
access : read-write

RFSR : no description available
bits : 16 - 16 (1 bit)
access : read-write

RPR : no description available
bits : 19 - 19 (1 bit)
access : read-write

REIE : no description available
bits : 20 - 20 (1 bit)
access : read-write

REDIE : no description available
bits : 21 - 21 (1 bit)
access : read-write

RIE : no description available
bits : 22 - 22 (1 bit)
access : read-write

RLIE : no description available
bits : 23 - 23 (1 bit)
access : read-write


RCCR

Receive Clock Control Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCCR RCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPM RPSR RDC RFP RCKP RFSP RHCKP RCKD RFSD RHCKD

RPM : no description available
bits : 0 - 7 (8 bit)
access : read-write

RPSR : no description available
bits : 8 - 8 (1 bit)
access : read-write

RDC : no description available
bits : 9 - 13 (5 bit)
access : read-write

RFP : no description available
bits : 14 - 17 (4 bit)
access : read-write

RCKP : no description available
bits : 18 - 18 (1 bit)
access : read-write

RFSP : no description available
bits : 19 - 19 (1 bit)
access : read-write

RHCKP : no description available
bits : 20 - 20 (1 bit)
access : read-write

RCKD : no description available
bits : 21 - 21 (1 bit)
access : read-write

RFSD : no description available
bits : 22 - 22 (1 bit)
access : read-write

RHCKD : no description available
bits : 23 - 23 (1 bit)
access : read-write


TSMA

Transmit Slot Mask Register A
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSMA TSMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS

TS : no description available
bits : 0 - 15 (16 bit)
access : read-write


TSMB

Transmit Slot Mask Register B
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSMB TSMB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS

TS : no description available
bits : 0 - 15 (16 bit)
access : read-write


RSMA

Receive Slot Mask Register A
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSMA RSMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS

RS : no description available
bits : 0 - 15 (16 bit)
access : read-write


RSMB

Receive Slot Mask Register B
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSMB RSMB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS

RS : no description available
bits : 0 - 15 (16 bit)
access : read-write


PRRC

Port C Direction Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRRC PRRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDC

PDC : no description available
bits : 0 - 11 (12 bit)
access : read-write


PCRC

Port C Control Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCRC PCRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC

PC : no description available
bits : 0 - 11 (12 bit)
access : read-write



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