Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8C byte (0x0)
mem_usage : registers
protection : not protected
CCM Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSCNT : no description available
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
#0000000 : 0000000
count 1 ckil
#1111111 : 1111111
count 128 ckil's
End of enumeration elements list.
COSC_EN : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable on chip oscillator
#1 : 1
enable on chip oscillator
End of enumeration elements list.
REG_BYPASS_COUNT : no description available
bits : 21 - 26 (6 bit)
access : read-write
Enumeration:
#000000 : 000000
no delay
#000001 : 000001
1 CKIL clock period delay
#111111 : 111111
63 CKIL clock periods delay
End of enumeration elements list.
RBC_EN : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#1 : 1
REG_BYPASS_COUNTER enabled.
#0 : 0
REG_BYPASS_COUNTER disabled
End of enumeration elements list.
CCM Arm Clock Root Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
arm_podf : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
CCM Bus Clock Divider Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
periph2_clk2_podf : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
fabric_mmdc_podf : no description available
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
ocram_clk_sel : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Periph_clk output will be used as OCRAM clock root
#1 : 1
AXI alternative clock will be used as OCRAM clock root
End of enumeration elements list.
ocram_alt_clk_sel : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL2 PFD2 will be selected as alternative clock for OCRAM root clock
#1 : 1
PLL3 PFD1 will be selected as alternative clock for OCRAM root clock
End of enumeration elements list.
ipg_podf : no description available
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
divide by 1
#01 : 01
divide by 2
#10 : 10
divide by 3
#11 : 11
divide by 4
End of enumeration elements list.
ahb_podf : no description available
bits : 10 - 12 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
ocram_podf : no description available
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
periph_clk_sel : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL2 (pll2_main_clk)
#1 : 1
derive clock from periph_clk2_clk clock source.
End of enumeration elements list.
periph2_clk_sel : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL2 (pll2_main_clk)
#1 : 1
derive clock from periph2_clk2_clk clock source.
End of enumeration elements list.
periph_clk2_podf : no description available
bits : 27 - 29 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
CCM Bus Clock Multiplexer Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
gpu_core_sel : no description available
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from PLL3 PFD1 clk
#01 : 01
derive clock from PLL3 PFD0
#10 : 10
derive clock from PLL2
#11 : 11
derive clock from PLL2 PFD2
End of enumeration elements list.
gpu_axi_sel : no description available
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from PLL2 PFD2 clk
#01 : 01
derive clock from PLL3 PFD0
#10 : 10
derive clock from PLL3 PFD1
#11 : 11
derive clock from PLL2
End of enumeration elements list.
pcie_axi_clk_sel : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
derive clock from AXI clock
#1 : 1
derive clock from AHB clock
End of enumeration elements list.
periph_clk2_sel : no description available
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from pll3_sw_clk
#01 : 01
derive clock from osc_clk (pll1_ref_clk)
#10 : 10
derive clock from PLL2 (pll2_main_clk)
End of enumeration elements list.
pre_periph_clk_sel : no description available
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from PLL2
#01 : 01
derive clock from PLL2 PFD2
#10 : 10
derive clock from PLL2 PFD0
#11 : 11
derive clock from divided (/2) PLL2 PFD2
End of enumeration elements list.
periph2_clk2_sel : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
derive clock from pll3_sw_clk
#1 : 1
derive clock fromOSC
End of enumeration elements list.
pre_periph2_clk_sel : no description available
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from PLL2
#01 : 01
derive clock from PLL2 PFD2
#10 : 10
derive clock from PLL2 PFD0
#11 : 11
derive clock from PLL4
End of enumeration elements list.
lcdif1_podf : no description available
bits : 23 - 25 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
gpu_axi_podf : no description available
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
gpu_core_podf : no description available
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
CCM Serial Clock Multiplexer Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
perclk_podf : no description available
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
perclk_clk_sel : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
derive clock from ipg clk root
#1 : 1
derive clock from osc_clk
End of enumeration elements list.
qspi1_sel : no description available
bits : 7 - 9 (3 bit)
access : read-write
Enumeration:
#000 : 000
Derive clock from PLL3
#001 : 001
Derive clock from PLL2 PFD0
#010 : 010
Derive clock from PLL2 PFD2
#011 : 011
Derive clock from PLL2
#100 : 100
Derive clock from PLL3 PFD3
#101 : 101
Derive clock from PLL3 PFD2
End of enumeration elements list.
ssi1_clk_sel : no description available
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from PLL3 PFD2
#01 : 01
derive clock from PLL5
#10 : 10
derive clock from PLL4
End of enumeration elements list.
ssi2_clk_sel : no description available
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from PLL3 PFD2
#01 : 01
derive clock from PLL5
#10 : 10
derive clock from PLL4
End of enumeration elements list.
ssi3_clk_sel : no description available
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from PLL3 PFD2
#01 : 01
derive clock from PLL5
#10 : 10
derive clock from PLL4
End of enumeration elements list.
usdhc1_clk_sel : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
derive clock from PLL2 PFD2
#1 : 1
derive clock from PLL2 PFD0
End of enumeration elements list.
usdhc2_clk_sel : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
derive clock from PLL2 PFD2
#1 : 1
derive clock from PLL2 PFD0
End of enumeration elements list.
usdhc3_clk_sel : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
derive clock from PLL2 PFD2
#1 : 1
derive clock from PLL2 PFD0
End of enumeration elements list.
usdhc4_clk_sel : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
derive clock from PLL2 PFD2
#1 : 1
derive clock from PLL2 PFD0
End of enumeration elements list.
lcdif2_podf : no description available
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
aclk_eim_slow_podf : no description available
bits : 23 - 25 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
qspi1_podf : no description available
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#111 : 111
divide by 8
End of enumeration elements list.
aclk_eim_slow_sel : no description available
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from AXI
#01 : 01
derive clock from pll3_sw_clk
#10 : 10
derive clock from PLL2 PFD2
#11 : 11
derive clock from PLL3 PFD0
End of enumeration elements list.
CCM Serial Clock Multiplexer Register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
can_clk_podf : no description available
bits : 2 - 7 (6 bit)
access : read-write
Enumeration:
#000000 : 000000
divide by 1
#000111 : 000111
divide by 8
#111111 : 111111
divide by 2^6
End of enumeration elements list.
can_clk_sel : no description available
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from pll3_sw_clk divided clock (60M)
#01 : 01
derive clock from osc_clk (24M)
#10 : 10
derive clock from pll3_sw_clk divided clock (80M)
#11 : 11
Disable FlexCAN clock
End of enumeration elements list.
ldb_di0_div : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
divide by 3.5
#1 : 1
divide by 7
End of enumeration elements list.
ldb_di1_div : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
divide by 3.5
#1 : 1
divide by 7
End of enumeration elements list.
esai_clk_sel : no description available
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from PLL4 clock
#01 : 01
derive clock from PLL3 PFD2 clock
#10 : 10
derive clock from PLL5 clock
#11 : 11
derive clock from pll3_sw_clk
End of enumeration elements list.
vid_clk_sel : no description available
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
#000 : 000
PLL3 PFD1
#001 : 001
PLL3
#010 : 010
PLL3 PFD3
#011 : 011
PLL4
#100 : 100
PLL5
End of enumeration elements list.
vid_clk_pre_podf : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
divide by 1
#01 : 01
divide by 2
#10 : 10
divide by 3
#11 : 11
divide by 4
End of enumeration elements list.
vid_clk_podf : no description available
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
CCM Serial Clock Divider Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
uart_clk_podf : no description available
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#000000 : 000000
divide by 1
#111111 : 111111
divide by 2^6
End of enumeration elements list.
uart_clk_sel : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
derive clock from pll3_80m
#1 : 1
derive clock from osc_clk
End of enumeration elements list.
usdhc1_podf : no description available
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
usdhc2_podf : no description available
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
usdhc3_podf : no description available
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
usdhc4_podf : no description available
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
CCM SSI1 Clock Divider Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ssi1_clk_podf : no description available
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#000000 : 000000
divide by 1
#111111 : 111111
divide by 2^6
End of enumeration elements list.
ssi1_clk_pred : no description available
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
esai_clk_pred : no description available
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
ssi3_clk_podf : no description available
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
#000000 : 000000
divide by 1
#111111 : 111111
divide by 2^6
End of enumeration elements list.
ssi3_clk_pred : no description available
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
esai_clk_podf : no description available
bits : 25 - 27 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
CCM SSI2 Clock Divider Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ssi2_clk_podf : no description available
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#000000 : 000000
divide by 1
#111111 : 111111
divide by 2^6
End of enumeration elements list.
ssi2_clk_pred : no description available
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
ldb_di0_clk_sel : no description available
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 000
PLL5 clock
#001 : 001
PLL2 PFD0
#010 : 010
PLL2 PFD2
#011 : 011
PLL2 PFD3
#100 : 100
PLL2 PFD1
#101 : 101
PLL3 PFD3
End of enumeration elements list.
ldb_di1_clk_sel : no description available
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 000
derive clock from pll3_sw_clk
#001 : 001
derive clock from PLL2 PFD0
#010 : 010
derive clock from PLL2 PFD2
#011 : 011
derive clock from PLL2
#100 : 100
derive clock from PLL3 PFD3
#101 : 101
derive clock from PLL3 PFD2
End of enumeration elements list.
qspi2_clk_sel : no description available
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
#000 : 000
derive clock from PLL2 PFD0
#001 : 001
derive clock from PLL2
#010 : 010
derive clock from pll3_sw_clk
#011 : 011
derive clock from PLL2 PFD2
#100 : 100
derive clock from PLL3 PFD3
End of enumeration elements list.
qspi2_clk_pred : no description available
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
qspi2_clk_podf : no description available
bits : 21 - 26 (6 bit)
access : read-write
Enumeration:
#000000 : 000000
divide by 1
#000001 : 000001
divide by 2
#111111 : 111111
divide by 2^6
End of enumeration elements list.
CCM D1 Clock Divider Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
audio_clk_sel : no description available
bits : 7 - 8 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from PLL4
#01 : 01
derive clock from PLL3 PFD2
#10 : 10
derive clock from PLL5
#11 : 11
derive clock from PLL3
End of enumeration elements list.
audio_clk_podf : no description available
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#111 : 111
divide by 8
End of enumeration elements list.
audio_clk_pred : no description available
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1 (do not use with high input frequencies)
#001 : 001
divide by 2
#010 : 010
divide by 3
#111 : 111
divide by 8
End of enumeration elements list.
spdif0_clk_sel : no description available
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from PLL4
#01 : 01
derive clock from PLL3 PFD2
#10 : 10
derive clock from PLL5
#11 : 11
derive clock from pll3_sw_clk
End of enumeration elements list.
spdif0_clk_podf : no description available
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#111 : 111
divide by 8
End of enumeration elements list.
spdif0_clk_pred : no description available
bits : 25 - 27 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1 (do not use with high input frequencies)
#001 : 001
divide by 2
#010 : 010
divide by 3
#111 : 111
divide by 8
End of enumeration elements list.
CCM HSC Clock Divider Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
m4_clk_sel : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
derive clock from divided pre-muxed M4 clock
#001 : 001
derive clock from ipp_di0_clk
#010 : 010
derive clock from ipp_di1_clk
#011 : 011
derive clock from ldb_di0_clk
#100 : 100
derive clock from ldb_di1_clk
End of enumeration elements list.
m4_podf : no description available
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
m4_pre_clk_sel : no description available
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
#000 : 000
derive clock from PLL2
#001 : 001
derive clock from pll3_sw_clk
#010 : 010
derive clock from osc_clk (24M)
#011 : 011
derive clock from PLL2 PFD0
#100 : 100
derive clock from PLL2 PFD2
#101 : 101
derive clock from PLL3 PFD3
End of enumeration elements list.
enet_clk_sel : no description available
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 000
derive clock from divided pre-muxed ENET clock
#001 : 001
derive clock from ipp_di0_clk
#010 : 010
derive clock from ipp_di1_clk
#011 : 011
derive clock from ldb_di0_clk
#100 : 100
derive clock from ldb_di1_clk
End of enumeration elements list.
enet_podf : no description available
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
enet_pre_clk_sel : no description available
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
#000 : 000
derive clock from PLL2
#001 : 001
derive clock from pll3_sw_clk
#010 : 010
derive clock from PLL5
#011 : 011
derive clock from PLL2 PFD0
#100 : 100
derive clock from PLL2 PFD2
#101 : 101
derive clock from PLL3 PFD2
End of enumeration elements list.
CCM Serial Clock Divider Register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
lcdif2_clk_sel : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
derive clock from divided pre-muxed lcdif2 clock
#001 : 001
derive clock from ipp_di0_clk
#010 : 010
derive clock from ipp_di1_clk
#011 : 011
derive clock from ldb_di0_clk
#100 : 100
derive clock from ldb_di1_clk
End of enumeration elements list.
lcdif2_pred : no description available
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
lcdif2_pre_clk_sel : no description available
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
#000 : 000
derive clock from PLL2
#001 : 001
derive clock from PLL3 PFD3
#010 : 010
derive clock from PLL5
#011 : 011
derive clock from PLL2 PFD0
#100 : 100
derive clock from PLL2 PFD3
#101 : 101
derive clock from PLL3 PFD1
End of enumeration elements list.
lcdif1_clk_sel : no description available
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 000
derive clock from divided pre-muxed lcdif1 clock
#001 : 001
derive clock from ipp_di0_clk
#010 : 010
derive clock from ipp_di1_clk
#011 : 011
derive clock from ldb_di0_clk
#100 : 100
derive clock from ldb_di1_clk
End of enumeration elements list.
lcdif1_pred : no description available
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
lcdif1_pre_clk_sel : no description available
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
#000 : 000
derive clock from PLL2
#001 : 001
derive clock from PLL3 PFD3
#010 : 010
derive clock from PLL5
#011 : 011
derive clock from PLL2 PFD0
#100 : 100
derive clock from PLL2 PFD1
#101 : 101
derive clock from PLL3 PFD1
End of enumeration elements list.
ecspi_clk_sel : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
derive clock from pll3_60m
#1 : 1
derive clock from osc_clk
End of enumeration elements list.
ecspi_clk_podf : no description available
bits : 19 - 24 (6 bit)
access : read-write
Enumeration:
#000000 : 000000
divide by 1
#111111 : 111111
divide by 2^6
End of enumeration elements list.
CCM Serial Clock Divider Register 3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
csi_clk_sel : no description available
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from osc_clk (24M)
#01 : 01
derive clock from PLL2 PFD2
#10 : 10
derive clock from pll3_120M
#11 : 11
derive clock from PLL3 PFD1
End of enumeration elements list.
csi_podf : no description available
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
display_clk_sel : no description available
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
derive clock from PLL2
#01 : 01
derive clock from PLL2 PFD2
#10 : 10
derive clock from PLL3
#11 : 11
derive clock from PLL3 PFD1
End of enumeration elements list.
display_podf : no description available
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
CCM Control Divider Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mmdc_mask : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
allow handshake with mmdc module
#1 : 1
mask handshake with mmdc. Request signal will not be generated.
End of enumeration elements list.
CCM Wakeup Detector Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CCM Divider Handshake In-Process Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ocram_podf_busy : no description available
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
divider is not busy and its value represents the actual division.
#1 : 1
divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ocram_podf will be applied.
End of enumeration elements list.
ahb_podf_busy : no description available
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
divider is not busy and its value represents the actual division.
#1 : 1
divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied.
End of enumeration elements list.
mmdc_podf_busy : no description available
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
divider is not busy and its value represents the actual division.
#1 : 1
divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the mmdc_axi_podf will be applied.
End of enumeration elements list.
periph2_clk_sel_busy : no description available
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
mux is not busy and its value represents the actual division.
#1 : 1
mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied.
End of enumeration elements list.
periph_clk_sel_busy : no description available
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
mux is not busy and its value represents the actual division.
#1 : 1
mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied.
End of enumeration elements list.
arm_podf_busy : no description available
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
divider is not busy and its value represents the actual division.
#1 : 1
divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied.
End of enumeration elements list.
CCM Low Power Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPM : no description available
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Remain in run mode
#01 : 01
Transfer to wait mode
#10 : 10
Transfer to stop mode
End of enumeration elements list.
ARM_clk_dis_on_lpm : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
ARM clock enabled on wait mode.
#1 : 1
ARM clock disabled on wait mode. .
End of enumeration elements list.
SBYOS : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0')
#1 : 1
On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process.
End of enumeration elements list.
dis_ref_osc : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.
#1 : 1
external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'
End of enumeration elements list.
VSTBY : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')
#1 : 1
Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').
End of enumeration elements list.
stby_count : no description available
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 00
CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles
#01 : 01
CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles
#10 : 10
CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles
#11 : 11
CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles
End of enumeration elements list.
cosc_pwrdown : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.
#1 : 1
On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.
End of enumeration elements list.
bypass_mmdc_lpm_hs : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
handshake with mmdc on next entrance to low power mode will be performed. .
#1 : 1
handshake with mmdc on next entrance to low power mode will be bypassed.
End of enumeration elements list.
mask_core0_wfi : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
WFI of core0 is not masked
#1 : 1
WFI of core0 is masked
End of enumeration elements list.
mask_scu_idle : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#1 : 1
SCU IDLE is masked
#0 : 0
SCU IDLE is not masked
End of enumeration elements list.
mask_l2cc_idle : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#1 : 1
L2CC IDLE is masked
#0 : 0
L2CC IDLE is not masked
End of enumeration elements list.
CCM Interrupt Status Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
lrf_pll : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs
#1 : 1
interrupt generated due to lock ready of all enabled and not bypaseed PLLs
End of enumeration elements list.
cosc_ready : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
interrupt is not generated due to on board oscillator ready
#1 : 1
interrupt generated due to on board oscillator ready
End of enumeration elements list.
ocram_podf_loaded : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
interrupt is not generated due to frequency change of ocram_podf
#1 : 1
interrupt generated due to frequency change of ocram_podf
End of enumeration elements list.
periph2_clk_sel_loaded : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
interrupt is not generated due to frequency change of periph2_clk_sel
#1 : 1
interrupt generated due to frequency change of periph2_clk_sel
End of enumeration elements list.
ahb_podf_loaded : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
interrupt is not generated due to frequency change of ahb_podf
#1 : 1
interrupt generated due to frequency change of ahb_podf
End of enumeration elements list.
mmdc_podf_loaded : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
interrupt is not generated due to frequency change of mmdc_podf_ loaded
#1 : 1
interrupt generated due to frequency change of mmdc_podf_ loaded
End of enumeration elements list.
periph_clk_sel_loaded : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
interrupt is not generated due to update of periph_clk_sel.
#1 : 1
interrupt generated due to update of periph_clk_sel.
End of enumeration elements list.
arm_podf_loaded : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
interrupt is not generated due to frequency change of arm_podf
#1 : 1
interrupt generated due to frequency change of arm_podf
End of enumeration elements list.
CCM Interrupt Mask Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mask_lrf_pll : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't mask interrupt due to lrf of PLLs - interrupt will be created
#1 : 1
mask interrupt due to lrf of PLLs
End of enumeration elements list.
mask_cosc_ready : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't mask interrupt due to on board oscillator ready - interrupt will be created
#1 : 1
mask interrupt due to on board oscillator ready
End of enumeration elements list.
mask_ocram_podf_loaded : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't mask interrupt due to frequency change of ocram_podf - interrupt will be created
#1 : 1
mask interrupt due to frequency change of ocram_podf
End of enumeration elements list.
mask_periph2_clk_sel_loaded : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't mask interrupt due to update of periph2_clk_sel - interrupt will be created
#1 : 1
mask interrupt due to update of periph2_clk_sel
End of enumeration elements list.
mask_ahb_podf_loaded : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't mask interrupt due to frequency change of ahb_podf - interrupt will be created
#1 : 1
mask interrupt due to frequency change of ahb_podf
End of enumeration elements list.
mask_mmdc_podf_loaded : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't mask interrupt due to update of mask_mmdc_podf - interrupt will be created
#1 : 1
mask interrupt due to update of mask_mmdc_podf
End of enumeration elements list.
mask_periph_clk_sel_loaded : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't mask interrupt due to update of periph_clk_sel - interrupt will be created
#1 : 1
mask interrupt due to update of periph_clk_sel
End of enumeration elements list.
arm_podf_loaded : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't mask interrupt due to frequency change of arm_podf - interrupt will be created
#1 : 1
mask interrupt due to frequency change of arm_podf
End of enumeration elements list.
CCM Clock Output Source Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKO_SEL : no description available
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0100 : 0100
vid_clk_root
#0101 : 0101
ocram_clk_root
#0110 : 0110
qspi2_clk_root
#0111 : 0111
m4_clk_root
#1000 : 1000
enet_axi_clk_root
#1001 : 1001
lcdif2_pix_clk_root
#1010 : 1010
lcdif1_pix_clk_root
#1011 : 1011
ahb_clk_root
#1100 : 1100
ipg_clk_root
#1101 : 1101
perclk_root
#1110 : 1110
ckil_sync_clk_root
#1111 : 1111
pll4_main_clk
End of enumeration elements list.
CLKO1_DIV : no description available
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
CLKO1_EN : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
CCM_CLKO1 disabled.
#1 : 1
CCM_CLKO1 enabled.
End of enumeration elements list.
CLK_OUT_SEL : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
CCM_CLKO1 output drives CCM_CLKO1 clock
#1 : 1
CCM_CLKO1 output drives CCM_CLKO2 clock
End of enumeration elements list.
CLKO2_SEL : no description available
bits : 16 - 20 (5 bit)
access : read-write
Enumeration:
#00001 : 00001
mmdc_clk_root
#00010 : 00010
usdhc4_clk_root
#00011 : 00011
usdhc1_clk_root
#00101 : 00101
wrck_clk_root
#00110 : 00110
ecspi_clk_root
#01000 : 01000
usdhc3_clk_root
#01001 : 01001
pcie_clk_root
#01010 : 01010
arm_clk_root
#01011 : 01011
csi_core
#01100 : 01100
display_axi_clk_root
#01110 : 01110
osc_clk
#10001 : 10001
usdhc2_clk_root
#10010 : 10010
ssi1_clk_root
#10011 : 10011
ssi2_clk_root
#10100 : 10100
ssi3_clk_root
#10101 : 10101
gpu_axi_clk_root
#10111 : 10111
can_clk_root
#11000 : 11000
lvds_clk_root
#11001 : 11001
qspi1_clk_root
#11010 : 11010
esai_clk_root
#11011 : 11011
aclk_eim_slow_clk_root
#11100 : 11100
uart_clk_root
#11101 : 11101
spdif0_clk_root
#11110 : 11110
audio_clk_root
End of enumeration elements list.
CLKO2_DIV : no description available
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
#000 : 000
divide by 1
#001 : 001
divide by 2
#010 : 010
divide by 3
#011 : 011
divide by 4
#100 : 100
divide by 5
#101 : 101
divide by 6
#110 : 110
divide by 7
#111 : 111
divide by 8
End of enumeration elements list.
CLKO2_EN : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
CCM_CLKO2 disabled.
#1 : 1
CCM_CLKO2 enabled.
End of enumeration elements list.
CCM General Purpose Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pmic_delay_scaler : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
clock is not divided
#1 : 1
clock is divided /8
End of enumeration elements list.
mmdc_ext_clk_dis : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#1 : 1
disable during stop mode
#0 : 0
don't disable during stop mode.
End of enumeration elements list.
efuse_prog_supply_gate : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
fuse programing supply voltage is gated off to the efuse module
#1 : 1
allow fuse programing.
End of enumeration elements list.
FPL : Fast PLL enable.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Engage PLL enable default way.
#1 : 1
Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.
End of enumeration elements list.
INT_MEM_CLK_LPM : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the clock to the ARM platform memories when entering Low Power Mode
#1 : 1
Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating)
End of enumeration elements list.
CCM Clock Gating Register 0
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Clock Gating Register 1
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Clock Gating Register 2
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Clock Gating Register 3
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Clock Gating Register 4
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Clock Gating Register 5
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REF_EN_B : no description available
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
value of CCM_REF_EN_B is '0'
#1 : 1
value of CCM_REF_EN_B is '1'
End of enumeration elements list.
cosc_ready : no description available
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
on board oscillator is not ready.
#1 : 1
on board oscillator is ready.
End of enumeration elements list.
CCM Clock Gating Register 6
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Module Enable Overide Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mod_en_ov_gpt : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't override module enable signal
#1 : 1
override module enable signal
End of enumeration elements list.
mod_en_ov_epit : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't override module enable signal
#1 : 1
override module enable signal
End of enumeration elements list.
mod_en_usdhc : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't override module enable signal
#1 : 1
override module enable signal
End of enumeration elements list.
mod_en_ov_gpu : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't override module enable signal
#1 : 1
override module enable signal
End of enumeration elements list.
mod_en_ov_can2_cpi : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't override module enable signal
#1 : 1
override module enable signal
End of enumeration elements list.
mod_en_ov_can1_cpi : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
don't overide module enable signal
#1 : 1
overide module enable signal
End of enumeration elements list.
CCM Clock Switcher Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pll3_sw_clk_sel : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
pll3_main_clk
#1 : 1
pll3 bypass clock
End of enumeration elements list.
pll1_sw_clk_sel : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
pll1_main_clk
#1 : 1
step_clk
End of enumeration elements list.
step_sel : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
derive clock from osc_clk (24M) - source for lp_apm.
#1 : 1
derive clock from PLL2 PFD2
End of enumeration elements list.
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