Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPIT is disabled
#1 : 1
EPIT is enabled
End of enumeration elements list.
ENMOD : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Counter starts counting from the value it had when it was disabled.
#1 : 1
Counter starts count from load value (RLD=1) or 0xFFFF_FFFF (If RLD=0)
End of enumeration elements list.
OCIEN : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare interrupt disabled
#1 : 1
Compare interrupt enabled
End of enumeration elements list.
RLD : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
When the counter reaches zero it rolls over to 0xFFFF_FFFF (free-running mode)
#1 : 1
When the counter reaches zero it reloads from the modulus register (set-and-forget mode)
End of enumeration elements list.
PRESCALAR : no description available
bits : 4 - 15 (12 bit)
access : read-write
Enumeration:
#0 : 0
Divide by 1
#1 : 1
Divide by 2...
#111111111111 : 111111111111
Divide by 4096
End of enumeration elements list.
SWR : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPIT is out of reset
#1 : 1
EPIT is undergoing reset
End of enumeration elements list.
IOVW : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write to load register does not result in counter value being overwritten.
#1 : 1
Write to load register results in immediate overwriting of counter value.
End of enumeration elements list.
DBGEN : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inactive in debug mode
#1 : 1
Active in debug mode
End of enumeration elements list.
WAITEN : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPIT is disabled in wait mode
#1 : 1
EPIT is enabled in wait mode
End of enumeration elements list.
STOPEN : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPIT is disabled in stop mode
#1 : 1
EPIT is enabled in stop mode
End of enumeration elements list.
OM : no description available
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 00
EPIT output is disconnected from pad
#01 : 01
Toggle output pin
#10 : 10
Clear output pin
#11 : 11
Set output pin
End of enumeration elements list.
CLKSRC : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Clock is off
#01 : 01
Peripheral clock
#10 : 10
High-frequency reference clock
#11 : 11
Low-frequency reference clock
End of enumeration elements list.
Counter register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only
Status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCIF : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare event has not occurred
#1 : 1
Compare event occurred
End of enumeration elements list.
Load register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOAD : no description available
bits : 0 - 31 (32 bit)
access : read-write
Compare register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPARE : no description available
bits : 0 - 31 (32 bit)
access : read-write
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