\n

MUB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected

Registers

BTR0

BRR0

BRR1

BRR2

BRR3

BSR

BCR

BTR1

BTR2

BTR3


BTR0

Processor B Transmit Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR0 BTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTR0

BTR0 : no description available
bits : 0 - 31 (32 bit)
access : read-write


BRR0

Processor B Receive Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BRR0 BRR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRR0

BRR0 : no description available
bits : 0 - 31 (32 bit)
access : read-only


BRR1

Processor B Receive Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BRR1 BRR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRR1

BRR1 : no description available
bits : 0 - 31 (32 bit)
access : read-only


BRR2

Processor B Receive Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BRR2 BRR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRR2

BRR2 : no description available
bits : 0 - 31 (32 bit)
access : read-only


BRR3

Processor B Receive Register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BRR3 BRR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRR3

BRR3 : no description available
bits : 0 - 31 (32 bit)
access : read-only


BSR

Processor B Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BSR BSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Fn EP APM ARS FUP TEn RFn GIPn

Fn : no description available
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0 : 0

ABFn bit in ACR register is written 0 (default).

#1 : 1

ABFn bit in ACR register is written 1.

End of enumeration elements list.

EP : no description available
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The Processor B-side event is not pending (default).

#1 : 1

The Processor B-side event is pending.

End of enumeration elements list.

APM : no description available
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

#00 : 00

The System is in Run Mode.

#01 : 01

The System is in WAIT Mode.

#11 : 11

The System is in STOP Mode.

End of enumeration elements list.

ARS : no description available
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The Processor A or the Processor A-side of the MU is not in reset.

#1 : 1

The Processor A or the Processor A-side of the MU is in reset.

End of enumeration elements list.

FUP : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No flags updated, initiated by the Processor B, in progress (default)

#1 : 1

Processor B initiated flags update, processing

End of enumeration elements list.

TEn : no description available
bits : 20 - 23 (4 bit)
access : read-write

Enumeration:

#0 : 0

BTRn register is not empty.

#1 : 1

BTRn register is empty (default).

End of enumeration elements list.

RFn : no description available
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

#0 : 0

BRRn register is not full (default).

#1 : 1

BRRn register has received data from ATRn register and is ready to be read by the Processor B.

End of enumeration elements list.

GIPn : no description available
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

#0 : 0

Processor B general purpose interrupt n is not pending. (default)

#1 : 1

Processor B general purpose interrupt n is pending.

End of enumeration elements list.


BCR

Processor B Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR BCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BAFn GIRn TIEn RIEn GIEn

BAFn : no description available
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0 : 0

Clears the Fn bit in the ASR register.

#1 : 1

Sets the Fn bit in the ASR register.

End of enumeration elements list.

GIRn : no description available
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0 : 0

Processor B General Interrupt n is not requested to the Processor A (default).

#1 : 1

Processor B General Interrupt n is requested to the Processor A.

End of enumeration elements list.

TIEn : no description available
bits : 20 - 23 (4 bit)
access : read-write

Enumeration:

#0 : 0

Disables Processor B Transmit Interrupt n. (default)

#1 : 1

Enables Processor B Transmit Interrupt n.

End of enumeration elements list.

RIEn : no description available
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

#0 : 0

Disables Processor B Receive Interrupt n. (default)

#1 : 1

Enables Processor B Receive Interrupt n.

End of enumeration elements list.

GIEn : no description available
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

#0 : 0

Disables Processor B General Interrupt n. (default)

#1 : 1

Enables Processor B General Interrupt n.

End of enumeration elements list.


BTR1

Processor B Transmit Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR1 BTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTR1

BTR1 : no description available
bits : 0 - 31 (32 bit)
access : read-write


BTR2

Processor B Transmit Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR2 BTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTR2

BTR2 : no description available
bits : 0 - 31 (32 bit)
access : read-write


BTR3

Processor B Transmit Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR3 BTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTR3

BTR3 : no description available
bits : 0 - 31 (32 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.