\n
address_offset : 0x0 Bytes (0x0)
size : 0x134 byte (0x0)
mem_usage : registers
protection : not protected
GPMI Control Register 0 Description
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFER_COUNT : no description available
bits : 0 - 15 (16 bit)
access : read-write
ADDRESS_INCREMENT : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Address does not increment.
#1 : 1
Increment address.
End of enumeration elements list.
ADDRESS : no description available
bits : 17 - 19 (3 bit)
access : read-write
CS : no description available
bits : 20 - 22 (3 bit)
access : read-write
WORD_LENGTH : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#1 : 1
8-bit Data Bus mode.
End of enumeration elements list.
COMMAND_MODE : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Write mode.
#01 : 01
Read Mode.
#10 : 10
Read and Compare Mode (setting sense flop).
#11 : 11
Wait for Ready.
End of enumeration elements list.
UDMA : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use ATA-PIO mode on the external bus.
#1 : 1
Use ATA-Ultra DMA mode on the external bus.
End of enumeration elements list.
LOCK_CS : no description available
bits : 27 - 27 (1 bit)
access : read-write
DEV_IRQ_EN : no description available
bits : 28 - 28 (1 bit)
access : read-write
RUN : no description available
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write
GPMI Compare Register Description
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFERENCE : no description available
bits : 0 - 15 (16 bit)
access : read-write
MASK : no description available
bits : 16 - 31 (16 bit)
access : read-write
GPMI Double Rate Read DLL Control Register Description
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : no description available
bits : 0 - 0 (1 bit)
access : read-write
RESET : no description available
bits : 1 - 1 (1 bit)
access : read-write
SLV_FORCE_UPD : no description available
bits : 2 - 2 (1 bit)
access : read-write
SLV_DLY_TARGET : no description available
bits : 3 - 6 (4 bit)
access : read-write
GATE_UPDATE : no description available
bits : 7 - 7 (1 bit)
access : read-write
REFCLK_ON : no description available
bits : 8 - 8 (1 bit)
access : read-write
SLV_OVERRIDE : no description available
bits : 9 - 9 (1 bit)
access : read-write
SLV_OVERRIDE_VAL : no description available
bits : 10 - 17 (8 bit)
access : read-write
RSVD1 : no description available
bits : 18 - 19 (2 bit)
access : read-only
SLV_UPDATE_INT : no description available
bits : 20 - 27 (8 bit)
access : read-write
REF_UPDATE_INT : no description available
bits : 28 - 31 (4 bit)
access : read-write
GPMI Double Rate Write DLL Control Register Description
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : no description available
bits : 0 - 0 (1 bit)
access : read-write
RESET : no description available
bits : 1 - 1 (1 bit)
access : read-write
SLV_FORCE_UPD : no description available
bits : 2 - 2 (1 bit)
access : read-write
SLV_DLY_TARGET : no description available
bits : 3 - 6 (4 bit)
access : read-write
GATE_UPDATE : no description available
bits : 7 - 7 (1 bit)
access : read-write
REFCLK_ON : no description available
bits : 8 - 8 (1 bit)
access : read-write
SLV_OVERRIDE : no description available
bits : 9 - 9 (1 bit)
access : read-write
SLV_OVERRIDE_VAL : no description available
bits : 10 - 17 (8 bit)
access : read-write
RSVD1 : no description available
bits : 18 - 19 (2 bit)
access : read-only
SLV_UPDATE_INT : no description available
bits : 20 - 27 (8 bit)
access : read-write
REF_UPDATE_INT : no description available
bits : 28 - 31 (4 bit)
access : read-write
GPMI Double Rate Read DLL Status Register Description
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SLV_LOCK : no description available
bits : 0 - 0 (1 bit)
access : read-only
SLV_SEL : no description available
bits : 1 - 8 (8 bit)
access : read-only
RSVD0 : no description available
bits : 9 - 15 (7 bit)
access : read-only
REF_LOCK : no description available
bits : 16 - 16 (1 bit)
access : read-only
REF_SEL : no description available
bits : 17 - 24 (8 bit)
access : read-only
RSVD1 : no description available
bits : 25 - 31 (7 bit)
access : read-only
GPMI Double Rate Write DLL Status Register Description
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SLV_LOCK : no description available
bits : 0 - 0 (1 bit)
access : read-only
SLV_SEL : no description available
bits : 1 - 8 (8 bit)
access : read-only
RSVD0 : no description available
bits : 9 - 15 (7 bit)
access : read-only
REF_LOCK : no description available
bits : 16 - 16 (1 bit)
access : read-only
REF_SEL : no description available
bits : 17 - 24 (8 bit)
access : read-only
RSVD1 : no description available
bits : 25 - 31 (7 bit)
access : read-only
GPMI Integrated ECC Control Register Description
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFFER_MASK : no description available
bits : 0 - 8 (9 bit)
access : read-write
ENABLE_ECC : no description available
bits : 12 - 12 (1 bit)
access : read-write
ECC_CMD : no description available
bits : 13 - 14 (2 bit)
access : read-write
RSVD2 : no description available
bits : 15 - 15 (1 bit)
access : read-write
HANDLE : no description available
bits : 16 - 31 (16 bit)
access : read-write
GPMI Integrated ECC Control Register Description
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFFER_MASK : no description available
bits : 0 - 8 (9 bit)
access : read-write
ENABLE_ECC : no description available
bits : 12 - 12 (1 bit)
access : read-write
ECC_CMD : no description available
bits : 13 - 14 (2 bit)
access : read-write
RSVD2 : no description available
bits : 15 - 15 (1 bit)
access : read-write
HANDLE : no description available
bits : 16 - 31 (16 bit)
access : read-write
GPMI Integrated ECC Control Register Description
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFFER_MASK : no description available
bits : 0 - 8 (9 bit)
access : read-write
ENABLE_ECC : no description available
bits : 12 - 12 (1 bit)
access : read-write
ECC_CMD : no description available
bits : 13 - 14 (2 bit)
access : read-write
RSVD2 : no description available
bits : 15 - 15 (1 bit)
access : read-write
HANDLE : no description available
bits : 16 - 31 (16 bit)
access : read-write
GPMI Integrated ECC Control Register Description
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFFER_MASK : no description available
bits : 0 - 8 (9 bit)
access : read-write
ENABLE_ECC : no description available
bits : 12 - 12 (1 bit)
access : read-write
ECC_CMD : no description available
bits : 13 - 14 (2 bit)
access : read-write
RSVD2 : no description available
bits : 15 - 15 (1 bit)
access : read-write
HANDLE : no description available
bits : 16 - 31 (16 bit)
access : read-write
GPMI Integrated ECC Transfer Count Register Description
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : no description available
bits : 0 - 15 (16 bit)
access : read-write
GPMI Control Register 0 Description
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFER_COUNT : no description available
bits : 0 - 15 (16 bit)
access : read-write
ADDRESS_INCREMENT : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Address does not increment.
#1 : 1
Increment address.
End of enumeration elements list.
ADDRESS : no description available
bits : 17 - 19 (3 bit)
access : read-write
CS : no description available
bits : 20 - 22 (3 bit)
access : read-write
WORD_LENGTH : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#1 : 1
8-bit Data Bus mode.
End of enumeration elements list.
COMMAND_MODE : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Write mode.
#01 : 01
Read Mode.
#10 : 10
Read and Compare Mode (setting sense flop).
#11 : 11
Wait for Ready.
End of enumeration elements list.
UDMA : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use ATA-PIO mode on the external bus.
#1 : 1
Use ATA-Ultra DMA mode on the external bus.
End of enumeration elements list.
LOCK_CS : no description available
bits : 27 - 27 (1 bit)
access : read-write
DEV_IRQ_EN : no description available
bits : 28 - 28 (1 bit)
access : read-write
RUN : no description available
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write
GPMI Payload Address Register Description
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : no description available
bits : 0 - 1 (2 bit)
access : read-only
ADDRESS : no description available
bits : 2 - 31 (30 bit)
access : read-write
GPMI Auxiliary Address Register Description
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : no description available
bits : 0 - 1 (2 bit)
access : read-only
ADDRESS : no description available
bits : 2 - 31 (30 bit)
access : read-write
GPMI Control Register 1 Description
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPMI_MODE : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
NAND mode.
#1 : 1
ATA mode.
End of enumeration elements list.
CAMERA_MODE : no description available
bits : 1 - 1 (1 bit)
access : read-write
ATA_IRQRDY_POLARITY : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
#1 : 1
External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
End of enumeration elements list.
DEV_RESET : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
NANDF_WP_B pin is held low (asserted).
#1 : 1
NANDF_WP_B pin is held high (de-asserted).
End of enumeration elements list.
ABORT_WAIT_FOR_READY_CHANNEL : no description available
bits : 4 - 6 (3 bit)
access : read-write
ABORT_WAIT_REQUEST : no description available
bits : 7 - 7 (1 bit)
access : read-write
BURST_EN : no description available
bits : 8 - 8 (1 bit)
access : read-write
TIMEOUT_IRQ : no description available
bits : 9 - 9 (1 bit)
access : read-write
DEV_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write
DMA2ECC_MODE : no description available
bits : 11 - 11 (1 bit)
access : read-write
RDN_DELAY : no description available
bits : 12 - 15 (4 bit)
access : read-write
HALF_PERIOD : no description available
bits : 16 - 16 (1 bit)
access : read-write
DLL_ENABLE : no description available
bits : 17 - 17 (1 bit)
access : read-write
BCH_MODE : no description available
bits : 18 - 18 (1 bit)
access : read-write
GANGED_RDYBUSY : no description available
bits : 19 - 19 (1 bit)
access : read-write
TIMEOUT_IRQ_EN : no description available
bits : 20 - 20 (1 bit)
access : read-write
TEST_TRIGGER : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
WRN_DLY_SEL : no description available
bits : 22 - 23 (2 bit)
access : read-write
DECOUPLE_CS : no description available
bits : 24 - 24 (1 bit)
access : read-write
SSYNCMODE : no description available
bits : 25 - 25 (1 bit)
access : read-write
UPDATE_CS : no description available
bits : 26 - 26 (1 bit)
access : read-write
GPMI_CLK_DIV2_EN : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
internal factor-2 clock divider is disabled
#1 : 1
internal factor-2 clock divider is enabled.
End of enumeration elements list.
TOGGLE_MODE : no description available
bits : 28 - 28 (1 bit)
access : read-write
WRITE_CLK_STOP : no description available
bits : 29 - 29 (1 bit)
access : read-write
SSYNC_CLK_STOP : no description available
bits : 30 - 30 (1 bit)
access : read-write
DEV_CLK_STOP : no description available
bits : 31 - 31 (1 bit)
access : read-write
GPMI Control Register 1 Description
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPMI_MODE : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
NAND mode.
#1 : 1
ATA mode.
End of enumeration elements list.
CAMERA_MODE : no description available
bits : 1 - 1 (1 bit)
access : read-write
ATA_IRQRDY_POLARITY : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
#1 : 1
External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
End of enumeration elements list.
DEV_RESET : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
NANDF_WP_B pin is held low (asserted).
#1 : 1
NANDF_WP_B pin is held high (de-asserted).
End of enumeration elements list.
ABORT_WAIT_FOR_READY_CHANNEL : no description available
bits : 4 - 6 (3 bit)
access : read-write
ABORT_WAIT_REQUEST : no description available
bits : 7 - 7 (1 bit)
access : read-write
BURST_EN : no description available
bits : 8 - 8 (1 bit)
access : read-write
TIMEOUT_IRQ : no description available
bits : 9 - 9 (1 bit)
access : read-write
DEV_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write
DMA2ECC_MODE : no description available
bits : 11 - 11 (1 bit)
access : read-write
RDN_DELAY : no description available
bits : 12 - 15 (4 bit)
access : read-write
HALF_PERIOD : no description available
bits : 16 - 16 (1 bit)
access : read-write
DLL_ENABLE : no description available
bits : 17 - 17 (1 bit)
access : read-write
BCH_MODE : no description available
bits : 18 - 18 (1 bit)
access : read-write
GANGED_RDYBUSY : no description available
bits : 19 - 19 (1 bit)
access : read-write
TIMEOUT_IRQ_EN : no description available
bits : 20 - 20 (1 bit)
access : read-write
TEST_TRIGGER : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
WRN_DLY_SEL : no description available
bits : 22 - 23 (2 bit)
access : read-write
DECOUPLE_CS : no description available
bits : 24 - 24 (1 bit)
access : read-write
SSYNCMODE : no description available
bits : 25 - 25 (1 bit)
access : read-write
UPDATE_CS : no description available
bits : 26 - 26 (1 bit)
access : read-write
GPMI_CLK_DIV2_EN : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
internal factor-2 clock divider is disabled
#1 : 1
internal factor-2 clock divider is enabled.
End of enumeration elements list.
TOGGLE_MODE : no description available
bits : 28 - 28 (1 bit)
access : read-write
WRITE_CLK_STOP : no description available
bits : 29 - 29 (1 bit)
access : read-write
SSYNC_CLK_STOP : no description available
bits : 30 - 30 (1 bit)
access : read-write
DEV_CLK_STOP : no description available
bits : 31 - 31 (1 bit)
access : read-write
GPMI Control Register 1 Description
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPMI_MODE : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
NAND mode.
#1 : 1
ATA mode.
End of enumeration elements list.
CAMERA_MODE : no description available
bits : 1 - 1 (1 bit)
access : read-write
ATA_IRQRDY_POLARITY : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
#1 : 1
External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
End of enumeration elements list.
DEV_RESET : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
NANDF_WP_B pin is held low (asserted).
#1 : 1
NANDF_WP_B pin is held high (de-asserted).
End of enumeration elements list.
ABORT_WAIT_FOR_READY_CHANNEL : no description available
bits : 4 - 6 (3 bit)
access : read-write
ABORT_WAIT_REQUEST : no description available
bits : 7 - 7 (1 bit)
access : read-write
BURST_EN : no description available
bits : 8 - 8 (1 bit)
access : read-write
TIMEOUT_IRQ : no description available
bits : 9 - 9 (1 bit)
access : read-write
DEV_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write
DMA2ECC_MODE : no description available
bits : 11 - 11 (1 bit)
access : read-write
RDN_DELAY : no description available
bits : 12 - 15 (4 bit)
access : read-write
HALF_PERIOD : no description available
bits : 16 - 16 (1 bit)
access : read-write
DLL_ENABLE : no description available
bits : 17 - 17 (1 bit)
access : read-write
BCH_MODE : no description available
bits : 18 - 18 (1 bit)
access : read-write
GANGED_RDYBUSY : no description available
bits : 19 - 19 (1 bit)
access : read-write
TIMEOUT_IRQ_EN : no description available
bits : 20 - 20 (1 bit)
access : read-write
TEST_TRIGGER : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
WRN_DLY_SEL : no description available
bits : 22 - 23 (2 bit)
access : read-write
DECOUPLE_CS : no description available
bits : 24 - 24 (1 bit)
access : read-write
SSYNCMODE : no description available
bits : 25 - 25 (1 bit)
access : read-write
UPDATE_CS : no description available
bits : 26 - 26 (1 bit)
access : read-write
GPMI_CLK_DIV2_EN : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
internal factor-2 clock divider is disabled
#1 : 1
internal factor-2 clock divider is enabled.
End of enumeration elements list.
TOGGLE_MODE : no description available
bits : 28 - 28 (1 bit)
access : read-write
WRITE_CLK_STOP : no description available
bits : 29 - 29 (1 bit)
access : read-write
SSYNC_CLK_STOP : no description available
bits : 30 - 30 (1 bit)
access : read-write
DEV_CLK_STOP : no description available
bits : 31 - 31 (1 bit)
access : read-write
GPMI Control Register 1 Description
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPMI_MODE : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
NAND mode.
#1 : 1
ATA mode.
End of enumeration elements list.
CAMERA_MODE : no description available
bits : 1 - 1 (1 bit)
access : read-write
ATA_IRQRDY_POLARITY : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
#1 : 1
External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
End of enumeration elements list.
DEV_RESET : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
NANDF_WP_B pin is held low (asserted).
#1 : 1
NANDF_WP_B pin is held high (de-asserted).
End of enumeration elements list.
ABORT_WAIT_FOR_READY_CHANNEL : no description available
bits : 4 - 6 (3 bit)
access : read-write
ABORT_WAIT_REQUEST : no description available
bits : 7 - 7 (1 bit)
access : read-write
BURST_EN : no description available
bits : 8 - 8 (1 bit)
access : read-write
TIMEOUT_IRQ : no description available
bits : 9 - 9 (1 bit)
access : read-write
DEV_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write
DMA2ECC_MODE : no description available
bits : 11 - 11 (1 bit)
access : read-write
RDN_DELAY : no description available
bits : 12 - 15 (4 bit)
access : read-write
HALF_PERIOD : no description available
bits : 16 - 16 (1 bit)
access : read-write
DLL_ENABLE : no description available
bits : 17 - 17 (1 bit)
access : read-write
BCH_MODE : no description available
bits : 18 - 18 (1 bit)
access : read-write
GANGED_RDYBUSY : no description available
bits : 19 - 19 (1 bit)
access : read-write
TIMEOUT_IRQ_EN : no description available
bits : 20 - 20 (1 bit)
access : read-write
TEST_TRIGGER : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
WRN_DLY_SEL : no description available
bits : 22 - 23 (2 bit)
access : read-write
DECOUPLE_CS : no description available
bits : 24 - 24 (1 bit)
access : read-write
SSYNCMODE : no description available
bits : 25 - 25 (1 bit)
access : read-write
UPDATE_CS : no description available
bits : 26 - 26 (1 bit)
access : read-write
GPMI_CLK_DIV2_EN : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
internal factor-2 clock divider is disabled
#1 : 1
internal factor-2 clock divider is enabled.
End of enumeration elements list.
TOGGLE_MODE : no description available
bits : 28 - 28 (1 bit)
access : read-write
WRITE_CLK_STOP : no description available
bits : 29 - 29 (1 bit)
access : read-write
SSYNC_CLK_STOP : no description available
bits : 30 - 30 (1 bit)
access : read-write
DEV_CLK_STOP : no description available
bits : 31 - 31 (1 bit)
access : read-write
GPMI Timing Register 0 Description
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_SETUP : no description available
bits : 0 - 7 (8 bit)
access : read-write
DATA_HOLD : no description available
bits : 8 - 15 (8 bit)
access : read-write
ADDRESS_SETUP : no description available
bits : 16 - 23 (8 bit)
access : read-write
RSVD1 : no description available
bits : 24 - 31 (8 bit)
access : write-only
GPMI Control Register 0 Description
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFER_COUNT : no description available
bits : 0 - 15 (16 bit)
access : read-write
ADDRESS_INCREMENT : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Address does not increment.
#1 : 1
Increment address.
End of enumeration elements list.
ADDRESS : no description available
bits : 17 - 19 (3 bit)
access : read-write
CS : no description available
bits : 20 - 22 (3 bit)
access : read-write
WORD_LENGTH : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#1 : 1
8-bit Data Bus mode.
End of enumeration elements list.
COMMAND_MODE : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Write mode.
#01 : 01
Read Mode.
#10 : 10
Read and Compare Mode (setting sense flop).
#11 : 11
Wait for Ready.
End of enumeration elements list.
UDMA : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use ATA-PIO mode on the external bus.
#1 : 1
Use ATA-Ultra DMA mode on the external bus.
End of enumeration elements list.
LOCK_CS : no description available
bits : 27 - 27 (1 bit)
access : read-write
DEV_IRQ_EN : no description available
bits : 28 - 28 (1 bit)
access : read-write
RUN : no description available
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write
GPMI Timing Register 1 Description
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD1 : no description available
bits : 0 - 15 (16 bit)
access : read-only
DEVICE_BUSY_TIMEOUT : no description available
bits : 16 - 31 (16 bit)
access : read-write
GPMI Timing Register 2 Description
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA_PAUSE : no description available
bits : 0 - 3 (4 bit)
access : read-write
CMDADD_PAUSE : no description available
bits : 4 - 7 (4 bit)
access : read-write
POSTAMBLE_DELAY : no description available
bits : 8 - 11 (4 bit)
access : read-write
PREAMBLE_DELAY : no description available
bits : 12 - 15 (4 bit)
access : read-write
CE_DELAY : no description available
bits : 16 - 20 (5 bit)
access : read-write
RSVD0 : no description available
bits : 21 - 23 (3 bit)
access : read-only
READ_LATENCY : no description available
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
READ LATENCY is 0
#001 : 001
READ LATENCY is 1
#010 : 010
READ LATENCY is 2
#011 : 011
READ LATENCY is 3
#100 : 100
READ LATENCY is 4
#101 : 101
READ LATENCY is 5
End of enumeration elements list.
TCR : no description available
bits : 27 - 28 (2 bit)
access : read-write
TRPSTH : no description available
bits : 29 - 31 (3 bit)
access : read-write
GPMI DMA Data Transfer Register Description
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : no description available
bits : 0 - 31 (32 bit)
access : read-write
GPMI Status Register Description
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRESENT : no description available
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
GPMI is not present in this product.
#1 : 1
GPMI is present is in this product.
End of enumeration elements list.
FIFO_FULL : no description available
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
FIFO is not full.
#1 : 1
FIFO is full.
End of enumeration elements list.
FIFO_EMPTY : no description available
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
FIFO is not empty.
#1 : 1
FIFO is empty.
End of enumeration elements list.
INVALID_BUFFER_MASK : no description available
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
ECC Buffer Mask is not invalid.
#1 : 1
ECC Buffer Mask is invalid.
End of enumeration elements list.
ATA_IRQ : no description available
bits : 4 - 4 (1 bit)
access : read-only
RSVD1 : no description available
bits : 5 - 7 (3 bit)
access : read-only
DEV0_ERROR : no description available
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error condition present on ATA/NAND Device accessed by DMA channel 0.
#1 : 1
An Error has occurred on ATA/NAND Device accessed by
End of enumeration elements list.
DEV1_ERROR : no description available
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error condition present on ATA/NAND Device accessed by DMA channel 1.
#1 : 1
An Error has occurred on ATA/NAND Device accessed by
End of enumeration elements list.
DEV2_ERROR : no description available
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error condition present on ATA/NAND Device accessed by DMA channel 2.
#1 : 1
An Error has occurred on ATA/NAND Device accessed by
End of enumeration elements list.
DEV3_ERROR : no description available
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error condition present on ATA/NAND Device accessed by DMA channel 3.
#1 : 1
An Error has occurred on ATA/NAND Device accessed by
End of enumeration elements list.
DEV4_ERROR : no description available
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error condition present on ATA/NAND Device accessed by DMA channel 4.
#1 : 1
An Error has occurred on ATA/NAND Device accessed by
End of enumeration elements list.
DEV5_ERROR : no description available
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error condition present on ATA/NAND Device accessed by DMA channel 5.
#1 : 1
An Error has occurred on ATA/NAND Device accessed by
End of enumeration elements list.
DEV6_ERROR : no description available
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error condition present on ATA/NAND Device accessed by DMA channel 6.
#1 : 1
An Error has occurred on ATA/NAND Device accessed by
End of enumeration elements list.
DEV7_ERROR : no description available
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error condition present on ATA/NAND Device accessed by DMA channel 7.
#1 : 1
An Error has occurred on ATA/NAND Device accessed by
End of enumeration elements list.
RDY_TIMEOUT : no description available
bits : 16 - 23 (8 bit)
access : read-only
READY_BUSY : no description available
bits : 24 - 31 (8 bit)
access : read-only
GPMI Control Register 0 Description
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFER_COUNT : no description available
bits : 0 - 15 (16 bit)
access : read-write
ADDRESS_INCREMENT : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Address does not increment.
#1 : 1
Increment address.
End of enumeration elements list.
ADDRESS : no description available
bits : 17 - 19 (3 bit)
access : read-write
CS : no description available
bits : 20 - 22 (3 bit)
access : read-write
WORD_LENGTH : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#1 : 1
8-bit Data Bus mode.
End of enumeration elements list.
COMMAND_MODE : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Write mode.
#01 : 01
Read Mode.
#10 : 10
Read and Compare Mode (setting sense flop).
#11 : 11
Wait for Ready.
End of enumeration elements list.
UDMA : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use ATA-PIO mode on the external bus.
#1 : 1
Use ATA-Ultra DMA mode on the external bus.
End of enumeration elements list.
LOCK_CS : no description available
bits : 27 - 27 (1 bit)
access : read-write
DEV_IRQ_EN : no description available
bits : 28 - 28 (1 bit)
access : read-write
RUN : no description available
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write
GPMI Debug Information Register Description
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMD_END : no description available
bits : 0 - 7 (8 bit)
access : read-only
DMAREQ : no description available
bits : 8 - 15 (8 bit)
access : read-only
DMA_SENSE : no description available
bits : 16 - 23 (8 bit)
access : read-only
WAIT_FOR_READY_END : no description available
bits : 24 - 31 (8 bit)
access : read-only
GPMI Version Register Description
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STEP : no description available
bits : 0 - 15 (16 bit)
access : read-only
MINOR : no description available
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : no description available
bits : 24 - 31 (8 bit)
access : read-only
GPMI Debug2 Information Register Description
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDN_TAP : no description available
bits : 0 - 5 (6 bit)
access : read-only
UPDATE_WINDOW : no description available
bits : 6 - 6 (1 bit)
access : read-only
VIEW_DELAYED_RDN : no description available
bits : 7 - 7 (1 bit)
access : read-write
SYND2GPMI_READY : no description available
bits : 8 - 8 (1 bit)
access : read-only
SYND2GPMI_VALID : no description available
bits : 9 - 9 (1 bit)
access : read-only
GPMI2SYND_READY : no description available
bits : 10 - 10 (1 bit)
access : read-only
GPMI2SYND_VALID : no description available
bits : 11 - 11 (1 bit)
access : read-only
SYND2GPMI_BE : no description available
bits : 12 - 15 (4 bit)
access : read-only
MAIN_STATE : no description available
bits : 16 - 19 (4 bit)
access : read-only
PIN_STATE : no description available
bits : 20 - 22 (3 bit)
access : read-only
BUSY : no description available
bits : 23 - 23 (1 bit)
access : read-only
UDMA_STATE : no description available
bits : 24 - 27 (4 bit)
access : read-only
RSVD1 : no description available
bits : 28 - 31 (4 bit)
access : read-write
GPMI Debug3 Information Register Description
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEV_WORD_CNTR : no description available
bits : 0 - 15 (16 bit)
access : read-only
APB_WORD_CNTR : no description available
bits : 16 - 31 (16 bit)
access : read-only
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